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| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:14:32 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (patch) | |
| tree | d92c7296f82d46d1b2da30933a97595f6cb8ad66 /target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch | |
| parent | a34f96d6cf80c7c3c425076714d9c4caa67e3670 (diff) | |
| download | upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.gz upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.bz2 upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.zip | |
layerscape: add 64b/32b target for ls1043ardb device
Add support for NXP layerscape ls1043ardb 64b/32b Dev board.
LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores.
ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC,
I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc.
64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from
NXP QorIQ SDK release.
All of 4.4 kernel patches porting from SDK release or upstream.
QorIQ SDK ISOs can be downloaded from this location:
http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch b/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch new file mode 100644 index 0000000000..7114fbb3af --- /dev/null +++ b/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch @@ -0,0 +1,46 @@ +From a0a4f406c7e90b2be66e88ea8b21699940c0823f Mon Sep 17 00:00:00 2001 +From: Joao Pinto <Joao.Pinto@synopsys.com> +Date: Thu, 10 Mar 2016 14:44:44 -0600 +Subject: [PATCH 57/70] PCI: designware: Add default link up check if + sub-driver doesn't override + +Add a default DesignWare "link_up" test for use when a sub-driver doesn't +supply its own pcie_host_ops.link_up() method. + +[bhelgaas: changelog, split into its own patch] +Signed-off-by: Joao Pinto <jpinto@synopsys.com> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +Acked-by: Pratyush Anand <pratyush.anand@gmail.com> +--- + drivers/pci/host/pcie-designware.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -70,6 +70,11 @@ + #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) + #define PCIE_ATU_UPPER_TARGET 0x91C + ++/* PCIe Port Logic registers */ ++#define PLR_OFFSET 0x700 ++#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) ++#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010 ++ + static struct pci_ops dw_pcie_ops; + + int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) +@@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_po + + int dw_pcie_link_up(struct pcie_port *pp) + { ++ u32 val; ++ + if (pp->ops->link_up) + return pp->ops->link_up(pp); + +- return 0; ++ val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); ++ return val & PCIE_PHY_DEBUG_R1_LINK_UP; + } + + static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |