layerscape: add 64b/32b target for ls1043ardb device

Add support for NXP layerscape ls1043ardb 64b/32b Dev board.

LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores.
ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC,
I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc.

64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from
NXP QorIQ SDK release.

All of 4.4 kernel patches porting from SDK release or upstream.

QorIQ SDK ISOs can be downloaded from this location:
http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 71 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch b/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch
new file mode 100644
index 0000000000..299e87ebe8
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch
@@ -0,0 +1,71 @@
+From 6882f9eef932e6f5cc3c57115e3d7d4b5bc19662 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Tue, 5 Jan 2016 15:56:30 -0600
+Subject: [PATCH 53/70] PCI: designware: Make config accessor override
+ checking symmetric
+
+Drivers based on the DesignWare core can override the config read accessors
+by supplying rd_own_conf() and rd_other_conf() function pointers.
+dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root
+bus) or dw_pcie_rd_other_conf():
+
+  dw_pcie_rd_conf
+    dw_pcie_rd_own_conf                # if on root bus
+    dw_pcie_rd_other_conf              # if not on root bus
+
+Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(),
+but we checked for rd_own_conf() in dw_pcie_rd_own_conf().
+
+Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric
+with the rd_own_conf() checking, and similarly for the write path.
+
+No functional change intended.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+---
+ drivers/pci/host/pcie-designware.c |   12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/pci/host/pcie-designware.c
++++ b/drivers/pci/host/pcie-designware.c
+@@ -571,6 +571,9 @@ static int dw_pcie_rd_other_conf(struct
+ 	u64 cpu_addr;
+ 	void __iomem *va_cfg_base;
+ 
++	if (pp->ops->rd_other_conf)
++		return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
++
+ 	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
+ 		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
+ 
+@@ -605,6 +608,9 @@ static int dw_pcie_wr_other_conf(struct
+ 	u64 cpu_addr;
+ 	void __iomem *va_cfg_base;
+ 
++	if (pp->ops->wr_other_conf)
++		return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
++
+ 	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
+ 		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
+ 
+@@ -667,9 +673,6 @@ static int dw_pcie_rd_conf(struct pci_bu
+ 	if (bus->number == pp->root_bus_nr)
+ 		return dw_pcie_rd_own_conf(pp, where, size, val);
+ 
+-	if (pp->ops->rd_other_conf)
+-		return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
+-
+ 	return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
+ }
+ 
+@@ -684,9 +687,6 @@ static int dw_pcie_wr_conf(struct pci_bu
+ 	if (bus->number == pp->root_bus_nr)
+ 		return dw_pcie_wr_own_conf(pp, where, size, val);
+ 
+-	if (pp->ops->wr_other_conf)
+-		return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
+-
+ 	return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
+ }
+