diff options
| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:14:32 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (patch) | |
| tree | d92c7296f82d46d1b2da30933a97595f6cb8ad66 /target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch | |
| parent | a34f96d6cf80c7c3c425076714d9c4caa67e3670 (diff) | |
| download | upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.gz upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.bz2 upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.zip | |
layerscape: add 64b/32b target for ls1043ardb device
Add support for NXP layerscape ls1043ardb 64b/32b Dev board.
LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores.
ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC,
I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc.
64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from
NXP QorIQ SDK release.
All of 4.4 kernel patches porting from SDK release or upstream.
QorIQ SDK ISOs can be downloaded from this location:
http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch b/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch new file mode 100644 index 0000000000..c670dac4a5 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch @@ -0,0 +1,43 @@ +From 7f434723cdb6823443330cd4847d5c3b8dd30bd7 Mon Sep 17 00:00:00 2001 +From: Stanimir Varbanov <stanimir.varbanov@linaro.org> +Date: Fri, 18 Dec 2015 14:38:55 +0200 +Subject: [PATCH 51/70] PCI: designware: Ensure ATU is enabled before IO/conf + space accesses + +Read back the ATU CR2 register to ensure ATU programming is effective +before any subsequent I/O or config space accesses. + +Without this, PCI device enumeration is unreliable. + +[bhelgaas: changelog, comment] +Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +Acked-by: Pratyush Anand <pratyush.anand@gmail.com> +--- + drivers/pci/host/pcie-designware.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pc + static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, + int type, u64 cpu_addr, u64 pci_addr, u32 size) + { ++ u32 val; ++ + dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, + PCIE_ATU_VIEWPORT); + dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE); +@@ -164,6 +166,12 @@ static void dw_pcie_prog_outbound_atu(st + dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); + dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); + dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); ++ ++ /* ++ * Make sure ATU enable takes effect before any subsequent config ++ * and I/O accesses. ++ */ ++ dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val); + } + + static struct irq_chip dw_msi_irq_chip = { |