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authorKoen Vandeputte <koen.vandeputte@ncentric.com>2020-02-21 15:05:48 +0100
committerKoen Vandeputte <koen.vandeputte@ncentric.com>2020-02-24 14:20:14 +0100
commitaf79c3bccce6781c7045bd09d37585a96c0a6137 (patch)
treed6acb8d247d606dc32128438fc34ce28797b1ce6 /target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch
parentbc0ca20ca90e4d58090392c96b6d8d6405444268 (diff)
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kernel: bump 4.14 to 4.14.171
Refreshed all patches. Fixes: - CVE-2013-1798 Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch')
-rw-r--r--target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch8
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch b/target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch
index 3ecec1756e..5b50f11a8b 100644
--- a/target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch
@@ -1512,7 +1512,7 @@ Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
case SNOR_MFR_MICRON:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
-@@ -1039,7 +1040,7 @@ static const struct flash_info spi_nor_i
+@@ -1044,7 +1045,7 @@ static const struct flash_info spi_nor_i
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
@@ -1521,7 +1521,7 @@ Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
-@@ -1054,6 +1055,12 @@ static const struct flash_info spi_nor_i
+@@ -1059,6 +1060,12 @@ static const struct flash_info spi_nor_i
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
@@ -1534,7 +1534,7 @@ Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
-@@ -2431,6 +2438,7 @@ static int spi_nor_init_params(struct sp
+@@ -2436,6 +2443,7 @@ static int spi_nor_init_params(struct sp
params->quad_enable = macronix_quad_enable;
break;
@@ -1542,7 +1542,7 @@ Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
case SNOR_MFR_MICRON:
break;
-@@ -2749,7 +2757,8 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -2754,7 +2762,8 @@ int spi_nor_scan(struct spi_nor *nor, co
mtd->_read = spi_nor_read;
/* NOR protection support for STmicro/Micron chips and similar */