layerscape: upgrade kernel to 4.14

This patch is to upgrade kernel to 4.14 for layerscape.
patches-4.14 for layerscape included two categories.

- NXP Layerscape SDK kernel-4.14 patches

  All patches on tag LSDK-18.09-V4.14 were ported to OpenWrt
  kernel. Since there were hundreds patches, we had to make
  an all-in-one patch for each IP/feature.
  See below links for LSDK kernel.
  https://lsdk.github.io/components.html
  https://source.codeaurora.org/external/qoriq/qoriq-components/linux

- Non-LSDK kernel patches

  Other patches which were not in LSDK were just put in patches-4.14.
  Kept below patches from patches-4.9.
  303-dts-layerscape-add-traverse-ls1043.patch
  821-add-esdhc-vsel-to-ls1043.patch
  822-rgmii-fixed-link.patch

  Renamed and rebase them as below in patches-4.14,
  303-add-DTS-for-Traverse-LS1043-Boards.patch
  712-sdk-dpaa-rgmii-fixed-link.patch
  824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>

1 files changed, 2415 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.14/701-dpaa2-dpio-support-layerscape.patch b/target/linux/layerscape/patches-4.14/701-dpaa2-dpio-support-layerscape.patch
new file mode 100644
index 0000000000..34514caa0c
--- /dev/null
+++ b/target/linux/layerscape/patches-4.14/701-dpaa2-dpio-support-layerscape.patch
@@ -0,0 +1,2415 @@
+From ede8d823f0e1b2c5e14cbac13839b818ed1c18cf Mon Sep 17 00:00:00 2001
+From: Biwen Li <biwen.li@nxp.com>
+Date: Tue, 30 Oct 2018 18:26:10 +0800
+Subject: [PATCH 07/40] apaa2-dpio:support layerscape
+This is an integrated patch of dpaa2-dpio for layerscape
+
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
+Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
+Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
+Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
+Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
+Signed-off-by: Biwen Li <biwen.li@nxp.com>
+---
+ drivers/staging/fsl-mc/Kconfig                |   1 +
+ drivers/staging/fsl-mc/Makefile               |   1 +
+ drivers/staging/fsl-mc/bus/Kconfig            |   5 +-
+ drivers/staging/fsl-mc/bus/Makefile           |   3 +-
+ drivers/staging/fsl-mc/bus/dpbp-cmd.h         |  28 +-
+ drivers/staging/fsl-mc/bus/dpbp.c             |  28 +-
+ drivers/staging/fsl-mc/bus/dpcon-cmd.h        |  28 +-
+ drivers/staging/fsl-mc/bus/dpcon.c            |  32 +-
+ drivers/staging/fsl-mc/bus/dpio/Makefile      |   3 +-
+ drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h    |  29 +-
+ drivers/staging/fsl-mc/bus/dpio/dpio-driver.c |  53 ++--
+ .../staging/fsl-mc/bus/dpio/dpio-service.c    | 258 +++++++++++++---
+ drivers/staging/fsl-mc/bus/dpio/dpio.c        |  51 ++--
+ drivers/staging/fsl-mc/bus/dpio/dpio.h        |  32 +-
+ .../staging/fsl-mc/bus/dpio/qbman-portal.c    | 217 ++++++++++---
+ .../staging/fsl-mc/bus/dpio/qbman-portal.h    | 112 ++++---
+ drivers/staging/fsl-mc/bus/dpmcp.c            |  28 +-
+ drivers/staging/fsl-mc/bus/dprc-driver.c      |   4 +-
+ drivers/staging/fsl-mc/bus/dprc.c             |  28 +-
+ drivers/staging/fsl-mc/bus/fsl-mc-allocator.c |   4 +-
+ drivers/staging/fsl-mc/bus/fsl-mc-bus.c       |   4 +-
+ drivers/staging/fsl-mc/bus/fsl-mc-msi.c       |   4 +-
+ drivers/staging/fsl-mc/bus/fsl-mc-private.h   |   4 +-
+ .../fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c    |   4 +-
+ drivers/staging/fsl-mc/bus/mc-io.c            |  28 +-
+ drivers/staging/fsl-mc/bus/mc-sys.c           |  28 +-
+ drivers/staging/fsl-mc/include/dpaa2-fd.h     | 288 ++++++++++++++++--
+ drivers/staging/fsl-mc/include/dpaa2-global.h |  27 +-
+ drivers/staging/fsl-mc/include/dpaa2-io.h     |  97 ++++--
+ drivers/staging/fsl-mc/include/dpbp.h         |  29 +-
+ drivers/staging/fsl-mc/include/dpcon.h        |  32 +-
+ drivers/staging/fsl-mc/include/dpopr.h        | 110 +++++++
+ drivers/staging/fsl-mc/include/mc.h           |   4 +-
+ 33 files changed, 970 insertions(+), 634 deletions(-)
+ create mode 100644 drivers/staging/fsl-mc/include/dpopr.h
+
+--- a/drivers/staging/fsl-mc/Kconfig
++++ b/drivers/staging/fsl-mc/Kconfig
+@@ -1 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
+ source "drivers/staging/fsl-mc/bus/Kconfig"
+--- a/drivers/staging/fsl-mc/Makefile
++++ b/drivers/staging/fsl-mc/Makefile
+@@ -1,2 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0
+ # Freescale Management Complex (MC) bus drivers
+ obj-$(CONFIG_FSL_MC_BUS)	+= bus/
+--- a/drivers/staging/fsl-mc/bus/Kconfig
++++ b/drivers/staging/fsl-mc/bus/Kconfig
+@@ -1,10 +1,9 @@
++# SPDX-License-Identifier: GPL-2.0
+ #
+ # DPAA2 fsl-mc bus
+ #
+ # Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ #
+-# This file is released under the GPLv2
+-#
+ 
+ config FSL_MC_BUS
+ 	bool "QorIQ DPAA2 fsl-mc bus driver"
+@@ -18,7 +17,7 @@ config FSL_MC_BUS
+ 
+ config FSL_MC_DPIO
+         tristate "QorIQ DPAA2 DPIO driver"
+-        depends on FSL_MC_BUS && ARCH_LAYERSCAPE
++        depends on FSL_MC_BUS
+         help
+ 	  Driver for the DPAA2 DPIO object.  A DPIO provides queue and
+ 	  buffer management facilities for software to interact with
+--- a/drivers/staging/fsl-mc/bus/Makefile
++++ b/drivers/staging/fsl-mc/bus/Makefile
+@@ -1,10 +1,9 @@
++# SPDX-License-Identifier: GPL-2.0
+ #
+ # Freescale Management Complex (MC) bus drivers
+ #
+ # Copyright (C) 2014 Freescale Semiconductor, Inc.
+ #
+-# This file is released under the GPLv2
+-#
+ obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o
+ 
+ mc-bus-driver-objs := fsl-mc-bus.o \
+--- a/drivers/staging/fsl-mc/bus/dpbp-cmd.h
++++ b/drivers/staging/fsl-mc/bus/dpbp-cmd.h
+@@ -1,33 +1,7 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef _FSL_DPBP_CMD_H
+ #define _FSL_DPBP_CMD_H
+--- a/drivers/staging/fsl-mc/bus/dpbp.c
++++ b/drivers/staging/fsl-mc/bus/dpbp.c
+@@ -1,33 +1,7 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #include <linux/kernel.h>
+ #include "../include/mc.h"
+--- a/drivers/staging/fsl-mc/bus/dpcon-cmd.h
++++ b/drivers/staging/fsl-mc/bus/dpcon-cmd.h
+@@ -1,33 +1,7 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef _FSL_DPCON_CMD_H
+ #define _FSL_DPCON_CMD_H
+--- a/drivers/staging/fsl-mc/bus/dpcon.c
++++ b/drivers/staging/fsl-mc/bus/dpcon.c
+@@ -1,33 +1,7 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #include <linux/kernel.h>
+ #include "../include/mc.h"
+--- a/drivers/staging/fsl-mc/bus/dpio/Makefile
++++ b/drivers/staging/fsl-mc/bus/dpio/Makefile
+@@ -1,9 +1,8 @@
++# SPDX-License-Identifier: GPL-2.0
+ #
+ # QorIQ DPAA2 DPIO driver
+ #
+ 
+-subdir-ccflags-y := -Werror
+-
+ obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
+ 
+ fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o
+--- a/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
+@@ -1,34 +1,8 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef _FSL_DPIO_CMD_H
+ #define _FSL_DPIO_CMD_H
+@@ -51,6 +25,7 @@
+ #define DPIO_CMDID_ENABLE				DPIO_CMD(0x002)
+ #define DPIO_CMDID_DISABLE				DPIO_CMD(0x003)
+ #define DPIO_CMDID_GET_ATTR				DPIO_CMD(0x004)
++#define DPIO_CMDID_RESET				DPIO_CMD(0x005)
+ 
+ struct dpio_cmd_open {
+ 	__le32 dpio_id;
+--- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
+@@ -1,33 +1,8 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2014-2016 Freescale Semiconductor Inc.
+- * Copyright NXP 2016
++ * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *	 notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *	 notice, this list of conditions and the following disclaimer in the
+- *	 documentation and/or other materials provided with the distribution.
+- *     * Neither the name of Freescale Semiconductor nor the
+- *	 names of its contributors may be used to endorse or promote products
+- *	 derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ 
+ #include <linux/types.h>
+@@ -114,6 +89,7 @@ static int dpaa2_dpio_probe(struct fsl_m
+ 	int err = -ENOMEM;
+ 	struct device *dev = &dpio_dev->dev;
+ 	static int next_cpu = -1;
++	int possible_next_cpu;
+ 
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+@@ -135,6 +111,12 @@ static int dpaa2_dpio_probe(struct fsl_m
+ 		goto err_open;
+ 	}
+ 
++	err = dpio_reset(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpio_reset() failed\n");
++		goto err_reset;
++	}
++
+ 	err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
+ 				  &dpio_attrs);
+ 	if (err) {
+@@ -156,23 +138,23 @@ static int dpaa2_dpio_probe(struct fsl_m
+ 
+ 	/* get the cpu to use for the affinity hint */
+ 	if (next_cpu == -1)
+-		next_cpu = cpumask_first(cpu_online_mask);
++		possible_next_cpu = cpumask_first(cpu_online_mask);
+ 	else
+-		next_cpu = cpumask_next(next_cpu, cpu_online_mask);
++		possible_next_cpu = cpumask_next(next_cpu, cpu_online_mask);
+ 
+-	if (!cpu_possible(next_cpu)) {
++	if (possible_next_cpu >= nr_cpu_ids) {
+ 		dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
+ 		err = -ERANGE;
+ 		goto err_allocate_irqs;
+ 	}
+-	desc.cpu = next_cpu;
++	desc.cpu = next_cpu = possible_next_cpu;
+ 
+ 	/*
+-	 * Set the CENA regs to be the cache inhibited area of the portal to
+-	 * avoid coherency issues if a user migrates to another core.
++	 * Set the CENA regs to be the cache enabled area of the portal to
++	 * achieve the best performance.
+ 	 */
+-	desc.regs_cena = ioremap_wc(dpio_dev->regions[1].start,
+-		resource_size(&dpio_dev->regions[1]));
++	desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
++		resource_size(&dpio_dev->regions[0]));
+ 	desc.regs_cinh = ioremap(dpio_dev->regions[1].start,
+ 		resource_size(&dpio_dev->regions[1]));
+ 
+@@ -207,6 +189,7 @@ err_register_dpio_irq:
+ err_allocate_irqs:
+ 	dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
+ err_get_attr:
++err_reset:
+ 	dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
+ err_open:
+ 	fsl_mc_portal_free(dpio_dev->mc_io);
+--- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
+@@ -1,33 +1,8 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2014-2016 Freescale Semiconductor Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *	 notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *	 notice, this list of conditions and the following disclaimer in the
+- *	 documentation and/or other materials provided with the distribution.
+- *     * Neither the name of Freescale Semiconductor nor the
+- *	 names of its contributors may be used to endorse or promote products
+- *	 derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ #include <linux/types.h>
+ #include "../../include/mc.h"
+@@ -43,7 +18,6 @@
+ #include "qbman-portal.h"
+ 
+ struct dpaa2_io {
+-	atomic_t refs;
+ 	struct dpaa2_io_desc dpio_desc;
+ 	struct qbman_swp_desc swp_desc;
+ 	struct qbman_swp *swp;
+@@ -83,7 +57,7 @@ static inline struct dpaa2_io *service_s
+ 	 * If cpu == -1, choose the current cpu, with no guarantees about
+ 	 * potentially being migrated away.
+ 	 */
+-	if (unlikely(cpu < 0))
++	if (cpu < 0)
+ 		cpu = smp_processor_id();
+ 
+ 	/* If a specific cpu was requested, pick it up immediately */
+@@ -95,6 +69,10 @@ static inline struct dpaa2_io *service_s
+ 	if (d)
+ 		return d;
+ 
++	d = service_select_by_cpu(d, -1);
++	if (d)
++		return d;
++
+ 	spin_lock(&dpio_list_lock);
+ 	d = list_entry(dpio_list.next, struct dpaa2_io, node);
+ 	list_del(&d->node);
+@@ -105,6 +83,23 @@ static inline struct dpaa2_io *service_s
+ }
+ 
+ /**
++ * dpaa2_io_service_select() - return a dpaa2_io service affined to this cpu
++ * @cpu: the cpu id
++ *
++ * Return the affine dpaa2_io service, or NULL if there is no service affined
++ * to the specified cpu. If DPAA2_IO_ANY_CPU is used, return the next available
++ * service.
++ */
++struct dpaa2_io *dpaa2_io_service_select(int cpu)
++{
++	if (cpu == DPAA2_IO_ANY_CPU)
++		return service_select(NULL);
++
++	return service_select_by_cpu(NULL, cpu);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_select);
++
++/**
+  * dpaa2_io_create() - create a dpaa2_io object.
+  * @desc: the dpaa2_io descriptor
+  *
+@@ -126,7 +121,6 @@ struct dpaa2_io *dpaa2_io_create(const s
+ 		return NULL;
+ 	}
+ 
+-	atomic_set(&obj->refs, 1);
+ 	obj->dpio_desc = *desc;
+ 	obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
+ 	obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
+@@ -158,7 +152,6 @@ struct dpaa2_io *dpaa2_io_create(const s
+ 
+ 	return obj;
+ }
+-EXPORT_SYMBOL(dpaa2_io_create);
+ 
+ /**
+  * dpaa2_io_down() - release the dpaa2_io object.
+@@ -171,11 +164,8 @@ EXPORT_SYMBOL(dpaa2_io_create);
+  */
+ void dpaa2_io_down(struct dpaa2_io *d)
+ {
+-	if (!atomic_dec_and_test(&d->refs))
+-		return;
+ 	kfree(d);
+ }
+-EXPORT_SYMBOL(dpaa2_io_down);
+ 
+ #define DPAA_POLL_MAX 32
+ 
+@@ -206,7 +196,7 @@ irqreturn_t dpaa2_io_irq(struct dpaa2_io
+ 			u64 q64;
+ 
+ 			q64 = qbman_result_SCN_ctx(dq);
+-			ctx = (void *)q64;
++			ctx = (void *)(uintptr_t)q64;
+ 			ctx->cb(ctx);
+ 		} else {
+ 			pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
+@@ -222,7 +212,6 @@ done:
+ 	qbman_swp_interrupt_set_inhibit(swp, 0);
+ 	return IRQ_HANDLED;
+ }
+-EXPORT_SYMBOL(dpaa2_io_irq);
+ 
+ /**
+  * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
+@@ -252,7 +241,7 @@ int dpaa2_io_service_register(struct dpa
+ 		return -ENODEV;
+ 
+ 	ctx->dpio_id = d->dpio_desc.dpio_id;
+-	ctx->qman64 = (u64)ctx;
++	ctx->qman64 = (u64)(uintptr_t)ctx;
+ 	ctx->dpio_private = d;
+ 	spin_lock_irqsave(&d->lock_notifications, irqflags);
+ 	list_add(&ctx->node, &d->notifications);
+@@ -265,7 +254,7 @@ int dpaa2_io_service_register(struct dpa
+ 							 ctx->qman64);
+ 	return 0;
+ }
+-EXPORT_SYMBOL(dpaa2_io_service_register);
++EXPORT_SYMBOL_GPL(dpaa2_io_service_register);
+ 
+ /**
+  * dpaa2_io_service_deregister - The opposite of 'register'.
+@@ -288,7 +277,7 @@ void dpaa2_io_service_deregister(struct
+ 	list_del(&ctx->node);
+ 	spin_unlock_irqrestore(&d->lock_notifications, irqflags);
+ }
+-EXPORT_SYMBOL(dpaa2_io_service_deregister);
++EXPORT_SYMBOL_GPL(dpaa2_io_service_deregister);
+ 
+ /**
+  * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
+@@ -322,7 +311,7 @@ int dpaa2_io_service_rearm(struct dpaa2_
+ 
+ 	return err;
+ }
+-EXPORT_SYMBOL(dpaa2_io_service_rearm);
++EXPORT_SYMBOL_GPL(dpaa2_io_service_rearm);
+ 
+ /**
+  * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq.
+@@ -385,7 +374,7 @@ int dpaa2_io_service_pull_channel(struct
+ 
+ 	return err;
+ }
+-EXPORT_SYMBOL(dpaa2_io_service_pull_channel);
++EXPORT_SYMBOL_GPL(dpaa2_io_service_pull_channel);
+ 
+ /**
+  * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue.
+@@ -441,7 +430,7 @@ int dpaa2_io_service_enqueue_qd(struct d
+ 
+ 	return qbman_swp_enqueue(d->swp, &ed, fd);
+ }
+-EXPORT_SYMBOL(dpaa2_io_service_enqueue_qd);
++EXPORT_SYMBOL_GPL(dpaa2_io_service_enqueue_qd);
+ 
+ /**
+  * dpaa2_io_service_release() - Release buffers to a buffer pool.
+@@ -453,7 +442,7 @@ EXPORT_SYMBOL(dpaa2_io_service_enqueue_q
+  * Return 0 for success, and negative error code for failure.
+  */
+ int dpaa2_io_service_release(struct dpaa2_io *d,
+-			     u32 bpid,
++			     u16 bpid,
+ 			     const u64 *buffers,
+ 			     unsigned int num_buffers)
+ {
+@@ -468,7 +457,7 @@ int dpaa2_io_service_release(struct dpaa
+ 
+ 	return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
+ }
+-EXPORT_SYMBOL(dpaa2_io_service_release);
++EXPORT_SYMBOL_GPL(dpaa2_io_service_release);
+ 
+ /**
+  * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
+@@ -482,7 +471,7 @@ EXPORT_SYMBOL(dpaa2_io_service_release);
+  * Eg. if the buffer pool is empty, this will return zero.
+  */
+ int dpaa2_io_service_acquire(struct dpaa2_io *d,
+-			     u32 bpid,
++			     u16 bpid,
+ 			     u64 *buffers,
+ 			     unsigned int num_buffers)
+ {
+@@ -499,7 +488,7 @@ int dpaa2_io_service_acquire(struct dpaa
+ 
+ 	return err;
+ }
+-EXPORT_SYMBOL(dpaa2_io_service_acquire);
++EXPORT_SYMBOL_GPL(dpaa2_io_service_acquire);
+ 
+ /*
+  * 'Stores' are reusable memory blocks for holding dequeue results, and to
+@@ -553,7 +542,7 @@ struct dpaa2_io_store *dpaa2_io_store_cr
+ 
+ 	return ret;
+ }
+-EXPORT_SYMBOL(dpaa2_io_store_create);
++EXPORT_SYMBOL_GPL(dpaa2_io_store_create);
+ 
+ /**
+  * dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
+@@ -567,7 +556,7 @@ void dpaa2_io_store_destroy(struct dpaa2
+ 	kfree(s->alloced_addr);
+ 	kfree(s);
+ }
+-EXPORT_SYMBOL(dpaa2_io_store_destroy);
++EXPORT_SYMBOL_GPL(dpaa2_io_store_destroy);
+ 
+ /**
+  * dpaa2_io_store_next() - Determine when the next dequeue result is available.
+@@ -615,4 +604,177 @@ struct dpaa2_dq *dpaa2_io_store_next(str
+ 
+ 	return ret;
+ }
+-EXPORT_SYMBOL(dpaa2_io_store_next);
++EXPORT_SYMBOL_GPL(dpaa2_io_store_next);
++
++/**
++ * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq.
++ * @d: the given DPIO object.
++ * @fqid: the id of frame queue to be queried.
++ * @fcnt: the queried frame count.
++ * @bcnt: the queried byte count.
++ *
++ * Knowing the FQ count at run-time can be useful in debugging situations.
++ * The instantaneous frame- and byte-count are hereby returned.
++ *
++ * Return 0 for a successful query, and negative error code if query fails.
++ */
++int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid,
++			    u32 *fcnt, u32 *bcnt)
++{
++	struct qbman_fq_query_np_rslt state;
++	struct qbman_swp *swp;
++	unsigned long irqflags;
++	int ret;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	swp = d->swp;
++	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
++	ret = qbman_fq_query_state(swp, fqid, &state);
++	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
++	if (ret)
++		return ret;
++	*fcnt = qbman_fq_state_frame_count(&state);
++	*bcnt = qbman_fq_state_byte_count(&state);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_query_fq_count);
++
++/**
++ * dpaa2_io_query_bp_count() - Query the number of buffers currently in a
++ * buffer pool.
++ * @d: the given DPIO object.
++ * @bpid: the index of buffer pool to be queried.
++ * @num: the queried number of buffers in the buffer pool.
++ *
++ * Return 0 for a successful query, and negative error code if query fails.
++ */
++int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, u32 *num)
++{
++	struct qbman_bp_query_rslt state;
++	struct qbman_swp *swp;
++	unsigned long irqflags;
++	int ret;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	swp = d->swp;
++	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
++	ret = qbman_bp_query(swp, bpid, &state);
++	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
++	if (ret)
++		return ret;
++	*num = qbman_bp_info_num_free_bufs(&state);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_query_bp_count);
++
++/**
++ * dpaa2_io_service_enqueue_orp_fq() - Enqueue a frame to a frame queue with
++ * order restoration
++ * @d: the given DPIO service.
++ * @fqid: the given frame queue id.
++ * @fd: the frame descriptor which is enqueued.
++ * @orpid: the order restoration point ID
++ * @seqnum: the order sequence number
++ * @last: must be set for the final frame if seqnum is shared (spilt frame)
++ *
++ * Performs an enqueue to a frame queue using the specified order restoration
++ * point. The QMan device will ensure the order of frames placed on the
++ * queue will be ordered as per the sequence number.
++ *
++ * In the case a frame is split it is possible to enqueue using the same
++ * sequence number more than once. The final frame in a shared sequence number
++ * most be indicated by setting last = 1. For non shared sequence numbers
++ * last = 1 must always be set.
++ *
++ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_enqueue_orp_fq(struct dpaa2_io *d, u32 fqid,
++				    const struct dpaa2_fd *fd, u16 orpid,
++				    u16 seqnum, int last)
++{
++	struct qbman_eq_desc ed;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_orp(&ed, 0, orpid, seqnum, !last);
++	qbman_eq_desc_set_fq(&ed, fqid);
++	return qbman_swp_enqueue(d->swp, &ed, fd);
++}
++EXPORT_SYMBOL(dpaa2_io_service_enqueue_orp_fq);
++
++/**
++ * dpaa2_io_service_enqueue_orp_qd() - Enqueue a frame to a queueing destination
++ * with order restoration
++ * @d: the given DPIO service.
++ * @qdid: the given queuing destination id.
++ * @fd: the frame descriptor which is enqueued.
++ * @orpid: the order restoration point ID
++ * @seqnum: the order sequence number
++ * @last: must be set for the final frame if seqnum is shared (spilt frame)
++ *
++ * Performs an enqueue to a frame queue using the specified order restoration
++ * point. The QMan device will ensure the order of frames placed on the
++ * queue will be ordered as per the sequence number.
++ *
++ * In the case a frame is split it is possible to enqueue using the same
++ * sequence number more than once. The final frame in a shared sequence number
++ * most be indicated by setting last = 1. For non shared sequence numbers
++ * last = 1 must always be set.
++ *
++ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_enqueue_orp_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
++				    u16 qdbin, const struct dpaa2_fd *fd,
++				    u16 orpid, u16 seqnum, int last)
++{
++	struct qbman_eq_desc ed;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_orp(&ed, 0, orpid, seqnum, !last);
++	qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
++	return qbman_swp_enqueue(d->swp, &ed, fd);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_enqueue_orp_qd);
++
++/**
++ * dpaa2_io_service_orp_seqnum_drop() - Remove a sequence number from
++ * an order restoration list
++ * @d: the given DPIO service.
++ * @orpid: Order restoration point to remove a sequence number from
++ * @seqnum: Sequence number to remove
++ *
++ * Removes a frames sequence number from an order restoration point without
++ * enqueing the frame. Used to indicate that the order restoration hardware
++ * should not expect to see this sequence number. Typically used to indicate
++ * a frame was terminated or dropped from a flow.
++ *
++ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_orp_seqnum_drop(struct dpaa2_io *d, u16 orpid, u16 seqnum)
++{
++	struct qbman_eq_desc ed;
++	struct dpaa2_fd fd;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_orp_hole(&ed, orpid, seqnum);
++	return qbman_swp_enqueue(d->swp, &ed, &fd);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_orp_seqnum_drop);
+--- a/drivers/staging/fsl-mc/bus/dpio/dpio.c
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
+@@ -1,34 +1,8 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #include <linux/kernel.h>
+ #include "../../include/mc.h"
+@@ -222,3 +196,26 @@ int dpio_get_api_version(struct fsl_mc_i
+ 
+ 	return 0;
+ }
++
++/**
++ * dpio_reset() - Reset the DPIO, returns the object to initial state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPIO object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpio_reset(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
+--- a/drivers/staging/fsl-mc/bus/dpio/dpio.h
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio.h
+@@ -1,34 +1,8 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef __FSL_DPIO_H
+ #define __FSL_DPIO_H
+@@ -106,4 +80,8 @@ int dpio_get_api_version(struct fsl_mc_i
+ 			 u16 *major_ver,
+ 			 u16 *minor_ver);
+ 
++int dpio_reset(struct fsl_mc_io	*mc_io,
++	       u32 cmd_flags,
++	       u16 token);
++
+ #endif /* __FSL_DPIO_H */
+--- a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
++++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
+@@ -1,33 +1,8 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of Freescale Semiconductor nor the
+- *       names of its contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ 
+ #include <asm/cacheflush.h>
+@@ -99,6 +74,14 @@ enum qbman_sdqcr_fc {
+ 	qbman_sdqcr_fc_up_to_3 = 1
+ };
+ 
++#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
++#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
++static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
++{
++	dcivac(p->addr_cena + offset);
++	prefetch(p->addr_cena + offset);
++}
++
+ /* Portal Access */
+ 
+ static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
+@@ -189,7 +172,7 @@ struct qbman_swp *qbman_swp_init(const s
+ 	p->addr_cinh = d->cinh_bar;
+ 
+ 	reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
+-				1, /* Writes Non-cacheable */
++				0, /* Writes cacheable */
+ 				0, /* EQCR_CI stashing threshold */
+ 				3, /* RPM: Valid bit mode, RCR in array mode */
+ 				2, /* DCM: Discrete consumption ack mode */
+@@ -315,6 +298,7 @@ void qbman_swp_mc_submit(struct qbman_sw
+ 
+ 	dma_wmb();
+ 	*v = cmd_verb | p->mc.valid_bit;
++	dccvac(cmd);
+ }
+ 
+ /*
+@@ -325,6 +309,7 @@ void *qbman_swp_mc_result(struct qbman_s
+ {
+ 	u32 *ret, verb;
+ 
++	qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
+ 	ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
+ 
+ 	/* Remove the valid-bit - command completed if the rest is non-zero */
+@@ -370,6 +355,43 @@ void qbman_eq_desc_set_no_orp(struct qbm
+ 		d->verb |= enqueue_rejects_to_fq;
+ }
+ 
++/**
++ * qbman_eq_desc_set_orp() - Set order-restoration in the enqueue descriptor
++ * @d: the enqueue descriptor.
++ * @response_success: 1 = enqueue with response always; 0 = enqueue with
++ * rejections returned on a FQ.
++ * @oprid: the order point record id.
++ * @seqnum: the order restoration sequence number.
++ * @incomplete: indicates whether this is the last fragments using the same
++ * sequence number.
++ */
++void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
++			   u16 oprid, u16 seqnum, int incomplete)
++{
++	d->verb |= (1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
++	if (respond_success)
++		d->verb |= enqueue_response_always;
++	else
++		d->verb |= enqueue_rejects_to_fq;
++	d->orpid = cpu_to_le16(oprid);
++	d->seqnum = cpu_to_le16((!!incomplete << 14) | seqnum);
++}
++
++/**
++ * qbman_eq_desc_set_orp_hole() - fill a hole in the order-restoration sequence
++ * without any enqueue
++ * @d: the enqueue descriptor.
++ * @oprid: the order point record id.
++ * @seqnum: the order restoration sequence number.
++ */
++void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, u16 oprid,
++				u16 seqnum)
++{
++	d->verb |= (1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT) | enqueue_empty;
++	d->orpid = cpu_to_le16(oprid);
++	d->seqnum = cpu_to_le16(seqnum);
++}
++
+ /*
+  * Exactly one of the following descriptor "targets" should be set. (Calling any
+  * one of these will replace the effect of any prior call to one of these.)
+@@ -429,12 +451,23 @@ int qbman_swp_enqueue(struct qbman_swp *
+ 		return -EBUSY;
+ 
+ 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
+-	memcpy(&p->dca, &d->dca, 31);
++	/* This is mapped as DEVICE type memory, writes are
++	 * with address alignment:
++	 * desc.dca address alignment = 1
++	 * desc.seqnum address alignment = 2
++	 * desc.orpid address alignment = 4
++	 * desc.tgtid address alignment = 8
++	 */
++	p->dca = d->dca;
++	p->seqnum = d->seqnum;
++	p->orpid = d->orpid;
++	memcpy(&p->tgtid, &d->tgtid, 24);
+ 	memcpy(&p->fd, fd, sizeof(*fd));
+ 
+ 	/* Set the verb byte, have to substitute in the valid-bit */
+ 	dma_wmb();
+ 	p->verb = d->verb | EQAR_VB(eqar);
++	dccvac(p);
+ 
+ 	return 0;
+ }
+@@ -522,7 +555,7 @@ void qbman_pull_desc_set_storage(struct
+ 				 int stash)
+ {
+ 	/* save the virtual address */
+-	d->rsp_addr_virt = (u64)storage;
++	d->rsp_addr_virt = (u64)(uintptr_t)storage;
+ 
+ 	if (!storage) {
+ 		d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
+@@ -615,7 +648,7 @@ int qbman_swp_pull(struct qbman_swp *s,
+ 		atomic_inc(&s->vdq.available);
+ 		return -EBUSY;
+ 	}
+-	s->vdq.storage = (void *)d->rsp_addr_virt;
++	s->vdq.storage = (void *)(uintptr_t)d->rsp_addr_virt;
+ 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
+ 	p->numf = d->numf;
+ 	p->tok = QMAN_DQ_TOKEN_VALID;
+@@ -627,6 +660,7 @@ int qbman_swp_pull(struct qbman_swp *s,
+ 	/* Set the verb byte, have to substitute in the valid-bit */
+ 	p->verb = d->verb | s->vdq.valid_bit;
+ 	s->vdq.valid_bit ^= QB_VALID_BIT;
++	dccvac(p);
+ 
+ 	return 0;
+ }
+@@ -680,8 +714,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
+ 				 s->dqrr.next_idx, pi);
+ 			s->dqrr.reset_bug = 0;
+ 		}
+-		prefetch(qbman_get_cmd(s,
+-				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
++		qbman_inval_prefetch(s,	QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
+ 	}
+ 
+ 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
+@@ -696,8 +729,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
+ 	 * knew from reading PI.
+ 	 */
+ 	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
+-		prefetch(qbman_get_cmd(s,
+-				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
++		qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
+ 		return NULL;
+ 	}
+ 	/*
+@@ -720,7 +752,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
+ 	    (flags & DPAA2_DQ_STAT_EXPIRED))
+ 		atomic_inc(&s->vdq.available);
+ 
+-	prefetch(qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
++	qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
+ 
+ 	return p;
+ }
+@@ -848,6 +880,7 @@ int qbman_swp_release(struct qbman_swp *
+ 	 */
+ 	dma_wmb();
+ 	p->verb = d->verb | RAR_VB(rar) | num_buffers;
++	dccvac(p);
+ 
+ 	return 0;
+ }
+@@ -855,7 +888,7 @@ int qbman_swp_release(struct qbman_swp *
+ struct qbman_acquire_desc {
+ 	u8 verb;
+ 	u8 reserved;
+-	u16 bpid;
++	__le16 bpid;
+ 	u8 num;
+ 	u8 reserved2[59];
+ };
+@@ -863,10 +896,10 @@ struct qbman_acquire_desc {
+ struct qbman_acquire_rslt {
+ 	u8 verb;
+ 	u8 rslt;
+-	u16 reserved;
++	__le16 reserved;
+ 	u8 num;
+ 	u8 reserved2[3];
+-	u64 buf[7];
++	__le64 buf[7];
+ };
+ 
+ /**
+@@ -929,7 +962,7 @@ int qbman_swp_acquire(struct qbman_swp *
+ struct qbman_alt_fq_state_desc {
+ 	u8 verb;
+ 	u8 reserved[3];
+-	u32 fqid;
++	__le32 fqid;
+ 	u8 reserved2[56];
+ };
+ 
+@@ -952,7 +985,7 @@ int qbman_swp_alt_fq_state(struct qbman_
+ 	if (!p)
+ 		return -EBUSY;
+ 
+-	p->fqid = cpu_to_le32(fqid) & ALT_FQ_FQID_MASK;
++	p->fqid = cpu_to_le32(fqid & ALT_FQ_FQID_MASK);
+ 
+ 	/* Complete the management command */
+ 	r = qbman_swp_mc_complete(s, p, alt_fq_verb);
+@@ -978,11 +1011,11 @@ int qbman_swp_alt_fq_state(struct qbman_
+ struct qbman_cdan_ctrl_desc {
+ 	u8 verb;
+ 	u8 reserved;
+-	u16 ch;
++	__le16 ch;
+ 	u8 we;
+ 	u8 ctrl;
+-	u16 reserved2;
+-	u64 cdan_ctx;
++	__le16 reserved2;
++	__le64 cdan_ctx;
+ 	u8 reserved3[48];
+ 
+ };
+@@ -990,7 +1023,7 @@ struct qbman_cdan_ctrl_desc {
+ struct qbman_cdan_ctrl_rslt {
+ 	u8 verb;
+ 	u8 rslt;
+-	u16 ch;
++	__le16 ch;
+ 	u8 reserved[60];
+ };
+ 
+@@ -1033,3 +1066,99 @@ int qbman_swp_CDAN_set(struct qbman_swp
+ 
+ 	return 0;
+ }
++
++#define QBMAN_RESPONSE_VERB_MASK	0x7f
++#define QBMAN_FQ_QUERY_NP		0x45
++#define QBMAN_BP_QUERY			0x32
++
++struct qbman_fq_query_desc {
++	u8 verb;
++	u8 reserved[3];
++	__le32 fqid;
++	u8 reserved2[56];
++};
++
++int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
++			 struct qbman_fq_query_np_rslt *r)
++{
++	struct qbman_fq_query_desc *p;
++	void *resp;
++
++	p = (struct qbman_fq_query_desc *)qbman_swp_mc_start(s);
++	if (!p)
++		return -EBUSY;
++
++	/* FQID is a 24 bit value */
++	p->fqid = cpu_to_le32(fqid & 0x00FFFFFF);
++	resp = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
++	if (!resp) {
++		pr_err("qbman: Query FQID %d NP fields failed, no response\n",
++		       fqid);
++		return -EIO;
++	}
++	*r = *(struct qbman_fq_query_np_rslt *)resp;
++	/* Decode the outcome */
++	WARN_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_FQ_QUERY_NP);
++
++	/* Determine success or failure */
++	if (r->rslt != QBMAN_MC_RSLT_OK) {
++		pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
++		       p->fqid, r->rslt);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++u32 qbman_fq_state_frame_count(const struct qbman_fq_query_np_rslt *r)
++{
++	return (le32_to_cpu(r->frm_cnt) & 0x00FFFFFF);
++}
++
++u32 qbman_fq_state_byte_count(const struct qbman_fq_query_np_rslt *r)
++{
++	return le32_to_cpu(r->byte_cnt);
++}
++
++struct qbman_bp_query_desc {
++	u8 verb;
++	u8 reserved;
++	__le16 bpid;
++	u8 reserved2[60];
++};
++
++int qbman_bp_query(struct qbman_swp *s, u16 bpid,
++		   struct qbman_bp_query_rslt *r)
++{
++	struct qbman_bp_query_desc *p;
++	void *resp;
++
++	p = (struct qbman_bp_query_desc *)qbman_swp_mc_start(s);
++	if (!p)
++		return -EBUSY;
++
++	p->bpid = cpu_to_le16(bpid);
++	resp = qbman_swp_mc_complete(s, p, QBMAN_BP_QUERY);
++	if (!resp) {
++		pr_err("qbman: Query BPID %d fields failed, no response\n",
++		       bpid);
++		return -EIO;
++	}
++	*r = *(struct qbman_bp_query_rslt *)resp;
++	/* Decode the outcome */
++	WARN_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_BP_QUERY);
++
++	/* Determine success or failure */
++	if (r->rslt != QBMAN_MC_RSLT_OK) {
++		pr_err("Query fields of BPID 0x%x failed, code=0x%02x\n",
++		       bpid, r->rslt);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a)
++{
++	return le32_to_cpu(a->fill);
++}
+--- a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
++++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
+@@ -1,33 +1,8 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of Freescale Semiconductor nor the
+- *       names of its contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef __FSL_QBMAN_PORTAL_H
+ #define __FSL_QBMAN_PORTAL_H
+@@ -57,8 +32,8 @@ struct qbman_pull_desc {
+ 	u8 numf;
+ 	u8 tok;
+ 	u8 reserved;
+-	u32 dq_src;
+-	u64 rsp_addr;
++	__le32 dq_src;
++	__le64 rsp_addr;
+ 	u64 rsp_addr_virt;
+ 	u8 padding[40];
+ };
+@@ -95,17 +70,17 @@ enum qbman_pull_type_e {
+ struct qbman_eq_desc {
+ 	u8 verb;
+ 	u8 dca;
+-	u16 seqnum;
+-	u16 orpid;
+-	u16 reserved1;
+-	u32 tgtid;
+-	u32 tag;
+-	u16 qdbin;
++	__le16 seqnum;
++	__le16 orpid;
++	__le16 reserved1;
++	__le32 tgtid;
++	__le32 tag;
++	__le16 qdbin;
+ 	u8 qpri;
+ 	u8 reserved[3];
+ 	u8 wae;
+ 	u8 rspid;
+-	u64 rsp_addr;
++	__le64 rsp_addr;
+ 	u8 fd[32];
+ };
+ 
+@@ -113,9 +88,9 @@ struct qbman_eq_desc {
+ struct qbman_release_desc {
+ 	u8 verb;
+ 	u8 reserved;
+-	u16 bpid;
+-	u32 reserved2;
+-	u64 buf[7];
++	__le16 bpid;
++	__le32 reserved2;
++	__le64 buf[7];
+ };
+ 
+ /* Management command result codes */
+@@ -187,6 +162,9 @@ int qbman_result_has_new_result(struct q
+ 
+ void qbman_eq_desc_clear(struct qbman_eq_desc *d);
+ void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
++void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
++			   u16 oprid, u16 seqnum, int incomplete);
++void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, u16 oprid, u16 seqnum);
+ void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
+ void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
+ void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
+@@ -466,4 +444,62 @@ static inline void *qbman_swp_mc_complet
+ 	return cmd;
+ }
+ 
++/* Query APIs */
++struct qbman_fq_query_np_rslt {
++	u8 verb;
++	u8 rslt;
++	u8 st1;
++	u8 st2;
++	u8 reserved[2];
++	__le16 od1_sfdr;
++	__le16 od2_sfdr;
++	__le16 od3_sfdr;
++	__le16 ra1_sfdr;
++	__le16 ra2_sfdr;
++	__le32 pfdr_hptr;
++	__le32 pfdr_tptr;
++	__le32 frm_cnt;
++	__le32 byte_cnt;
++	__le16 ics_surp;
++	u8 is;
++	u8 reserved2[29];
++};
++
++int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
++			 struct qbman_fq_query_np_rslt *r);
++u32 qbman_fq_state_frame_count(const struct qbman_fq_query_np_rslt *r);
++u32 qbman_fq_state_byte_count(const struct qbman_fq_query_np_rslt *r);
++
++struct qbman_bp_query_rslt {
++	u8 verb;
++	u8 rslt;
++	u8 reserved[4];
++	u8 bdi;
++	u8 state;
++	__le32 fill;
++	__le32 hdotr;
++	__le16 swdet;
++	__le16 swdxt;
++	__le16 hwdet;
++	__le16 hwdxt;
++	__le16 swset;
++	__le16 swsxt;
++	__le16 vbpid;
++	__le16 icid;
++	__le64 bpscn_addr;
++	__le64 bpscn_ctx;
++	__le16 hw_targ;
++	u8 dbe;
++	u8 reserved2;
++	u8 sdcnt;
++	u8 hdcnt;
++	u8 sscnt;
++	u8 reserved3[9];
++};
++
++int qbman_bp_query(struct qbman_swp *s, u16 bpid,
++		   struct qbman_bp_query_rslt *r);
++
++u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a);
++
+ #endif /* __FSL_QBMAN_PORTAL_H */
+--- a/drivers/staging/fsl-mc/bus/dpmcp.c
++++ b/drivers/staging/fsl-mc/bus/dpmcp.c
+@@ -1,33 +1,7 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #include <linux/kernel.h>
+ #include "../include/mc.h"
+--- a/drivers/staging/fsl-mc/bus/dprc-driver.c
++++ b/drivers/staging/fsl-mc/bus/dprc-driver.c
+@@ -1,12 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Freescale data path resource container (DPRC) driver
+  *
+  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+  * Author: German Rivera <German.Rivera@freescale.com>
+  *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ #include <linux/module.h>
+--- a/drivers/staging/fsl-mc/bus/dprc.c
++++ b/drivers/staging/fsl-mc/bus/dprc.c
+@@ -1,33 +1,7 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #include <linux/kernel.h>
+ #include "../include/mc.h"
+--- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
++++ b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
+@@ -1,11 +1,9 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * fsl-mc object allocator driver
+  *
+  * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+  *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ #include <linux/module.h>
+--- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
++++ b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
+@@ -1,12 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Freescale Management Complex (MC) bus driver
+  *
+  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+  * Author: German Rivera <German.Rivera@freescale.com>
+  *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ #define pr_fmt(fmt) "fsl-mc: " fmt
+--- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
++++ b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
+@@ -1,12 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Freescale Management Complex (MC) bus driver MSI support
+  *
+  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+  * Author: German Rivera <German.Rivera@freescale.com>
+  *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ #include <linux/of_device.h>
+--- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h
++++ b/drivers/staging/fsl-mc/bus/fsl-mc-private.h
+@@ -1,11 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0 */
+ /*
+  * Freescale Management Complex (MC) bus private declarations
+  *
+  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+  *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ #ifndef _FSL_MC_PRIVATE_H_
+ #define _FSL_MC_PRIVATE_H_
+--- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
++++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
+@@ -1,12 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0
+ /*
+  * Freescale Management Complex (MC) bus driver MSI support
+  *
+  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+  * Author: German Rivera <German.Rivera@freescale.com>
+  *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ 
+ #include <linux/of_device.h>
+--- a/drivers/staging/fsl-mc/bus/mc-io.c
++++ b/drivers/staging/fsl-mc/bus/mc-io.c
+@@ -1,33 +1,7 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of the above-listed copyright holders nor the
+- *       names of any contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ 
+ #include <linux/io.h>
+--- a/drivers/staging/fsl-mc/bus/mc-sys.c
++++ b/drivers/staging/fsl-mc/bus/mc-sys.c
+@@ -1,35 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+  * I/O services to send MC commands to the MC hardware
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of the above-listed copyright holders nor the
+- *       names of any contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ 
+ #include <linux/delay.h>
+--- a/drivers/staging/fsl-mc/include/dpaa2-fd.h
++++ b/drivers/staging/fsl-mc/include/dpaa2-fd.h
+@@ -1,33 +1,8 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2014-2016 Freescale Semiconductor Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of Freescale Semiconductor nor the
+- *       names of its contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef __FSL_DPAA2_FD_H
+ #define __FSL_DPAA2_FD_H
+@@ -91,6 +66,27 @@ struct dpaa2_fd {
+ #define SG_BPID_MASK		0x3FFF
+ #define SG_FINAL_FLAG_MASK	0x1
+ #define SG_FINAL_FLAG_SHIFT	15
++#define FL_SHORT_LEN_FLAG_MASK	0x1
++#define FL_SHORT_LEN_FLAG_SHIFT	14
++#define FL_SHORT_LEN_MASK	0x3FFFF
++#define FL_OFFSET_MASK		0x0FFF
++#define FL_FORMAT_MASK		0x3
++#define FL_FORMAT_SHIFT		12
++#define FL_BPID_MASK		0x3FFF
++#define FL_FINAL_FLAG_MASK	0x1
++#define FL_FINAL_FLAG_SHIFT	15
++
++/* Error bits in FD CTRL */
++#define FD_CTRL_ERR_MASK	0x000000FF
++#define FD_CTRL_UFD		0x00000004
++#define FD_CTRL_SBE		0x00000008
++#define FD_CTRL_FLC		0x00000010
++#define FD_CTRL_FSE		0x00000020
++#define FD_CTRL_FAERR		0x00000040
++
++/* Annotation bits in FD CTRL */
++#define FD_CTRL_PTA		0x00800000
++#define FD_CTRL_PTV1		0x00400000
+ 
+ enum dpaa2_fd_format {
+ 	dpaa2_fd_single = 0,
+@@ -312,7 +308,7 @@ enum dpaa2_sg_format {
+  */
+ static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
+ {
+-	return le64_to_cpu((dma_addr_t)sg->addr);
++	return (dma_addr_t)le64_to_cpu(sg->addr);
+ }
+ 
+ /**
+@@ -443,9 +439,243 @@ static inline bool dpaa2_sg_is_final(con
+  */
+ static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
+ {
+-	sg->format_offset &= cpu_to_le16(~(SG_FINAL_FLAG_MASK
+-					 << SG_FINAL_FLAG_SHIFT));
++	sg->format_offset &= cpu_to_le16((~(SG_FINAL_FLAG_MASK
++					 << SG_FINAL_FLAG_SHIFT)) & 0xFFFF);
+ 	sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
+ }
+ 
++/**
++ * struct dpaa2_fl_entry - structure for frame list entry.
++ * @addr:          address in the FLE
++ * @len:           length in the FLE
++ * @bpid:          buffer pool ID
++ * @format_offset: format, offset, and short-length fields
++ * @frc:           frame context
++ * @ctrl:          control bits...including pta, pvt1, pvt2, err, etc
++ * @flc:           flow context address
++ */
++struct dpaa2_fl_entry {
++	__le64 addr;
++	__le32 len;
++	__le16 bpid;
++	__le16 format_offset;
++	__le32 frc;
++	__le32 ctrl;
++	__le64 flc;
++};
++
++enum dpaa2_fl_format {
++	dpaa2_fl_single = 0,
++	dpaa2_fl_res,
++	dpaa2_fl_sg
++};
++
++/**
++ * dpaa2_fl_get_addr() - get the addr field of FLE
++ * @fle: the given frame list entry
++ *
++ * Return the address in the frame list entry.
++ */
++static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
++{
++	return (dma_addr_t)le64_to_cpu(fle->addr);
++}
++
++/**
++ * dpaa2_fl_set_addr() - Set the addr field of FLE
++ * @fle: the given frame list entry
++ * @addr: the address needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
++				     dma_addr_t addr)
++{
++	fle->addr = cpu_to_le64(addr);
++}
++
++/**
++ * dpaa2_fl_get_frc() - Get the frame context in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the frame context field in the frame lsit entry.
++ */
++static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
++{
++	return le32_to_cpu(fle->frc);
++}
++
++/**
++ * dpaa2_fl_set_frc() - Set the frame context in the FLE
++ * @fle: the given frame list entry
++ * @frc: the frame context needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
++{
++	fle->frc = cpu_to_le32(frc);
++}
++
++/**
++ * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the control bits field in the frame list entry.
++ */
++static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
++{
++	return le32_to_cpu(fle->ctrl);
++}
++
++/**
++ * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
++ * @fle: the given frame list entry
++ * @ctrl: the control bits to be set in the frame list entry
++ */
++static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
++{
++	fle->ctrl = cpu_to_le32(ctrl);
++}
++
++/**
++ * dpaa2_fl_get_flc() - Get the flow context in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the flow context in the frame list entry.
++ */
++static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
++{
++	return (dma_addr_t)le64_to_cpu(fle->flc);
++}
++
++/**
++ * dpaa2_fl_set_flc() - Set the flow context field of FLE
++ * @fle: the given frame list entry
++ * @flc_addr: the flow context needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
++				    dma_addr_t flc_addr)
++{
++	fle->flc = cpu_to_le64(flc_addr);
++}
++
++static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
++{
++	return !!((le16_to_cpu(fle->format_offset) >>
++		  FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
++}
++
++/**
++ * dpaa2_fl_get_len() - Get the length in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the length field in the frame list entry.
++ */
++static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
++{
++	if (dpaa2_fl_short_len(fle))
++		return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
++
++	return le32_to_cpu(fle->len);
++}
++
++/**
++ * dpaa2_fl_set_len() - Set the length field of FLE
++ * @fle: the given frame list entry
++ * @len: the length needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
++{
++	fle->len = cpu_to_le32(len);
++}
++
++/**
++ * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
++ * @fle: the given frame list entry
++ *
++ * Return the offset.
++ */
++static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
++{
++	return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
++}
++
++/**
++ * dpaa2_fl_set_offset() - Set the offset field of FLE
++ * @fle: the given frame list entry
++ * @offset: the offset needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
++{
++	fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
++	fle->format_offset |= cpu_to_le16(offset);
++}
++
++/**
++ * dpaa2_fl_get_format() - Get the format field in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the format.
++ */
++static inline enum dpaa2_fl_format dpaa2_fl_get_format(
++					const struct dpaa2_fl_entry *fle)
++{
++	return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
++				       FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
++}
++
++/**
++ * dpaa2_fl_set_format() - Set the format field of FLE
++ * @fle: the given frame list entry
++ * @format: the format needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
++				       enum dpaa2_fl_format format)
++{
++	fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
++	fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
++}
++
++/**
++ * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the buffer pool id.
++ */
++static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
++{
++	return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
++}
++
++/**
++ * dpaa2_fl_set_bpid() - Set the bpid field of FLE
++ * @fle: the given frame list entry
++ * @bpid: buffer pool id to be set
++ */
++static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
++{
++	fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
++	fle->bpid |= cpu_to_le16(bpid);
++}
++
++/**
++ * dpaa2_fl_is_final() - Check final bit in FLE
++ * @fle: the given frame list entry
++ *
++ * Return bool.
++ */
++static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
++{
++	return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
++}
++
++/**
++ * dpaa2_fl_set_final() - Set the final bit in FLE
++ * @fle: the given frame list entry
++ * @final: the final boolean to be set
++ */
++static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
++{
++	fle->format_offset &= cpu_to_le16(~(FL_FINAL_FLAG_MASK <<
++					    FL_FINAL_FLAG_SHIFT));
++	fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
++}
++
+ #endif /* __FSL_DPAA2_FD_H */
+--- a/drivers/staging/fsl-mc/include/dpaa2-global.h
++++ b/drivers/staging/fsl-mc/include/dpaa2-global.h
+@@ -1,33 +1,8 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2014-2016 Freescale Semiconductor Inc.
+  * Copyright 2016 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of Freescale Semiconductor nor the
+- *       names of its contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef __FSL_DPAA2_GLOBAL_H
+ #define __FSL_DPAA2_GLOBAL_H
+--- a/drivers/staging/fsl-mc/include/dpaa2-io.h
++++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
+@@ -1,33 +1,8 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2014-2016 Freescale Semiconductor Inc.
+- * Copyright NXP
++ * Copyright 2017 NXP
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of Freescale Semiconductor nor the
+- *       names of its contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef __FSL_DPAA2_IO_H
+ #define __FSL_DPAA2_IO_H
+@@ -88,6 +63,8 @@ void dpaa2_io_down(struct dpaa2_io *d);
+ 
+ irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
+ 
++struct dpaa2_io *dpaa2_io_service_select(int cpu);
++
+ /**
+  * struct dpaa2_io_notification_ctx - The DPIO notification context structure
+  * @cb:           The callback to be invoked when the notification arrives
+@@ -103,7 +80,7 @@ irqreturn_t dpaa2_io_irq(struct dpaa2_io
+  * Used when a FQDAN/CDAN registration is made by drivers.
+  */
+ struct dpaa2_io_notification_ctx {
+-	void (*cb)(struct dpaa2_io_notification_ctx *);
++	void (*cb)(struct dpaa2_io_notification_ctx *ctx);
+ 	int is_cdan;
+ 	u32 id;
+ 	int desired_cpu;
+@@ -129,9 +106,9 @@ int dpaa2_io_service_enqueue_fq(struct d
+ 				const struct dpaa2_fd *fd);
+ int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
+ 				u16 qdbin, const struct dpaa2_fd *fd);
+-int dpaa2_io_service_release(struct dpaa2_io *d, u32 bpid,
++int dpaa2_io_service_release(struct dpaa2_io *d, u16 bpid,
+ 			     const u64 *buffers, unsigned int num_buffers);
+-int dpaa2_io_service_acquire(struct dpaa2_io *d, u32 bpid,
++int dpaa2_io_service_acquire(struct dpaa2_io *d, u16 bpid,
+ 			     u64 *buffers, unsigned int num_buffers);
+ 
+ struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
+@@ -139,4 +116,64 @@ struct dpaa2_io_store *dpaa2_io_store_cr
+ void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
+ struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
+ 
++/* Order Restoration Support */
++int dpaa2_io_service_enqueue_orp_fq(struct dpaa2_io *d, u32 fqid,
++				    const struct dpaa2_fd *fd, u16 orpid,
++				    u16 seqnum, int last);
++
++int dpaa2_io_service_enqueue_orp_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
++				    u16 qdbin, const struct dpaa2_fd *fd,
++				    u16 orpid, u16 seqnum, int last);
++
++int dpaa2_io_service_orp_seqnum_drop(struct dpaa2_io *d, u16 orpid,
++				     u16 seqnum);
++
++/***************/
++/* CSCN        */
++/***************/
++
++/**
++ * struct dpaa2_cscn - The CSCN message format
++ * @verb: identifies the type of message (should be 0x27).
++ * @stat: status bits related to dequeuing response (not used)
++ * @state: bit 0 = 0/1 if CG is no/is congested
++ * @reserved: reserved byte
++ * @cgid: congest grp ID - the first 16 bits
++ * @ctx: context data
++ *
++ * Congestion management can be implemented in software through
++ * the use of Congestion State Change Notifications (CSCN). These
++ * are messages written by DPAA2 hardware to memory whenever the
++ * instantaneous count (I_CNT field in the CG) exceeds the
++ * Congestion State (CS) entrance threshold, signifying congestion
++ * entrance, or when the instantaneous count returns below exit
++ * threshold, signifying congestion exit. The format of the message
++ * is given by the dpaa2_cscn structure. Bit 0 of the state field
++ * represents congestion state written by the hardware.
++ */
++struct dpaa2_cscn {
++	u8 verb;
++	u8 stat;
++	u8 state;
++	u8 reserved;
++	__le32 cgid;
++	__le64 ctx;
++};
++
++#define DPAA2_CSCN_SIZE                        64
++#define DPAA2_CSCN_ALIGN               16
++
++#define DPAA2_CSCN_STATE_MASK          0x1
++#define DPAA2_CSCN_CONGESTED           1
++
++static inline bool dpaa2_cscn_state_congested(struct dpaa2_cscn *cscn)
++{
++	return ((cscn->state & DPAA2_CSCN_STATE_MASK) == DPAA2_CSCN_CONGESTED);
++}
++
++int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid,
++			    u32 *fcnt, u32 *bcnt);
++int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid,
++			    u32 *num);
++
+ #endif /* __FSL_DPAA2_IO_H */
+--- a/drivers/staging/fsl-mc/include/dpbp.h
++++ b/drivers/staging/fsl-mc/include/dpbp.h
+@@ -1,34 +1,7 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+ /*
+  * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef __FSL_DPBP_H
+ #define __FSL_DPBP_H
+--- a/drivers/staging/fsl-mc/include/dpcon.h
++++ b/drivers/staging/fsl-mc/include/dpcon.h
+@@ -1,33 +1,7 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
+  *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+  */
+ #ifndef __FSL_DPCON_H
+ #define __FSL_DPCON_H
+--- /dev/null
++++ b/drivers/staging/fsl-mc/include/dpopr.h
+@@ -0,0 +1,110 @@
++/*
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_DPOPR_H_
++#define __FSL_DPOPR_H_
++
++/* Data Path Order Restoration API
++ * Contains initialization APIs and runtime APIs for the Order Restoration
++ */
++
++/** Order Restoration properties */
++
++/**
++ * Create a new Order Point Record option
++ */
++#define OPR_OPT_CREATE 0x1
++/**
++ * Retire an existing Order Point Record option
++ */
++#define OPR_OPT_RETIRE 0x2
++
++/**
++ * struct opr_cfg - Structure representing OPR configuration
++ * @oprrws: Order point record (OPR) restoration window size (0 to 5)
++ *			0 - Window size is 32 frames.
++ *			1 - Window size is 64 frames.
++ *			2 - Window size is 128 frames.
++ *			3 - Window size is 256 frames.
++ *			4 - Window size is 512 frames.
++ *			5 - Window size is 1024 frames.
++ * @oa: OPR auto advance NESN window size (0 disabled, 1 enabled)
++ * @olws: OPR acceptable late arrival window size (0 to 3)
++ *			0 - Disabled. Late arrivals are always rejected.
++ *			1 - Window size is 32 frames.
++ *			2 - Window size is the same as the OPR restoration
++ *				window size configured in the OPRRWS field.
++ *			3 - Window size is 8192 frames. Late arrivals are
++ *				always accepted.
++ * @oeane: Order restoration list (ORL) resource exhaustion
++ *			advance NESN enable (0 disabled, 1 enabled)
++ * @oloe: OPR loose ordering enable (0 disabled, 1 enabled)
++ */
++struct opr_cfg {
++	u8 oprrws;
++	u8 oa;
++	u8 olws;
++	u8 oeane;
++	u8 oloe;
++};
++
++/**
++ * struct opr_qry - Structure representing OPR configuration
++ * @enable: Enabled state
++ * @rip: Retirement In Progress
++ * @ndsn: Next dispensed sequence number
++ * @nesn: Next expected sequence number
++ * @ea_hseq: Early arrival head sequence number
++ * @hseq_nlis: HSEQ not last in sequence
++ * @ea_tseq: Early arrival tail sequence number
++ * @tseq_nlis: TSEQ not last in sequence
++ * @ea_tptr: Early arrival tail pointer
++ * @ea_hptr: Early arrival head pointer
++ * @opr_id: Order Point Record ID
++ * @opr_vid: Order Point Record Virtual ID
++ */
++struct opr_qry {
++	char enable;
++	char rip;
++	u16 ndsn;
++	u16 nesn;
++	u16 ea_hseq;
++	char hseq_nlis;
++	u16 ea_tseq;
++	char tseq_nlis;
++	u16 ea_tptr;
++	u16 ea_hptr;
++	u16 opr_id;
++	u16 opr_vid;
++};
++
++#endif /* __FSL_DPOPR_H_ */
+--- a/drivers/staging/fsl-mc/include/mc.h
++++ b/drivers/staging/fsl-mc/include/mc.h
+@@ -1,12 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0 */
+ /*
+  * Freescale Management Complex (MC) bus public interface
+  *
+  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+  * Author: German Rivera <German.Rivera@freescale.com>
+  *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+  */
+ #ifndef _FSL_MC_H_
+ #define _FSL_MC_H_