aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch
diff options
context:
space:
mode:
authorBiwen Li <biwen.li@nxp.com>2018-11-02 11:21:57 +0800
committerHauke Mehrtens <hauke@hauke-m.de>2018-12-18 20:17:23 +0100
commit0a827ebd2fa3c7dc210aff0a30d0dc1d536ed89c (patch)
treeb80223fffb0814b6db33f48dd3aaa047cd3e0299 /target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch
parent7bd6969acce763a7117b33a6647b8c5dbbf2b0aa (diff)
downloadupstream-0a827ebd2fa3c7dc210aff0a30d0dc1d536ed89c.tar.gz
upstream-0a827ebd2fa3c7dc210aff0a30d0dc1d536ed89c.tar.bz2
upstream-0a827ebd2fa3c7dc210aff0a30d0dc1d536ed89c.zip
layerscape: upgrade kernel to 4.14
This patch is to upgrade kernel to 4.14 for layerscape. patches-4.14 for layerscape included two categories. - NXP Layerscape SDK kernel-4.14 patches All patches on tag LSDK-18.09-V4.14 were ported to OpenWrt kernel. Since there were hundreds patches, we had to make an all-in-one patch for each IP/feature. See below links for LSDK kernel. https://lsdk.github.io/components.html https://source.codeaurora.org/external/qoriq/qoriq-components/linux - Non-LSDK kernel patches Other patches which were not in LSDK were just put in patches-4.14. Kept below patches from patches-4.9. 303-dts-layerscape-add-traverse-ls1043.patch 821-add-esdhc-vsel-to-ls1043.patch 822-rgmii-fixed-link.patch Renamed and rebase them as below in patches-4.14, 303-add-DTS-for-Traverse-LS1043-Boards.patch 712-sdk-dpaa-rgmii-fixed-link.patch 824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch')
-rw-r--r--target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch6848
1 files changed, 6848 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch b/target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch
new file mode 100644
index 0000000000..afe8d450d9
--- /dev/null
+++ b/target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch
@@ -0,0 +1,6848 @@
+From caecd8632a257759735ed6dd9354091cae8a5746 Mon Sep 17 00:00:00 2001
+From: Biwen Li <biwen.li@nxp.com>
+Date: Fri, 16 Nov 2018 17:11:32 +0800
+Subject: [PATCH] dts: support layerscape This is an integrated patch of dts
+ for layerscape
+
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
+Signed-off-by: Alan Wang <alan.wang@nxp.com>
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
+Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
+Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
+Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
+Signed-off-by: Changming Huang <jerry.huang@nxp.com>
+Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
+Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
+Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
+Signed-off-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
+Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
+Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
+Signed-off-by: Biwen Li <biwen.li@nxp.com>
+---
+ arch/arm/boot/dts/ls1021a-qds.dts | 28 +
+ arch/arm/boot/dts/ls1021a-twr.dts | 27 +
+ arch/arm/boot/dts/ls1021a.dtsi | 105 +++-
+ arch/arm64/boot/dts/freescale/Makefile | 9 +
+ .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++++
+ .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 96 ++--
+ .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 177 +++++++
+ .../boot/dts/freescale/fsl-ls1012a-qds.dts | 133 +++--
+ .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 100 ++--
+ .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 179 +++++--
+ .../boot/dts/freescale/fsl-ls1043-post.dtsi | 3 +-
+ .../dts/freescale/fsl-ls1043a-qds-sdk.dts | 71 +++
+ .../boot/dts/freescale/fsl-ls1043a-qds.dts | 201 ++++++--
+ .../dts/freescale/fsl-ls1043a-rdb-sdk.dts | 71 +++
+ .../dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++++
+ .../boot/dts/freescale/fsl-ls1043a-rdb.dts | 75 ++-
+ .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 196 +++++--
+ .../boot/dts/freescale/fsl-ls1046-post.dtsi | 2 +-
+ .../dts/freescale/fsl-ls1046a-qds-sdk.dts | 79 +++
+ .../boot/dts/freescale/fsl-ls1046a-qds.dts | 189 +++++--
+ .../dts/freescale/fsl-ls1046a-rdb-sdk.dts | 115 +++++
+ .../dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 ++++
+ .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 44 +-
+ .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 182 +++++--
+ .../boot/dts/freescale/fsl-ls1088a-qds.dts | 88 ++--
+ .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 150 ++++--
+ .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 486 ++++++++++++++++--
+ .../boot/dts/freescale/fsl-ls2080a-qds.dts | 100 ++--
+ .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 118 +++--
+ .../boot/dts/freescale/fsl-ls2080a-simu.dts | 38 +-
+ .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 42 +-
+ .../boot/dts/freescale/fsl-ls2081a-rdb.dts | 163 ++++++
+ .../boot/dts/freescale/fsl-ls2088a-qds.dts | 158 ++++--
+ .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 118 +++--
+ .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 44 +-
+ .../boot/dts/freescale/fsl-ls208xa-qds.dtsi | 43 +-
+ .../boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 60 +--
+ .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 210 ++++++--
+ .../dts/freescale/qoriq-bman-portals-sdk.dtsi | 55 ++
+ .../dts/freescale/qoriq-bman-portals.dtsi | 8 +-
+ .../boot/dts/freescale/qoriq-dpaa-eth.dtsi | 97 ++++
+ .../dts/freescale/qoriq-fman3-0-10g-0.dtsi | 11 +-
+ .../dts/freescale/qoriq-fman3-0-10g-1.dtsi | 11 +-
+ .../dts/freescale/qoriq-fman3-0-1g-0.dtsi | 7 +-
+ .../dts/freescale/qoriq-fman3-0-1g-1.dtsi | 7 +-
+ .../dts/freescale/qoriq-fman3-0-1g-2.dtsi | 7 +-
+ .../dts/freescale/qoriq-fman3-0-1g-3.dtsi | 7 +-
+ .../dts/freescale/qoriq-fman3-0-1g-4.dtsi | 7 +-
+ .../dts/freescale/qoriq-fman3-0-1g-5.dtsi | 7 +-
+ .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
+ .../boot/dts/freescale/qoriq-fman3-0.dtsi | 54 +-
+ .../dts/freescale/qoriq-qman-portals-sdk.dtsi | 38 ++
+ .../dts/freescale/qoriq-qman-portals.dtsi | 9 +-
+ .../boot/dts/fsl/qoriq-fman-0-10g-0.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-0-1g-0.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-0-1g-1.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-0-1g-2.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-0-1g-3.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-0-1g-4.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-1-10g-0.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-1-1g-0.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-1-1g-1.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-1-1g-2.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-1-1g-3.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman-1-1g-4.dtsi | 4 +-
+ .../fsl/qoriq-fman3-0-10g-0-best-effort.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
+ .../fsl/qoriq-fman3-0-10g-1-best-effort.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi | 4 +-
+ .../boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi | 4 +-
+ 83 files changed, 3742 insertions(+), 1000 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
+
+--- a/arch/arm/boot/dts/ls1021a-qds.dts
++++ b/arch/arm/boot/dts/ls1021a-qds.dts
+@@ -124,6 +124,21 @@
+ };
+ };
+
++&qspi {
++ num-cs = <2>;
++ status = "okay";
++
++ qflash0: s25fl128s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ };
++};
++
+ &enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1c>;
+@@ -239,6 +254,11 @@
+ device-width = <1>;
+ };
+
++ nand@2,0 {
++ compatible = "fsl,ifc-nand";
++ reg = <0x2 0x0 0x10000>;
++ };
++
+ fpga: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+@@ -331,3 +351,11 @@
+ &uart1 {
+ status = "okay";
+ };
++
++&can0 {
++ status = "okay";
++};
++
++&can1 {
++ status = "okay";
++};
+--- a/arch/arm/boot/dts/ls1021a-twr.dts
++++ b/arch/arm/boot/dts/ls1021a-twr.dts
+@@ -142,6 +142,21 @@
+ };
+ };
+
++&qspi {
++ num-cs = <2>;
++ status = "okay";
++
++ qflash0: n25q128a13@0 {
++ compatible = "n25q128a13", "jedec,spi-nor";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ };
++};
++
+ &enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy2>;
+@@ -228,6 +243,10 @@
+ };
+ };
+
++&esdhc {
++ status = "okay";
++};
++
+ &sai1 {
+ status = "okay";
+ };
+@@ -243,3 +262,11 @@
+ &uart1 {
+ status = "okay";
+ };
++
++&can0 {
++ status = "okay";
++};
++
++&can1 {
++ status = "okay";
++};
+--- a/arch/arm/boot/dts/ls1021a.dtsi
++++ b/arch/arm/boot/dts/ls1021a.dtsi
+@@ -146,12 +146,13 @@
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
++ big-endian;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1021a-dcfg", "syscon";
+- reg = <0x0 0x1ee0000 0x0 0x10000>;
++ reg = <0x0 0x1ee0000 0x0 0x1000>;
+ big-endian;
+ };
+
+@@ -334,25 +335,41 @@
+ status = "disabled";
+ };
+
++ qspi: quadspi@1550000 {
++ compatible = "fsl,ls1021a-qspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x1550000 0x0 0x10000>,
++ <0x0 0x40000000 0x0 0x4000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "qspi_en", "qspi";
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ big-endian;
++ status = "disabled";
++ };
++
+ i2c0: i2c@2180000 {
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 1>;
++ fsl-scl-gpio = <&gpio3 23 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 1>;
++ fsl-scl-gpio = <&gpio3 23 0>;
+ status = "disabled";
+ };
+
+@@ -497,6 +514,17 @@
+ status = "disabled";
+ };
+
++ ftm0: ftm0@29d0000 {
++ compatible = "fsl,ls1021a-ftm-alarm";
++ reg = <0x0 0x29d0000 0x0 0x10000>,
++ <0x0 0x1ee2144 0x0 0x4>,
++ <0x0 0x0157051c 0x0 0x4>;
++ reg-names = "ftm", "pmctrl", "scrachpad";
++ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++ big-endian;
++ status = "okay";
++ };
++
+ wdog0: watchdog@2ad0000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+@@ -550,6 +578,25 @@
+ <&clockgen 4 1>;
+ };
+
++ qdma: qdma@8390000 {
++ compatible = "fsl,ls1021a-qdma";
++ reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
++ <0x0 0x8389000 0x0 0x1000>, /* Status regs */
++ <0x0 0x838a000 0x0 0x2000>; /* Block regs */
++ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "qdma-error",
++ "qdma-queue0", "qdma-queue1";
++ channels = <8>;
++ block-number = <2>;
++ block-offset = <0x1000>;
++ queues = <2>;
++ status-sizes = <64>;
++ queue-sizes = <64 64>;
++ big-endian;
++ };
++
+ dcu: dcu@2ce0000 {
+ compatible = "fsl,ls1021a-dcu";
+ reg = <0x0 0x2ce0000 0x0 0x10000>;
+@@ -684,6 +731,10 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ configure-gfladj;
++ usb3-lpm-capable;
++ snps,dis-u1u2-when-u3-quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ pcie@3400000 {
+@@ -691,7 +742,9 @@
+ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
++ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++ interrupt-names = "pme", "aer";
+ fsl,pcie-scfg = <&scfg 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+@@ -714,7 +767,9 @@
+ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++ interrupt-names = "pme", "aer";
+ fsl,pcie-scfg = <&scfg 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+@@ -731,5 +786,45 @@
+ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ };
++
++ can0: can@2a70000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2a70000 0x0 0x1000>;
++ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
++
++ can1: can@2a80000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2a80000 0x0 0x1000>;
++ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
++
++ can2: can@2a90000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2a90000 0x0 0x1000>;
++ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
++
++ can3: can@2aa0000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2aa0000 0x0 0x1000>;
++ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
+ };
+ };
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -1,15 +1,24 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+@@ -0,0 +1,123 @@
++/*
++ * Device Tree file for NXP LS1012A 2G5RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A 2G5RDB Board";
++ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++};
++
++&duart0 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&qspi {
++ num-cs = <2>;
++ bus-num = <0>;
++ status = "okay";
++
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ m25p,fast-read;
++ reg = <0>;
++ };
++};
++
++&sata {
++ status = "okay";
++};
++
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -1,45 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS1012A Freedom Board.
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ /dts-v1/;
+
+@@ -49,6 +13,11 @@
+ model = "LS1012A Freedom Board";
+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+@@ -110,6 +79,44 @@
+ };
+ };
+
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
++
+ &sai2 {
+ status = "okay";
+ };
+@@ -117,3 +124,18 @@
+ &sata {
+ status = "okay";
+ };
++
++&qspi {
++ status = "okay";
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ m25p,fast-read;
++ reg = <0>;
++ spi-rx-bus-width = <2>;
++ spi-tx-bus-width = <2>;
++ };
++
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+@@ -0,0 +1,177 @@
++/*
++ * Device Tree file for NXP LS1012A FRWY Board.
++ *
++ * Copyright 2018 NXP
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A FRWY Board";
++ compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
++
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++
++ sys_mclk: clock-mclk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <25000000>;
++ };
++
++ reg_1p8v: regulator-1p8v {
++ compatible = "regulator-fixed";
++ regulator-name = "1P8V";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ };
++
++ sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,widgets =
++ "Microphone", "Microphone Jack",
++ "Headphone", "Headphone Jack",
++ "Speaker", "Speaker Ext",
++ "Line", "Line In Jack";
++ simple-audio-card,routing =
++ "MIC_IN", "Microphone Jack",
++ "Microphone Jack", "Mic Bias",
++ "LINE_IN", "Line In Jack",
++ "Headphone Jack", "HP_OUT",
++ "Speaker Ext", "LINE_OUT";
++
++ simple-audio-card,cpu {
++ sound-dai = <&sai2>;
++ frame-master;
++ bitclock-master;
++ };
++
++ simple-audio-card,codec {
++ sound-dai = <&codec>;
++ frame-master;
++ bitclock-master;
++ system-clock-frequency = <25000000>;
++ };
++ };
++};
++
++&pcie {
++ status = "okay";
++};
++
++&duart0 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ codec: sgtl5000@a {
++ compatible = "fsl,sgtl5000";
++ #sound-dai-cells = <0>;
++ reg = <0xa>;
++ VDDA-supply = <&reg_1p8v>;
++ VDDIO-supply = <&reg_1p8v>;
++ clocks = <&sys_mclk>;
++ };
++};
++
++&qspi {
++ num-cs = <1>;
++ bus-num = <0>;
++ status = "okay";
++
++ qflash0: w25q16dw@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ m25p,fast-read;
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
++
++&sai2 {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+@@ -1,45 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS1012A QDS Board.
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ /dts-v1/;
+
+@@ -49,6 +13,11 @@
+ model = "LS1012A QDS Board";
+ compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+@@ -93,6 +62,43 @@
+ };
+ };
+
++&pcie {
++ status = "okay";
++};
++
++&dspi {
++ bus-num = <0>;
++ status = "okay";
++
++ flash@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "n25q128a11", "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++ };
++
++ flash@1 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "sst25wf040b", "jedec,spi-nor";
++ spi-cpol;
++ spi-cpha;
++ reg = <1>;
++ spi-max-frequency = <10000000>;
++ };
++
++ flash@2 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "en25s64", "jedec,spi-nor";
++ spi-cpol;
++ spi-cpha;
++ reg = <2>;
++ spi-max-frequency = <10000000>;
++ };
++};
++
+ &duart0 {
+ status = "okay";
+ };
+@@ -131,6 +137,44 @@
+ };
+ };
+
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x2>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x3>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
++
+ &sai2 {
+ status = "okay";
+ };
+@@ -138,3 +182,18 @@
+ &sata {
+ status = "okay";
+ };
++
++&qspi {
++ status = "okay";
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ m25p,fast-read;
++ reg = <0>;
++ spi-rx-bus-width = <2>;
++ spi-tx-bus-width = <2>;
++ };
++
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -1,45 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS1012A RDB Board.
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ /dts-v1/;
+
+@@ -48,6 +12,15 @@
+ / {
+ model = "LS1012A RDB Board";
+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++};
++
++&pcie {
++ status = "okay";
+ };
+
+ &duart0 {
+@@ -74,3 +47,56 @@
+ &sata {
+ status = "okay";
+ };
++
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
++ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "rgmii-txid";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
++
++&qspi {
++ status = "okay";
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ m25p,fast-read;
++ reg = <0>;
++ spi-rx-bus-width = <2>;
++ spi-tx-bus-width = <2>;
++ };
++
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+@@ -1,45 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+@@ -70,6 +34,24 @@
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_PH20>;
++ };
++ };
++
++ idle-states {
++ /*
++ * PSCI node is not added default, U-boot will add missing
++ * parts if it determines to use PSCI.
++ */
++ entry-method = "arm,psci";
++
++ CPU_PH20: cpu-ph20 {
++ compatible = "arm,idle-state";
++ idle-state-name = "PH20";
++ arm,psci-suspend-param = <0x0>;
++ entry-latency-us = <1000>;
++ exit-latency-us = <1000>;
++ min-residency-us = <3000>;
+ };
+ };
+
+@@ -247,7 +229,7 @@
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1012a-dcfg",
+ "syscon";
+- reg = <0x0 0x1ee0000 0x0 0x10000>;
++ reg = <0x0 0x1ee0000 0x0 0x1000>;
+ big-endian;
+ };
+
+@@ -335,13 +317,23 @@
+ };
+ };
+
++ ftm0: ftm0@29d0000 {
++ compatible = "fsl,ls1012a-ftm-alarm";
++ reg = <0x0 0x29d0000 0x0 0x10000>,
++ <0x0 0x1ee2140 0x0 0x4>;
++ reg-names = "ftm", "pmctrl";
++ interrupts = <0 86 0x4>;
++ big-endian;
++ };
++
+ i2c0: i2c@2180000 {
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&clockgen 4 0>;
++ clocks = <&clockgen 4 3>;
++ fsl-scl-gpio = <&gpio0 13 0>;
+ status = "disabled";
+ };
+
+@@ -351,7 +343,20 @@
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 3>;
++ status = "disabled";
++ };
++
++ dspi: dspi@2100000 {
++ compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2100000 0x0 0x10000>;
++ interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
++ spi-num-chipselects = <5>;
++ big-endian;
+ status = "disabled";
+ };
+
+@@ -400,6 +405,20 @@
+ big-endian;
+ };
+
++ qspi: quadspi@1550000 {
++ compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x1550000 0x0 0x10000>,
++ <0x0 0x40000000 0x0 0x10000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "qspi_en", "qspi";
++ clocks = <&clockgen 4 0>, <&clockgen 4 0>;
++ big-endian;
++ status = "disabled";
++ };
++
+ sai1: sai@2b50000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+@@ -451,6 +470,7 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ sata: sata@3200000 {
+@@ -471,5 +491,84 @@
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
++
++ msi: msi-controller1@1572000 {
++ compatible = "fsl,ls1012a-msi";
++ reg = <0x0 0x1572000 0x0 0x8>;
++ msi-controller;
++ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ pcie: pcie@3400000 {
++ compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
++ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <0 118 0x4>, /* AER interrupt */
++ <0 117 0x4>; /* PME interrupt */
++ interrupt-names = "aer", "pme";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ num-lanes = <4>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&msi>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++
++ rcpm: rcpm@1ee2000 {
++ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
++ reg = <0x0 0x1ee2000 0x0 0x1000>;
++ fsl,#rcpm-wakeup-cells = <1>;
++ };
++ };
++
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ pfe_reserved: packetbuffer@83400000 {
++ reg = <0 0x83400000 0 0xc00000>;
++ };
++ };
++
++ pfe: pfe@04000000 {
++ compatible = "fsl,pfe";
++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
++ reg-names = "pfe", "pfe-ddr";
++ fsl,pfe-num-interfaces = <0x2>;
++ interrupts = <0 172 0x4>, /* HIF interrupt */
++ <0 173 0x4>, /*HIF_NOCPY interrupt */
++ <0 174 0x4>; /* WoL interrupt */
++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
++ memory-region = <&pfe_reserved>;
++ fsl,pfe-scfg = <&scfg 0>;
++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
++ clocks = <&clockgen 4 0>;
++ clock-names = "pfe";
++
++ status = "okay";
++ pfe_mac0: ethernet@0 {
++ };
++
++ pfe_mac1: ethernet@1 {
++ };
++ };
++
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
+ };
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+@@ -1,9 +1,8 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 device tree nodes for ls1043
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+- *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ &soc {
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+@@ -0,0 +1,71 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1043a-qds.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++ compatible = "fsl,bman-fbpr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++ compatible = "fsl,qman-fqd";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++ compatible = "fsl,qman-pfdr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fman0 {
++ compatible = "fsl,fman", "simple-bus";
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+@@ -1,47 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -60,6 +23,22 @@
+ serial1 = &duart1;
+ serial2 = &duart2;
+ serial3 = &duart3;
++ sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
++ sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
++ sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
++ sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
++ qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
++ qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
++ qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
++ qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
++ qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
++ qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
++ qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
++ qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
++ emi1_slot1 = &ls1043mdio_s1;
++ emi1_slot2 = &ls1043mdio_s2;
++ emi1_slot3 = &ls1043mdio_s3;
++ emi1_slot4 = &ls1043mdio_s4;
+ };
+
+ chosen {
+@@ -179,7 +158,153 @@
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
+ };
+ };
+
+ #include "fsl-ls1043-post.dtsi"
++
++&fman0 {
++ ethernet@e0000 {
++ phy-handle = <&qsgmii_phy_s2_p1>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@e2000 {
++ phy-handle = <&qsgmii_phy_s2_p2>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@e4000 {
++ phy-handle = <&rgmii_phy1>;
++ phy-connection-type = "rgmii";
++ };
++
++ ethernet@e6000 {
++ phy-handle = <&rgmii_phy2>;
++ phy-connection-type = "rgmii";
++ };
++
++ ethernet@e8000 {
++ phy-handle = <&qsgmii_phy_s2_p3>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@ea000 {
++ phy-handle = <&qsgmii_phy_s2_p4>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@f0000 { /* DTSEC9/10GEC1 */
++ fixed-link = <1 1 10000 0 0>;
++ phy-connection-type = "xgmii";
++ };
++};
++
++&fpga {
++ mdio-mux-emi1 {
++ compatible = "mdio-mux-mmioreg", "mdio-mux";
++ mdio-parent-bus = <&mdio0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x54 1>; /* BRDCFG4 */
++ mux-mask = <0xe0>; /* EMI1 */
++
++ /* On-board RGMII1 PHY */
++ ls1043mdio0: mdio@0 {
++ reg = <0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
++ reg = <0x1>;
++ };
++ };
++
++ /* On-board RGMII2 PHY */
++ ls1043mdio1: mdio@1 {
++ reg = <0x20>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
++ reg = <0x2>;
++ };
++ };
++
++ /* Slot 1 */
++ ls1043mdio_s1: mdio@2 {
++ reg = <0x40>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ qsgmii_phy_s1_p1: ethernet-phy@4 {
++ reg = <0x4>;
++ };
++ qsgmii_phy_s1_p2: ethernet-phy@5 {
++ reg = <0x5>;
++ };
++ qsgmii_phy_s1_p3: ethernet-phy@6 {
++ reg = <0x6>;
++ };
++ qsgmii_phy_s1_p4: ethernet-phy@7 {
++ reg = <0x7>;
++ };
++
++ sgmii_phy_s1_p1: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++ };
++
++ /* Slot 2 */
++ ls1043mdio_s2: mdio@3 {
++ reg = <0x60>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ qsgmii_phy_s2_p1: ethernet-phy@8 {
++ reg = <0x8>;
++ };
++ qsgmii_phy_s2_p2: ethernet-phy@9 {
++ reg = <0x9>;
++ };
++ qsgmii_phy_s2_p3: ethernet-phy@a {
++ reg = <0xa>;
++ };
++ qsgmii_phy_s2_p4: ethernet-phy@b {
++ reg = <0xb>;
++ };
++
++ sgmii_phy_s2_p1: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++ };
++
++ /* Slot 3 */
++ ls1043mdio_s3: mdio@4 {
++ reg = <0x80>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ sgmii_phy_s3_p1: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++ };
++
++ /* Slot 4 */
++ ls1043mdio_s4: mdio@5 {
++ reg = <0xa0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ sgmii_phy_s4_p1: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+@@ -0,0 +1,71 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1043a-rdb.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++ compatible = "fsl,bman-fbpr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++ compatible = "fsl,qman-fqd";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++ compatible = "fsl,qman-pfdr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fman0 {
++ compatible = "fsl,fman", "simple-bus";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+@@ -0,0 +1,117 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright (C) 2014-2015, Freescale Semiconductor
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include "fsl-ls1043a-rdb-sdk.dts"
++
++&soc {
++ bp7: buffer-pool@7 {
++ compatible = "fsl,p4080-bpool", "fsl,bpool";
++ fsl,bpid = <7>;
++ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
++ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
++ };
++
++ bp8: buffer-pool@8 {
++ compatible = "fsl,p4080-bpool", "fsl,bpool";
++ fsl,bpid = <8>;
++ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
++ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++ };
++
++ bp9: buffer-pool@9 {
++ compatible = "fsl,p4080-bpool", "fsl,bpool";
++ fsl,bpid = <9>;
++ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
++ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++ };
++
++ fsl,dpaa {
++ compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
++
++ ethernet@0 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
++ fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
++ };
++
++ ethernet@1 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
++ fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
++ };
++
++ ethernet@2 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
++ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
++ };
++
++ ethernet@3 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
++ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
++ };
++
++ ethernet@4 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
++ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
++ };
++
++ ethernet@5 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
++ fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
++ };
++
++ ethernet@8 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
++ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
++
++ };
++ dpa-fman0-oh@2 {
++ compatible = "fsl,dpa-oh";
++ /* Define frame queues for the OH port*/
++ /* <OH Rx error, OH Rx default> */
++ fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
++ fsl,fman-oh-port = <&fman0_oh2>;
++ };
++ };
++};
++/ {
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ usdpaa_mem: usdpaa_mem {
++ compatible = "fsl,usdpaa-mem";
++ alloc-ranges = <0 0 0x10000 0>;
++ size = <0 0x10000000>;
++ alignment = <0 0x10000000>;
++ };
++ };
++};
++
++&fman0 {
++ fman0_oh2: port@83000 {
++ cell-index = <1>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x83000 0x1000>;
++ };
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -1,47 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -86,6 +49,10 @@
+ compatible = "pericom,pt7c4338";
+ reg = <0x68>;
+ };
++ rtc@51 {
++ compatible = "nxp,pcf85263";
++ reg = <0x51>;
++ };
+ };
+
+ &ifc {
+@@ -130,6 +97,38 @@
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
++
++ slic@2 {
++ compatible = "maxim,ds26522";
++ reg = <2>;
++ spi-max-frequency = <2000000>;
++ fsl,spi-cs-sck-delay = <100>;
++ fsl,spi-sck-cs-delay = <50>;
++ };
++
++ slic@3 {
++ compatible = "maxim,ds26522";
++ reg = <3>;
++ spi-max-frequency = <2000000>;
++ fsl,spi-cs-sck-delay = <100>;
++ fsl,spi-sck-cs-delay = <50>;
++ };
++};
++
++&uqe {
++ ucc_hdlc: ucc@2000 {
++ compatible = "fsl,ucc-hdlc";
++ rx-clock-name = "clk8";
++ tx-clock-name = "clk9";
++ fsl,rx-sync-clock = "rsync_pin";
++ fsl,tx-sync-clock = "tsync_pin";
++ fsl,tx-timeslot-mask = <0xfffffffe>;
++ fsl,rx-timeslot-mask = <0xfffffffe>;
++ fsl,tdm-framer-type = "e1";
++ fsl,tdm-id = <0>;
++ fsl,siram-entry-id = <0>;
++ fsl,tdm-interface;
++ };
+ };
+
+ &duart0 {
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -1,47 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ #include <dt-bindings/thermal/thermal.h>
+@@ -81,6 +44,7 @@
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
+ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ cpu1: cpu@1 {
+@@ -89,6 +53,7 @@
+ reg = <0x1>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
++ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ cpu2: cpu@2 {
+@@ -97,6 +62,7 @@
+ reg = <0x2>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
++ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ cpu3: cpu@3 {
+@@ -105,6 +71,7 @@
+ reg = <0x3>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
++ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ l2: l2-cache {
+@@ -112,6 +79,23 @@
+ };
+ };
+
++ idle-states {
++ /*
++ * PSCI node is not added default, U-boot will add missing
++ * parts if it determines to use PSCI.
++ */
++ entry-method = "arm,psci";
++
++ CPU_PH20: cpu-ph20 {
++ compatible = "arm,idle-state";
++ idle-state-name = "PH20";
++ arm,psci-suspend-param = <0x0>;
++ entry-latency-us = <1000>;
++ exit-latency-us = <1000>;
++ min-residency-us = <3000>;
++ };
++ };
++
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+@@ -255,7 +239,7 @@
+
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1043a-dcfg", "syscon";
+- reg = <0x0 0x1ee0000 0x0 0x10000>;
++ reg = <0x0 0x1ee0000 0x0 0x1000>;
+ big-endian;
+ };
+
+@@ -422,7 +406,7 @@
+ };
+
+ i2c0: i2c@2180000 {
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+@@ -432,6 +416,7 @@
+ dmas = <&edma0 1 39>,
+ <&edma0 1 38>;
+ dma-names = "tx", "rx";
++ fsl-scl-gpio = <&gpio4 12 0>;
+ status = "disabled";
+ };
+
+@@ -536,6 +521,72 @@
+ #interrupt-cells = <2>;
+ };
+
++ uqe: uqe@2400000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ device_type = "qe";
++ compatible = "fsl,qe", "simple-bus";
++ ranges = <0x0 0x0 0x2400000 0x40000>;
++ reg = <0x0 0x2400000 0x0 0x480>;
++ brg-frequency = <100000000>;
++ bus-frequency = <200000000>;
++
++ fsl,qe-num-riscs = <1>;
++ fsl,qe-num-snums = <28>;
++
++ qeic: qeic@80 {
++ compatible = "fsl,qe-ic";
++ reg = <0x80 0x80>;
++ #address-cells = <0>;
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ interrupts = <0 77 0x04 0 77 0x04>;
++ };
++
++ si1: si@700 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,ls1043-qe-si",
++ "fsl,t1040-qe-si";
++ reg = <0x700 0x80>;
++ };
++
++ siram1: siram@1000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "fsl,ls1043-qe-siram",
++ "fsl,t1040-qe-siram";
++ reg = <0x1000 0x800>;
++ };
++
++ ucc@2000 {
++ cell-index = <1>;
++ reg = <0x2000 0x200>;
++ interrupts = <32>;
++ interrupt-parent = <&qeic>;
++ };
++
++ ucc@2200 {
++ cell-index = <3>;
++ reg = <0x2200 0x200>;
++ interrupts = <34>;
++ interrupt-parent = <&qeic>;
++ };
++
++ muram@10000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "fsl,qe-muram", "fsl,cpm-muram";
++ ranges = <0x0 0x10000 0x6000>;
++
++ data-only@0 {
++ compatible = "fsl,qe-muram-data",
++ "fsl,cpm-muram-data";
++ reg = <0x0 0x6000>;
++ };
++ };
++ };
++
+ lpuart0: serial@2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+@@ -590,6 +641,16 @@
+ status = "disabled";
+ };
+
++ ftm0: ftm0@29d0000 {
++ compatible = "fsl,ls1043a-ftm-alarm";
++ reg = <0x0 0x29d0000 0x0 0x10000>,
++ <0x0 0x1ee2140 0x0 0x4>;
++ reg-names = "ftm", "pmctrl";
++ interrupts = <0 86 0x4>;
++ big-endian;
++ status = "okay";
++ };
++
+ wdog0: wdog@2ad0000 {
+ compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+@@ -622,6 +683,9 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ usb3-lpm-capable;
++ snps,dis-u1u2-when-u3-quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ usb1: usb3@3000000 {
+@@ -631,6 +695,9 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ usb3-lpm-capable;
++ snps,dis-u1u2-when-u3-quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ usb2: usb3@3100000 {
+@@ -640,6 +707,9 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ usb3-lpm-capable;
++ snps,dis-u1u2-when-u3-quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ sata: sata@3200000 {
+@@ -652,6 +722,27 @@
+ dma-coherent;
+ };
+
++ qdma: qdma@8380000 {
++ compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
++ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
++ <0x0 0x8390000 0x0 0x10000>, /* Status regs */
++ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
++ interrupts = <0 152 0x4>,
++ <0 39 0x4>,
++ <0 40 0x4>,
++ <0 41 0x4>,
++ <0 42 0x4>;
++ interrupt-names = "qdma-error", "qdma-queue0",
++ "qdma-queue1", "qdma-queue2", "qdma-queue3";
++ channels = <8>;
++ block-number = <1>;
++ block-offset = <0x10000>;
++ queues = <2>;
++ status-sizes = <64>;
++ queue-sizes = <64 64>;
++ big-endian;
++ };
++
+ msi1: msi-controller1@1571000 {
+ compatible = "fsl,ls1043a-msi";
+ reg = <0x0 0x1571000 0x0 0x8>;
+@@ -678,9 +769,9 @@
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+- interrupts = <0 118 0x4>, /* controller interrupt */
+- <0 117 0x4>; /* PME interrupt */
+- interrupt-names = "intr", "pme";
++ interrupts = <0 117 0x4>, /* PME interrupt */
++ <0 118 0x4>; /* aer interrupt */
++ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+@@ -703,9 +794,9 @@
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+- interrupts = <0 128 0x4>,
+- <0 127 0x4>;
+- interrupt-names = "intr", "pme";
++ interrupts = <0 127 0x4>,
++ <0 128 0x4>;
++ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+@@ -728,9 +819,9 @@
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+- interrupts = <0 162 0x4>,
+- <0 161 0x4>;
+- interrupt-names = "intr", "pme";
++ interrupts = <0 161 0x4>,
++ <0 162 0x4>;
++ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+@@ -749,6 +840,13 @@
+ };
+ };
+
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
++
+ };
+
+ #include "qoriq-qman-portals.dtsi"
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+@@ -1,9 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 device tree nodes for ls1046
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ &soc {
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+@@ -0,0 +1,79 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1046a-qds.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++ compatible = "fsl,bman-fbpr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++ compatible = "fsl,qman-fqd";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++ compatible = "fsl,qman-pfdr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fsldpaa {
++ ethernet@9 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet7>;
++ dma-coherent;
++ };
++};
++
++&fman0 {
++ compatible = "fsl,fman", "simple-bus";
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+@@ -1,47 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * Shaohui Xie <Shaohui.Xie@nxp.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -61,6 +24,20 @@
+ serial1 = &duart1;
+ serial2 = &duart2;
+ serial3 = &duart3;
++
++ emi1_slot1 = &ls1046mdio_s1;
++ emi1_slot2 = &ls1046mdio_s2;
++ emi1_slot4 = &ls1046mdio_s4;
++
++ sgmii_s1_p1 = &sgmii_phy_s1_p1;
++ sgmii_s1_p2 = &sgmii_phy_s1_p2;
++ sgmii_s1_p3 = &sgmii_phy_s1_p3;
++ sgmii_s1_p4 = &sgmii_phy_s1_p4;
++ sgmii_s4_p1 = &sgmii_phy_s4_p1;
++ qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
++ qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
++ qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
++ qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
+ };
+
+ chosen {
+@@ -208,7 +185,143 @@
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
+ };
+ };
+
+ #include "fsl-ls1046-post.dtsi"
++
++&fman0 {
++ ethernet@e0000 {
++ phy-handle = <&qsgmii_phy_s2_p1>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@e2000 {
++ phy-handle = <&sgmii_phy_s4_p1>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@e4000 {
++ phy-handle = <&rgmii_phy1>;
++ phy-connection-type = "rgmii";
++ };
++
++ ethernet@e6000 {
++ phy-handle = <&rgmii_phy2>;
++ phy-connection-type = "rgmii";
++ };
++
++ ethernet@e8000 {
++ phy-handle = <&sgmii_phy_s1_p3>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@ea000 {
++ phy-handle = <&sgmii_phy_s1_p4>;
++ phy-connection-type = "sgmii";
++ };
++
++ ethernet@f0000 { /* DTSEC9/10GEC1 */
++ phy-handle = <&sgmii_phy_s1_p1>;
++ phy-connection-type = "xgmii";
++ };
++
++ ethernet@f2000 { /* DTSEC10/10GEC2 */
++ phy-handle = <&sgmii_phy_s1_p2>;
++ phy-connection-type = "xgmii";
++ };
++};
++
++&fpga {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ mdio-mux-emi1 {
++ compatible = "mdio-mux-mmioreg", "mdio-mux";
++ mdio-parent-bus = <&mdio0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x54 1>; /* BRDCFG4 */
++ mux-mask = <0xe0>; /* EMI1 */
++
++ /* On-board RGMII1 PHY */
++ ls1046mdio0: mdio@0 {
++ reg = <0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
++ reg = <0x1>;
++ };
++ };
++
++ /* On-board RGMII2 PHY */
++ ls1046mdio1: mdio@1 {
++ reg = <0x20>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
++ reg = <0x2>;
++ };
++ };
++
++ /* Slot 1 */
++ ls1046mdio_s1: mdio@2 {
++ reg = <0x40>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ sgmii_phy_s1_p1: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++
++ sgmii_phy_s1_p2: ethernet-phy@1d {
++ reg = <0x1d>;
++ };
++
++ sgmii_phy_s1_p3: ethernet-phy@1e {
++ reg = <0x1e>;
++ };
++
++ sgmii_phy_s1_p4: ethernet-phy@1f {
++ reg = <0x1f>;
++ };
++ };
++
++ /* Slot 2 */
++ ls1046mdio_s2: mdio@3 {
++ reg = <0x60>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ qsgmii_phy_s2_p1: ethernet-phy@8 {
++ reg = <0x8>;
++ };
++ qsgmii_phy_s2_p2: ethernet-phy@9 {
++ reg = <0x9>;
++ };
++ qsgmii_phy_s2_p3: ethernet-phy@a {
++ reg = <0xa>;
++ };
++ qsgmii_phy_s2_p4: ethernet-phy@b {
++ reg = <0xb>;
++ };
++ };
++
++ /* Slot 4 */
++ ls1046mdio_s4: mdio@5 {
++ reg = <0x80>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ sgmii_phy_s4_p1: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+@@ -0,0 +1,115 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1046a-rdb.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++ compatible = "fsl,bman-fbpr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++ compatible = "fsl,qman-fqd";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++ compatible = "fsl,qman-pfdr";
++ alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fsldpaa {
++ ethernet@0 {
++ status = "disabled";
++ };
++ ethernet@1 {
++ status = "disabled";
++ };
++ ethernet@9 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet7>;
++ dma-coherent;
++ };
++};
++
++&fman0 {
++ compatible = "fsl,fman", "simple-bus";
++};
++
++&mdio9 {
++ pcsphy6: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x8C0 0x40>; /* lane D */
++ };
++};
++
++&mdio10 {
++ pcsphy7: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x880 0x40>; /* lane C */
++ };
++};
++
++/* Update MAC connections to backplane PHYs
++ * &mac9 {
++ * phy-handle = <&pcsphy6>;
++ *};
++ *
++ *&mac10 {
++ * phy-handle = <&pcsphy7>;
++ *};
++*/
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+@@ -0,0 +1,110 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include "fsl-ls1046a-rdb-sdk.dts"
++
++&soc {
++ bp7: buffer-pool@7 {
++ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++ fsl,bpid = <7>;
++ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
++ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
++ };
++
++ bp8: buffer-pool@8 {
++ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++ fsl,bpid = <8>;
++ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
++ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++ };
++
++ bp9: buffer-pool@9 {
++ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++ fsl,bpid = <9>;
++ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
++ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++ };
++
++ fsl,dpaa {
++ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
++
++ ethernet@2 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
++ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
++ };
++
++ ethernet@3 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
++ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
++ };
++
++ ethernet@4 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
++ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
++ };
++
++ ethernet@5 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
++ fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
++ };
++
++ ethernet@8 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
++ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
++ };
++
++ ethernet@9 {
++ compatible = "fsl,dpa-ethernet-init";
++ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++ fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
++ fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
++ };
++
++ dpa-fman0-oh@2 {
++ compatible = "fsl,dpa-oh";
++ /* Define frame queues for the OH port*/
++ /* <OH Rx error, OH Rx default> */
++ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
++ fsl,fman-oh-port = <&fman0_oh2>;
++ };
++ };
++};
++/ {
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ usdpaa_mem: usdpaa_mem {
++ compatible = "fsl,usdpaa-mem";
++ alloc-ranges = <0 0 0x10000 0>;
++ size = <0 0x10000000>;
++ alignment = <0 0x10000000>;
++ };
++ };
++};
++
++&fman0 {
++ fman0_oh2: port@83000 {
++ cell-index = <1>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x83000 0x1000>;
++ };
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+@@ -1,47 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <mingkai.hu@nxp.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -139,6 +102,7 @@
+ num-cs = <2>;
+ bus-num = <0>;
+ status = "okay";
++ fsl,qspi-has-second-chip;
+
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+@@ -146,6 +110,8 @@
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
+ };
+
+ qflash1: s25fs512s@1 {
+@@ -154,6 +120,8 @@
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <1>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+@@ -1,47 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <mingkai.hu@nxp.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+@@ -122,7 +85,7 @@
+ CPU_PH20: cpu-ph20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PH20";
+- arm,psci-suspend-param = <0x00010000>;
++ arm,psci-suspend-param = <0x0>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <1000>;
+ min-residency-us = <3000>;
+@@ -214,7 +177,6 @@
+ clock-names = "qspi_en", "qspi";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+ big-endian;
+- fsl,qspi-has-second-chip;
+ status = "disabled";
+ };
+
+@@ -304,7 +266,7 @@
+
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1046a-dcfg", "syscon";
+- reg = <0x0 0x1ee0000 0x0 0x10000>;
++ reg = <0x0 0x1ee0000 0x0 0x1000>;
+ big-endian;
+ };
+
+@@ -407,7 +369,7 @@
+ };
+
+ i2c0: i2c@2180000 {
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+@@ -416,6 +378,7 @@
+ dmas = <&edma0 1 39>,
+ <&edma0 1 38>;
+ dma-names = "tx", "rx";
++ fsl-scl-gpio = <&gpio3 12 0>;
+ status = "disabled";
+ };
+
+@@ -440,12 +403,13 @@
+ };
+
+ i2c3: i2c@21b0000 {
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
++ fsl-scl-gpio = <&gpio3 12 0>;
+ status = "disabled";
+ };
+
+@@ -571,6 +535,15 @@
+ status = "disabled";
+ };
+
++ ftm0: ftm0@29d0000 {
++ compatible = "fsl,ls1046a-ftm-alarm";
++ reg = <0x0 0x29d0000 0x0 0x10000>,
++ <0x0 0x1ee2140 0x0 0x4>;
++ reg-names = "ftm", "pmctrl";
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ big-endian;
++ };
++
+ wdog0: watchdog@2ad0000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+@@ -602,6 +575,9 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ usb3-lpm-capable;
++ snps,dis-u1u2-when-u3-quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ usb1: usb@3000000 {
+@@ -611,6 +587,9 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ usb3-lpm-capable;
++ snps,dis-u1u2-when-u3-quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ usb2: usb@3100000 {
+@@ -620,6 +599,9 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ usb3-lpm-capable;
++ snps,dis-u1u2-when-u3-quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ sata: sata@3200000 {
+@@ -631,6 +613,27 @@
+ clocks = <&clockgen 4 1>;
+ };
+
++ qdma: qdma@8380000 {
++ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
++ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
++ <0x0 0x8390000 0x0 0x10000>, /* Status regs */
++ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
++ interrupts = <0 153 0x4>,
++ <0 39 0x4>,
++ <0 40 0x4>,
++ <0 41 0x4>,
++ <0 42 0x4>;
++ interrupt-names = "qdma-error", "qdma-queue0",
++ "qdma-queue1", "qdma-queue2", "qdma-queue3";
++ channels = <8>;
++ block-number = <1>;
++ block-offset = <0x10000>;
++ queues = <2>;
++ status-sizes = <64>;
++ queue-sizes = <64 64>;
++ big-endian;
++ };
++
+ msi1: msi-controller@1580000 {
+ compatible = "fsl,ls1046a-msi";
+ msi-controller;
+@@ -661,6 +664,92 @@
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ pcie@3400000 {
++ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
++ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
++ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++ interrupt-names = "pme", "aer";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ dma-coherent;
++ num-lanes = <4>;
++ num-ib-windows = <6>;
++ num-ob-windows = <6>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&msi1>, <&msi2>, <&msi3>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ pcie@3500000 {
++ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
++ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pme", "aer";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ dma-coherent;
++ num-lanes = <2>;
++ num-ib-windows = <6>;
++ num-ob-windows = <6>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&msi1>, <&msi2>, <&msi3>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ pcie@3600000 {
++ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
++ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pme", "aer";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ dma-coherent;
++ num-lanes = <2>;
++ num-ib-windows = <6>;
++ num-ob-windows = <6>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&msi1>, <&msi2>, <&msi3>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ serdes1: serdes@1ea0000 {
++ reg = <0x0 0x1ea0000 0 0x00002000>;
++ compatible = "fsl,serdes-10g";
++ };
++
+ };
+
+ reserved-memory {
+@@ -689,6 +778,13 @@
+ no-map;
+ };
+ };
++
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
+ };
+
+ #include "qoriq-qman-portals.dtsi"
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for NXP LS1088A QDS Board.
+ *
+@@ -5,43 +6,6 @@
+ *
+ * Harninder Rai <harninder.rai@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -134,6 +98,30 @@
+ };
+ };
+
++&qspi {
++ status = "okay";
++ fsl,qspi-has-second-chip;
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ };
++
++ qflash1: s25fs512s@1 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ reg = <1>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ };
++};
++
+ &duart0 {
+ status = "okay";
+ };
+@@ -149,3 +137,29 @@
+ &sata {
+ status = "okay";
+ };
++
++&pcs_mdio1 {
++ pcs_phy1: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x840 0x40>;/* lane B */
++ };
++};
++
++&pcs_mdio2 {
++ pcs_phy2: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x800 0x40>;/* lane A */
++ };
++};
++
++/* Update DPMAC connections to backplane PHYs, under SerDes 0x1D_0xXX.
++ * &dpmac1 {
++ * phy-handle = <&pcs_phy1>;
++ * };
++ */
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for NXP LS1088A RDB Board.
+ *
+@@ -5,43 +6,6 @@
+ *
+ * Harninder Rai <harninder.rai@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -110,6 +74,31 @@
+ };
+ };
+
++&qspi {
++ status = "okay";
++ fsl,qspi-has-second-chip;
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ };
++
++ qflash1: s25fs512s@1 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ reg = <1>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ };
++
++};
++
+ &duart0 {
+ status = "okay";
+ };
+@@ -118,6 +107,14 @@
+ status = "okay";
+ };
+
++&usb0 {
++ status = "okay";
++};
++
++&usb1 {
++ status = "okay";
++};
++
+ &esdhc {
+ status = "okay";
+ };
+@@ -125,3 +122,82 @@
+ &sata {
+ status = "okay";
+ };
++
++&emdio1 {
++ /* Freescale F104 PHY1 */
++ mdio1_phy1: emdio1_phy@1 {
++ reg = <0x1c>;
++ phy-connection-type = "qsgmii";
++ };
++ mdio1_phy2: emdio1_phy@2 {
++ reg = <0x1d>;
++ phy-connection-type = "qsgmii";
++ };
++ mdio1_phy3: emdio1_phy@3 {
++ reg = <0x1e>;
++ phy-connection-type = "qsgmii";
++ };
++ mdio1_phy4: emdio1_phy@4 {
++ reg = <0x1f>;
++ phy-connection-type = "qsgmii";
++ };
++ /* F104 PHY2 */
++ mdio1_phy5: emdio1_phy@5 {
++ reg = <0x0c>;
++ phy-connection-type = "qsgmii";
++ };
++ mdio1_phy6: emdio1_phy@6 {
++ reg = <0x0d>;
++ phy-connection-type = "qsgmii";
++ };
++ mdio1_phy7: emdio1_phy@7 {
++ reg = <0x0e>;
++ phy-connection-type = "qsgmii";
++ };
++ mdio1_phy8: emdio1_phy@8 {
++ reg = <0x0f>;
++ phy-connection-type = "qsgmii";
++ };
++};
++
++&emdio2 {
++ /* Aquantia AQR105 10G PHY */
++ mdio2_phy1: emdio2_phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 2 0x4>;
++ reg = <0x0>;
++ phy-connection-type = "xfi";
++ };
++};
++
++/* DPMAC connections to external PHYs
++ * based on LS1088A RM RevC - $24.1.2 SerDes Options
++ */
++/* DPMAC1 is 10G SFP+, fixed link */
++&dpmac2 {
++ phy-handle = <&mdio2_phy1>;
++};
++&dpmac3 {
++ phy-handle = <&mdio1_phy5>;
++};
++&dpmac4 {
++ phy-handle = <&mdio1_phy6>;
++};
++&dpmac5 {
++ phy-handle = <&mdio1_phy7>;
++};
++&dpmac6 {
++ phy-handle = <&mdio1_phy8>;
++};
++&dpmac7 {
++ phy-handle = <&mdio1_phy1>;
++};
++&dpmac8 {
++ phy-handle = <&mdio1_phy2>;
++};
++&dpmac9 {
++ phy-handle = <&mdio1_phy3>;
++};
++&dpmac10 {
++ phy-handle = <&mdio1_phy4>;
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for NXP Layerscape-1088A family SoC.
+ *
+@@ -5,43 +6,6 @@
+ *
+ * Harninder Rai <harninder.rai@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/thermal/thermal.h>
+@@ -130,7 +94,7 @@
+ CPU_PH20: cpu-ph20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PH20";
+- arm,psci-suspend-param = <0x00010000>;
++ arm,psci-suspend-param = <0x0>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <1000>;
+ min-residency-us = <3000>;
+@@ -147,6 +111,15 @@
+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */
+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */
+ interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ its: gic-its@6020000 {
++ compatible = "arm,gic-v3-its";
++ msi-controller;
++ reg = <0x0 0x6020000 0 0x20000>;
++ };
+ };
+
+ timer {
+@@ -169,11 +142,31 @@
+ clock-output-names = "sysclk";
+ };
+
++ dcfg: dcfg@1e00000 {
++ compatible = "fsl,ls1088a-dcfg", "syscon";
++ reg = <0x0 0x1e00000 0x0 0x10000>;
++ little-endian;
++ };
++
++ rstcr: syscon@1e60000 {
++ compatible = "fsl,ls1088a-rstcr", "syscon";
++ reg = <0x0 0x1e60000 0x0 0x4>;
++ };
++
++ reboot {
++ compatible = "syscon-reboot";
++ regmap = <&rstcr>;
++ offset = <0x0>;
++ mask = <0x02>;
++ };
++
++
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
++ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+
+ clockgen: clocking@1300000 {
+ compatible = "fsl,ls1088a-clockgen";
+@@ -283,6 +276,62 @@
+ status = "disabled";
+ };
+
++ cluster1_core0_watchdog: wdt@c000000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc000000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
++ cluster1_core1_watchdog: wdt@c010000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc010000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
++ cluster1_core2_watchdog: wdt@c020000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc020000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
++ cluster1_core3_watchdog: wdt@c030000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc030000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
++ cluster2_core0_watchdog: wdt@c100000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc100000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
++ cluster2_core1_watchdog: wdt@c110000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc110000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
++ cluster2_core2_watchdog: wdt@c120000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc120000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
++ cluster2_core3_watchdog: wdt@c130000 {
++ compatible = "arm,sp805-wdt", "arm,primecell";
++ reg = <0x0 0xc130000 0x0 0x1000>;
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "apb_pclk", "wdog_clk";
++ };
++
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+@@ -323,6 +372,72 @@
+ #interrupt-cells = <2>;
+ };
+
++ /* TODO: WRIOP (CCSR?) */
++ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
++ * E-MDIO1: 0x1_6000
++ */
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8B96000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian; /* force the driver in LE mode */
++
++ /* Not necessary on the QDS, but needed on the RDB */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
++ * E-MDIO2: 0x1_7000
++ */
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8B97000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian; /* force the driver in LE mode */
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio1: mdio@0x8c07000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c07000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio2: mdio@0x8c0b000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c0b000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio3: mdio@0x8c0f000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c0f000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio4: mdio@0x8c13000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c13000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
+ ifc: ifc@2240000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x2240000 0x0 0x20000>;
+@@ -333,13 +448,22 @@
+ status = "disabled";
+ };
+
++ ftm0: ftm0@2800000 {
++ compatible = "fsl,ls1088a-ftm-alarm";
++ reg = <0x0 0x2800000 0x0 0x10000>,
++ <0x0 0x1e34050 0x0 0x4>;
++ reg-names = "ftm", "pmctrl";
++ interrupts = <0 44 4>;
++ };
++
+ i2c0: i2c@2000000 {
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
++ fsl-scl-gpio = <&gpio3 30 0>;
+ status = "disabled";
+ };
+
+@@ -349,7 +473,7 @@
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+@@ -359,7 +483,7 @@
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+@@ -369,7 +493,7 @@
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+@@ -385,6 +509,26 @@
+ status = "disabled";
+ };
+
++ usb0: usb3@3100000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0x3100000 0x0 0x10000>;
++ interrupts = <0 80 0x4>; /* Level high type */
++ dr_mode = "host";
++ configure-gfladj;
++ snps,dis_rxdet_inp3_quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++ };
++
++ usb1: usb3@3110000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0x3110000 0x0 0x10000>;
++ interrupts = <0 81 0x4>; /* Level high type */
++ dr_mode = "host";
++ configure-gfladj;
++ snps,dis_rxdet_inp3_quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++ };
++
+ sata: sata@3200000 {
+ compatible = "fsl,ls1088a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+@@ -395,6 +539,17 @@
+ dma-coherent;
+ status = "disabled";
+ };
++ qspi: quadspi@20c0000 {
++ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x20c0000 0x0 0x10000>,
++ <0x0 0x20000000 0x0 0x10000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ interrupts = <0 25 0x4>; /* Level high type */
++ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++ clock-names = "qspi_en", "qspi";
++ };
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+@@ -434,6 +589,251 @@
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
++
++ pcie@3400000 {
++ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
++ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++ interrupt-names = "aer";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ dma-coherent;
++ num-lanes = <4>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ pcie@3500000 {
++ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
++ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++ interrupt-names = "aer";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ dma-coherent;
++ num-lanes = <4>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ pcie@3600000 {
++ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
++ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++ interrupt-names = "aer";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ dma-coherent;
++ num-lanes = <8>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ fsl_mc: fsl-mc@80c000000 {
++ compatible = "fsl,qoriq-mc";
++ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
++ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
++ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
++ dma-coherent;
++ #address-cells = <3>;
++ #size-cells = <1>;
++
++ /*
++ * Region type 0x0 - MC portals
++ * Region type 0x1 - QBMAN portals
++ */
++ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
++ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
++
++ dpmacs {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ dpmac1: dpmac@1 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <1>;
++ };
++
++ dpmac2: dpmac@2 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <2>;
++ };
++
++ dpmac3: dpmac@3 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <3>;
++ };
++
++ dpmac4: dpmac@4 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <4>;
++ };
++
++ dpmac5: dpmac@5 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <5>;
++ };
++
++ dpmac6: dpmac@6 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <6>;
++ };
++
++ dpmac7: dpmac@7 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <7>;
++ };
++
++ dpmac8: dpmac@8 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <8>;
++ };
++
++ dpmac9: dpmac@9 {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <9>;
++ };
++
++ dpmac10: dpmac@a {
++ compatible = "fsl,qoriq-mc-dpmac";
++ reg = <0xa>;
++ };
++ };
++ };
++
++ smmu: iommu@5000000 {
++ compatible = "arm,mmu-500";
++ reg = <0 0x5000000 0 0x800000>;
++ #global-interrupts = <12>;
++ #iommu-cells = <1>;
++ stream-match-mask = <0x7C00>;
++ interrupts = <0 13 4>, /* global secure fault */
++ <0 14 4>, /* combined secure interrupt */
++ <0 15 4>, /* global non-secure fault */
++ <0 16 4>, /* combined non-secure interrupt */
++ /* performance counter interrupts 0-7 */
++ <0 211 4>,
++ <0 212 4>,
++ <0 213 4>,
++ <0 214 4>,
++ <0 215 4>,
++ <0 216 4>,
++ <0 217 4>,
++ <0 218 4>,
++ /* per context interrupt, 64 interrupts */
++ <0 146 4>,
++ <0 147 4>,
++ <0 148 4>,
++ <0 149 4>,
++ <0 150 4>,
++ <0 151 4>,
++ <0 152 4>,
++ <0 153 4>,
++ <0 154 4>,
++ <0 155 4>,
++ <0 156 4>,
++ <0 157 4>,
++ <0 158 4>,
++ <0 159 4>,
++ <0 160 4>,
++ <0 161 4>,
++ <0 162 4>,
++ <0 163 4>,
++ <0 164 4>,
++ <0 165 4>,
++ <0 166 4>,
++ <0 167 4>,
++ <0 168 4>,
++ <0 169 4>,
++ <0 170 4>,
++ <0 171 4>,
++ <0 172 4>,
++ <0 173 4>,
++ <0 174 4>,
++ <0 175 4>,
++ <0 176 4>,
++ <0 177 4>,
++ <0 178 4>,
++ <0 179 4>,
++ <0 180 4>,
++ <0 181 4>,
++ <0 182 4>,
++ <0 183 4>,
++ <0 184 4>,
++ <0 185 4>,
++ <0 186 4>,
++ <0 187 4>,
++ <0 188 4>,
++ <0 189 4>,
++ <0 190 4>,
++ <0 191 4>,
++ <0 192 4>,
++ <0 193 4>,
++ <0 194 4>,
++ <0 195 4>,
++ <0 196 4>,
++ <0 197 4>,
++ <0 198 4>,
++ <0 199 4>,
++ <0 200 4>,
++ <0 201 4>,
++ <0 202 4>,
++ <0 203 4>,
++ <0 204 4>,
++ <0 205 4>,
++ <0 206 4>,
++ <0 207 4>,
++ <0 208 4>,
++ <0 209 4>;
++ };
++
++ serdes1: serdes@1ea0000 {
++ reg = <0x0 0x1ea0000 0 0x00002000>;
++ compatible = "fsl,serdes-10g";
++ };
+ };
+
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS2080a QDS Board.
+ *
+@@ -7,43 +8,6 @@
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -59,3 +23,65 @@
+ stdout-path = "serial0:115200n8";
+ };
+ };
++
++&ifc {
++ boardctrl: board-control@3,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
++ reg = <3 0 0x300>; /* TODO check address */
++ ranges = <0 3 0 0x300>;
++
++ mdio_mux_emi1 {
++ compatible = "mdio-mux-mmioreg", "mdio-mux";
++ mdio-parent-bus = <&emdio1>;
++ reg = <0x54 1>; /* BRDCFG4 */
++ mux-mask = <0xe0>; /* EMI1_MDIO */
++
++ #address-cells=<1>;
++ #size-cells = <0>;
++
++ /* Child MDIO buses, one for each riser card:
++ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
++ * VSC8234 PHYs on the riser cards.
++ */
++
++ mdio_mux3: mdio@60 {
++ reg = <0x60>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ mdio0_phy12: mdio_phy0@1c {
++ reg = <0x1c>;
++ phy-connection-type = "sgmii";
++ };
++ mdio0_phy13: mdio_phy1@1d {
++ reg = <0x1d>;
++ phy-connection-type = "sgmii";
++ };
++ mdio0_phy14: mdio_phy2@1e {
++ reg = <0x1e>;
++ phy-connection-type = "sgmii";
++ };
++ mdio0_phy15: mdio_phy3@1f {
++ reg = <0x1f>;
++ phy-connection-type = "sgmii";
++ };
++ };
++ };
++ };
++};
++
++/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
++&dpmac9 {
++ phy-handle = <&mdio0_phy12>;
++};
++&dpmac10 {
++ phy-handle = <&mdio0_phy13>;
++};
++&dpmac11 {
++ phy-handle = <&mdio0_phy14>;
++};
++&dpmac12 {
++ phy-handle = <&mdio0_phy15>;
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS2080a RDB Board.
+ *
+@@ -7,43 +8,6 @@
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -59,3 +23,83 @@
+ stdout-path = "serial1:115200n8";
+ };
+ };
++
++&emdio1 {
++ status = "disabled";
++ /* CS4340 PHYs */
++ mdio1_phy1: emdio1_phy@1 {
++ reg = <0x10>;
++ phy-connection-type = "xfi";
++ };
++ mdio1_phy2: emdio1_phy@2 {
++ reg = <0x11>;
++ phy-connection-type = "xfi";
++ };
++ mdio1_phy3: emdio1_phy@3 {
++ reg = <0x12>;
++ phy-connection-type = "xfi";
++ };
++ mdio1_phy4: emdio1_phy@4 {
++ reg = <0x13>;
++ phy-connection-type = "xfi";
++ };
++};
++
++&emdio2 {
++ /* AQR405 PHYs */
++ mdio2_phy1: emdio2_phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 1 0x4>; /* Level high type */
++ reg = <0x0>;
++ phy-connection-type = "xfi";
++ };
++ mdio2_phy2: emdio2_phy@2 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 2 0x4>; /* Level high type */
++ reg = <0x1>;
++ phy-connection-type = "xfi";
++ };
++ mdio2_phy3: emdio2_phy@3 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 4 0x4>; /* Level high type */
++ reg = <0x2>;
++ phy-connection-type = "xfi";
++ };
++ mdio2_phy4: emdio2_phy@4 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 5 0x4>; /* Level high type */
++ reg = <0x3>;
++ phy-connection-type = "xfi";
++ };
++};
++
++/* Update DPMAC connections to external PHYs, under the assumption of
++ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
++ */
++/* Leave Cortina nodes commented out until driver is integrated
++ *&dpmac1 {
++ * phy-handle = <&mdio1_phy1>;
++ *};
++ *&dpmac2 {
++ * phy-handle = <&mdio1_phy2>;
++ *};
++ *&dpmac3 {
++ * phy-handle = <&mdio1_phy3>;
++ *};
++ *&dpmac4 {
++ * phy-handle = <&mdio1_phy4>;
++ *};
++ */
++
++&dpmac5 {
++ phy-handle = <&mdio2_phy1>;
++};
++&dpmac6 {
++ phy-handle = <&mdio2_phy2>;
++};
++&dpmac7 {
++ phy-handle = <&mdio2_phy3>;
++};
++&dpmac8 {
++ phy-handle = <&mdio2_phy4>;
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS2080a software Simulator model
+ *
+@@ -5,43 +6,6 @@
+ *
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPL or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-2080A family SoC.
+ *
+@@ -6,43 +7,6 @@
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ #include "fsl-ls208xa.dtsi"
+@@ -150,6 +114,10 @@
+ };
+ };
+
++&timer {
++ fsl,erratum-a008585;
++};
++
+ &pcie1 {
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
+@@ -0,0 +1,163 @@
++/*
++ * Device Tree file for NXP LS2081A RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Priyanka Jain <priyanka.jain@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "fsl-ls2088a.dtsi"
++
++/ {
++ model = "NXP Layerscape 2081A RDB Board";
++ compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
++
++ aliases {
++ serial0 = &serial0;
++ serial1 = &serial1;
++ };
++
++ chosen {
++ stdout-path = "serial1:115200n8";
++ };
++};
++
++&esdhc {
++ status = "okay";
++};
++
++&ifc {
++ status = "disabled";
++};
++
++&i2c0 {
++ status = "okay";
++ pca9547@75 {
++ compatible = "nxp,pca9547";
++ reg = <0x75>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x01>;
++ rtc@51 {
++ compatible = "nxp,pcf2129";
++ reg = <0x51>;
++ };
++ };
++
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x02>;
++
++ ina220@40 {
++ compatible = "ti,ina220";
++ reg = <0x40>;
++ shunt-resistor = <500>;
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x3>;
++
++ adt7481@4c {
++ compatible = "adi,adt7461";
++ reg = <0x4c>;
++ };
++ };
++ };
++};
++
++&dspi {
++ status = "okay";
++ dflash0: n25q512a {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p80";
++ spi-max-frequency = <3000000>;
++ reg = <0>;
++ };
++};
++
++&qspi {
++ status = "okay";
++ fsl,qspi-has-second-chip;
++ flash0: s25fs512s@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spansion,m25p80";
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++ flash1: s25fs512s@1 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
++ compatible = "spansion,m25p80";
++ spi-max-frequency = <20000000>;
++ reg = <1>;
++ };
++};
++
++&sata0 {
++ status = "okay";
++};
++
++&sata1 {
++ status = "okay";
++};
++
++&usb0 {
++ status = "okay";
++};
++
++&usb1 {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS2088A QDS Board.
+ *
+@@ -6,43 +7,6 @@
+ *
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -58,3 +22,123 @@
+ stdout-path = "serial0:115200n8";
+ };
+ };
++
++&ifc {
++ boardctrl: board-control@3,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
++ reg = <3 0 0x300>; /* TODO check address */
++ ranges = <0 3 0 0x300>;
++
++ mdio_mux_emi1 {
++ compatible = "mdio-mux-mmioreg", "mdio-mux";
++ mdio-parent-bus = <&emdio1>;
++ reg = <0x54 1>; /* BRDCFG4 */
++ mux-mask = <0xe0>; /* EMI1_MDIO */
++
++ #address-cells=<1>;
++ #size-cells = <0>;
++
++ /* Child MDIO buses, one for each riser card:
++ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
++ * VSC8234 PHYs on the riser cards.
++ */
++
++ mdio_mux3: mdio@60 {
++ reg = <0x60>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ mdio0_phy12: mdio_phy0@1c {
++ reg = <0x1c>;
++ phy-connection-type = "sgmii";
++ };
++ mdio0_phy13: mdio_phy1@1d {
++ reg = <0x1d>;
++ phy-connection-type = "sgmii";
++ };
++ mdio0_phy14: mdio_phy2@1e {
++ reg = <0x1e>;
++ phy-connection-type = "sgmii";
++ };
++ mdio0_phy15: mdio_phy3@1f {
++ reg = <0x1f>;
++ phy-connection-type = "sgmii";
++ };
++ };
++ };
++ };
++};
++
++&pcs_mdio1 {
++ pcs_phy1: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x9C0 0x40>;/* lane H */
++ };
++};
++
++&pcs_mdio2 {
++ pcs_phy2: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x980 0x40>;/* lane G */
++ };
++};
++
++&pcs_mdio3 {
++ pcs_phy3: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x940 0x40>;/* lane F */
++ };
++};
++
++&pcs_mdio4 {
++ pcs_phy4: ethernet-phy@0 {
++ backplane-mode = "10gbase-kr";
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x0>;
++ fsl,lane-handle = <&serdes1>;
++ fsl,lane-reg = <0x900 0x40>;/* lane E */
++ };
++};
++
++/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
++ * &dpmac1 {
++ * phy-handle = <&pcs_phy1>;
++ * };
++ *
++ * &dpmac2 {
++ * phy-handle = <&pcs_phy2>;
++ * };
++ *
++ * &dpmac3 {
++ * phy-handle = <&pcs_phy3>;
++ * };
++ *
++ * &dpmac4 {
++ * phy-handle = <&pcs_phy4>;
++ * };
++ */
++
++/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
++&dpmac9 {
++ phy-handle = <&mdio0_phy12>;
++};
++&dpmac10 {
++ phy-handle = <&mdio0_phy13>;
++};
++&dpmac11 {
++ phy-handle = <&mdio0_phy14>;
++};
++&dpmac12 {
++ phy-handle = <&mdio0_phy15>;
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS2088A RDB Board.
+ *
+@@ -6,43 +7,6 @@
+ *
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ /dts-v1/;
+@@ -58,3 +22,83 @@
+ stdout-path = "serial1:115200n8";
+ };
+ };
++
++&emdio1 {
++ status = "disabled";
++ /* CS4340 PHYs */
++ mdio1_phy1: emdio1_phy@1 {
++ reg = <0x10>;
++ phy-connection-type = "xfi";
++ };
++ mdio1_phy2: emdio1_phy@2 {
++ reg = <0x11>;
++ phy-connection-type = "xfi";
++ };
++ mdio1_phy3: emdio1_phy@3 {
++ reg = <0x12>;
++ phy-connection-type = "xfi";
++ };
++ mdio1_phy4: emdio1_phy@4 {
++ reg = <0x13>;
++ phy-connection-type = "xfi";
++ };
++};
++
++&emdio2 {
++ /* AQR405 PHYs */
++ mdio2_phy1: emdio2_phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 1 0x4>; /* Level high type */
++ reg = <0x0>;
++ phy-connection-type = "xfi";
++ };
++ mdio2_phy2: emdio2_phy@2 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 2 0x4>; /* Level high type */
++ reg = <0x1>;
++ phy-connection-type = "xfi";
++ };
++ mdio2_phy3: emdio2_phy@3 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 4 0x4>; /* Level high type */
++ reg = <0x2>;
++ phy-connection-type = "xfi";
++ };
++ mdio2_phy4: emdio2_phy@4 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ interrupts = <0 5 0x4>; /* Level high type */
++ reg = <0x3>;
++ phy-connection-type = "xfi";
++ };
++};
++
++/* Update DPMAC connections to external PHYs, under the assumption of
++ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
++ */
++/* Leave Cortina PHYs commented out until proper driver is integrated
++ *&dpmac1 {
++ * phy-handle = <&mdio1_phy1>;
++ *};
++ *&dpmac2 {
++ * phy-handle = <&mdio1_phy2>;
++ *};
++ *&dpmac3 {
++ * phy-handle = <&mdio1_phy3>;
++ *};
++ *&dpmac4 {
++ * phy-handle = <&mdio1_phy4>;
++ *};
++ */
++
++&dpmac5 {
++ phy-handle = <&mdio2_phy1>;
++};
++&dpmac6 {
++ phy-handle = <&mdio2_phy2>;
++};
++&dpmac7 {
++ phy-handle = <&mdio2_phy3>;
++};
++&dpmac8 {
++ phy-handle = <&mdio2_phy4>;
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-2088A family SoC.
+ *
+@@ -6,43 +7,6 @@
+ *
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ #include "fsl-ls208xa.dtsi"
+@@ -143,7 +107,7 @@
+ CPU_PW20: cpu-pw20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PW20";
+- arm,psci-suspend-param = <0x00010000>;
++ arm,psci-suspend-param = <0x0>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6000>;
+@@ -151,6 +115,7 @@
+ };
+
+ &pcie1 {
++ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+
+@@ -159,6 +124,7 @@
+ };
+
+ &pcie2 {
++ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+
+@@ -167,6 +133,7 @@
+ };
+
+ &pcie3 {
++ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+
+@@ -175,6 +142,7 @@
+ };
+
+ &pcie4 {
++ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
+ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS2080A QDS Board.
+ *
+@@ -6,43 +7,6 @@
+ *
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ &esdhc {
+@@ -165,16 +129,21 @@
+
+ &qspi {
+ status = "okay";
++ fsl,qspi-has-second-chip;
+ flash0: s25fl256s1@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+ flash2: s25fl256s1@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <4>;
+ compatible = "st,m25p80";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree file for Freescale LS2080A RDB Board.
+ *
+@@ -6,43 +7,6 @@
+ *
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ &esdhc {
+@@ -85,6 +49,7 @@
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
++ i2c-mux-never-disable;
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+@@ -95,6 +60,17 @@
+ };
+ };
+
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x02>;
++ ina220@40 {
++ compatible = "ti,ina220";
++ reg = <0x40>;
++ shunt-resistor = <500>;
++ };
++ };
++
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+@@ -132,7 +108,15 @@
+ };
+
+ &qspi {
+- status = "disabled";
++ status = "okay";
++ flash0: s25fs512s@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spansion,m25p80";
++ m25p,fast-read;
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
+ };
+
+ &sata0 {
+--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+@@ -1,3 +1,4 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+ * Device Tree Include file for Freescale Layerscape-2080A family SoC.
+ *
+@@ -6,43 +7,6 @@
+ *
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+ *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- * a) This library is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of the
+- * License, or (at your option) any later version.
+- *
+- * This library is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- * b) Permission is hereby granted, free of charge, to any person
+- * obtaining a copy of this software and associated documentation
+- * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use,
+- * copy, modify, merge, publish, distribute, sublicense, and/or
+- * sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following
+- * conditions:
+- *
+- * The above copyright notice and this permission notice shall be
+- * included in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+ #include <dt-bindings/thermal/thermal.h>
+@@ -111,13 +75,12 @@
+ mask = <0x2>;
+ };
+
+- timer {
++ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
+ <1 14 4>, /* Physical Non-Secure PPI, active-low */
+ <1 11 4>, /* Virtual PPI, active-low */
+ <1 10 4>; /* Hypervisor PPI, active-low */
+- fsl,erratum-a008585;
+ };
+
+ pmu {
+@@ -135,6 +98,7 @@
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
++ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+
+ clockgen: clocking@1300000 {
+ compatible = "fsl,ls2080a-clockgen";
+@@ -357,6 +321,8 @@
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
++ dma-coherent;
+ #address-cells = <3>;
+ #size-cells = <1>;
+
+@@ -460,6 +426,8 @@
+ compatible = "arm,mmu-500";
+ reg = <0 0x5000000 0 0x800000>;
+ #global-interrupts = <12>;
++ #iommu-cells = <1>;
++ stream-match-mask = <0x7C00>;
+ interrupts = <0 13 4>, /* global secure fault */
+ <0 14 4>, /* combined secure interrupt */
+ <0 15 4>, /* global non-secure fault */
+@@ -502,7 +470,6 @@
+ <0 204 4>, <0 205 4>,
+ <0 206 4>, <0 207 4>,
+ <0 208 4>, <0 209 4>;
+- mmu-masters = <&fsl_mc 0x300 0>;
+ };
+
+ dspi: dspi@2100000 {
+@@ -574,15 +541,126 @@
+ #interrupt-cells = <2>;
+ };
+
++ /* TODO: WRIOP (CCSR?) */
++ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
++ * E-MDIO1: 0x1_6000
++ */
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8B96000 0x0 0x1000>;
++ device_type = "mdio"; /* TODO: is this necessary? */
++ little-endian; /* force the driver in LE mode */
++
++ /* Not necessary on the QDS, but needed on the RDB */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
++ * E-MDIO2: 0x1_7000
++ */
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8B97000 0x0 0x1000>;
++ device_type = "mdio"; /* TODO: is this necessary? */
++ little-endian; /* force the driver in LE mode */
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio1: mdio@0x8c07000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c07000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio2: mdio@0x8c0b000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c0b000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio3: mdio@0x8c0f000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c0f000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio4: mdio@0x8c13000 {
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c13000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio5: mdio@0x8c17000 {
++ status = "disabled";
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c17000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio6: mdio@0x8c1b000 {
++ status = "disabled";
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c1b000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio7: mdio@0x8c1f000 {
++ status = "disabled";
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c1f000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ pcs_mdio8: mdio@0x8c23000 {
++ status = "disabled";
++ compatible = "fsl,fman-memac-mdio";
++ reg = <0x0 0x8c23000 0x0 0x1000>;
++ device_type = "mdio";
++ little-endian;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
+ i2c0: i2c@2000000 {
+ status = "disabled";
+- compatible = "fsl,vf610-i2c";
++ compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ clock-names = "i2c";
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
++ fsl-scl-gpio = <&gpio3 10 0>;
+ };
+
+ i2c1: i2c@2010000 {
+@@ -593,7 +671,7 @@
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ clock-names = "i2c";
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
+ };
+
+ i2c2: i2c@2020000 {
+@@ -604,7 +682,7 @@
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ clock-names = "i2c";
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
+ };
+
+ i2c3: i2c@2030000 {
+@@ -615,7 +693,7 @@
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ clock-names = "i2c";
+- clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
+ };
+
+ ifc: ifc@2240000 {
+@@ -648,8 +726,8 @@
+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+ "snps,dw-pcie";
+ reg-names = "regs", "config";
+- interrupts = <0 108 0x4>; /* Level high type */
+- interrupt-names = "intr";
++ interrupts = <0 108 0x4>; /* aer interrupt */
++ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+@@ -657,6 +735,7 @@
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
+@@ -669,8 +748,8 @@
+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+ "snps,dw-pcie";
+ reg-names = "regs", "config";
+- interrupts = <0 113 0x4>; /* Level high type */
+- interrupt-names = "intr";
++ interrupts = <0 113 0x4>; /* aer interrupt */
++ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+@@ -678,6 +757,7 @@
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
+@@ -690,8 +770,8 @@
+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+ "snps,dw-pcie";
+ reg-names = "regs", "config";
+- interrupts = <0 118 0x4>; /* Level high type */
+- interrupt-names = "intr";
++ interrupts = <0 118 0x4>; /* aer interrupt */
++ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+@@ -699,6 +779,7 @@
+ num-lanes = <8>;
+ bus-range = <0x0 0xff>;
+ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
+@@ -711,8 +792,8 @@
+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+ "snps,dw-pcie";
+ reg-names = "regs", "config";
+- interrupts = <0 123 0x4>; /* Level high type */
+- interrupt-names = "intr";
++ interrupts = <0 123 0x4>; /* aer interrupt */
++ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+@@ -720,6 +801,7 @@
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ msi-parent = <&its>;
++ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
+@@ -754,6 +836,7 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ };
+
+ usb1: usb3@3110000 {
+@@ -764,6 +847,12 @@
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
++ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++ };
++
++ serdes1: serdes@1ea0000 {
++ reg = <0x0 0x1ea0000 0 0x00002000>;
++ compatible = "fsl,serdes-10g";
+ };
+
+ ccn@4000000 {
+@@ -771,6 +860,14 @@
+ reg = <0x0 0x04000000 0x0 0x01000000>;
+ interrupts = <0 12 4>;
+ };
++
++ ftm0: ftm0@2800000 {
++ compatible = "fsl,ls208xa-ftm-alarm";
++ reg = <0x0 0x2800000 0x0 0x10000>,
++ <0x0 0x1e34050 0x0 0x4>;
++ reg-names = "ftm", "pmctrl";
++ interrupts = <0 44 4>;
++ };
+ };
+
+ ddr1: memory-controller@1080000 {
+@@ -786,4 +883,11 @@
+ interrupts = <0 18 0x4>;
+ little-endian;
+ };
++
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
+ };
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
+@@ -0,0 +1,55 @@
++/*
++ * QorIQ BMan SDK Portals device tree nodes
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++&bportals {
++ bman-portal@0 {
++ cell-index = <0>;
++ };
++
++ bman-portal@10000 {
++ cell-index = <1>;
++ };
++
++ bman-portal@20000 {
++ cell-index = <2>;
++ };
++
++ bman-portal@30000 {
++ cell-index = <3>;
++ };
++
++ bman-portal@40000 {
++ cell-index = <4>;
++ };
++
++ bman-portal@50000 {
++ cell-index = <5>;
++ };
++
++ bman-portal@60000 {
++ cell-index = <6>;
++ };
++
++ bman-portal@70000 {
++ cell-index = <7>;
++ };
++
++ bman-portal@80000 {
++ cell-index = <8>;
++ };
++
++ bman-portal@90000 {
++ cell-index = <9>;
++ };
++
++ bman-bpids@0 {
++ compatible = "fsl,bpid-range";
++ fsl,bpid-range = <32 32>;
++ };
++};
+--- a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
+@@ -1,9 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ BMan Portals device tree
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ &bportals {
+@@ -68,4 +68,10 @@
+ reg = <0x80000 0x4000>, <0x4080000 0x4000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ };
++
++ bman-portal@90000 {
++ compatible = "fsl,bman-portal";
++ reg = <0x90000 0x4000>, <0x4090000 0x4000>;
++ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++ };
+ };
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
+@@ -0,0 +1,97 @@
++/*
++ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
++ *
++ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Freescale Semiconductor nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++fsldpaa: fsl,dpaa {
++ compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
++ ethernet@0 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet0>;
++ dma-coherent;
++ };
++ ethernet@1 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet1>;
++ dma-coherent;
++ };
++ ethernet@2 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet2>;
++ dma-coherent;
++ };
++ ethernet@3 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet3>;
++ dma-coherent;
++ };
++ ethernet@4 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet4>;
++ dma-coherent;
++ };
++ ethernet@5 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet5>;
++ dma-coherent;
++ };
++ ethernet@8 {
++ compatible = "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet6>;
++ dma-coherent;
++ };
++ ethernet@6 {
++ compatible = "fsl,im-ethernet";
++ fsl,fman-mac = <&enet2>;
++ dma-coherent;
++ fpmevt-sel = <0>;
++ };
++ ethernet@7 {
++ compatible = "fsl,im-ethernet";
++ fsl,fman-mac = <&enet3>;
++ dma-coherent;
++ fpmevt-sel = <1>;
++ };
++ ethernet@10 {
++ compatible = "fsl,im-ethernet";
++ fsl,fman-mac = <&enet4>;
++ dma-coherent;
++ fpmevt-sel = <2>;
++ };
++ ethernet@11 {
++ compatible = "fsl,im-ethernet";
++ fsl,fman-mac = <&enet5>;
++ dma-coherent;
++ fpmevt-sel = <3>;
++ };
++};
++
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
+@@ -1,27 +1,28 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 10g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x10: port@90000 {
+ cell-index = <0x10>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman0_tx_0x30: port@b0000 {
+ cell-index = <0x30>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ fsl,fman-10g-port;
++ fsl,qman-channel-id = <0x800>;
+ };
+
+- ethernet@f0000 {
++ mac9: ethernet@f0000 {
+ cell-index = <0x8>;
+ compatible = "fsl,fman-memac";
+ reg = <0xf0000 0x1000>;
+@@ -29,7 +30,7 @@ fman@1a00000 {
+ pcsphy-handle = <&pcsphy6>;
+ };
+
+- mdio@f1000 {
++ mdio9: mdio@f1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
+@@ -1,27 +1,28 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 10g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x11: port@91000 {
+ cell-index = <0x11>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
+ reg = <0x91000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman0_tx_0x31: port@b1000 {
+ cell-index = <0x31>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
+ reg = <0xb1000 0x1000>;
+ fsl,fman-10g-port;
++ fsl,qman-channel-id = <0x801>;
+ };
+
+- ethernet@f2000 {
++ mac10: ethernet@f2000 {
+ cell-index = <0x9>;
+ compatible = "fsl,fman-memac";
+ reg = <0xf2000 0x1000>;
+@@ -29,7 +30,7 @@ fman@1a00000 {
+ pcsphy-handle = <&pcsphy7>;
+ };
+
+- mdio@f3000 {
++ mdio10: mdio@f3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
+@@ -1,22 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 1g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x08: port@88000 {
+ cell-index = <0x8>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+
+ fman0_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
++ fsl,qman-channel-id = <0x802>;
+ };
+
+ ethernet@e0000 {
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
+@@ -1,22 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 1g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x09: port@89000 {
+ cell-index = <0x9>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+
+ fman0_tx_0x29: port@a9000 {
+ cell-index = <0x29>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
++ fsl,qman-channel-id = <0x803>;
+ };
+
+ ethernet@e2000 {
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
+@@ -1,22 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 1g port #2 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x0a: port@8a000 {
+ cell-index = <0xa>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+
+ fman0_tx_0x2a: port@aa000 {
+ cell-index = <0x2a>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
++ fsl,qman-channel-id = <0x804>;
+ };
+
+ ethernet@e4000 {
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
+@@ -1,22 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 1g port #3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x0b: port@8b000 {
+ cell-index = <0xb>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+
+ fman0_tx_0x2b: port@ab000 {
+ cell-index = <0x2b>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
++ fsl,qman-channel-id = <0x805>;
+ };
+
+ ethernet@e6000 {
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
+@@ -1,22 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 1g port #4 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x0c: port@8c000 {
+ cell-index = <0xc>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+
+ fman0_tx_0x2c: port@ac000 {
+ cell-index = <0x2c>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
++ fsl,qman-channel-id = <0x806>;
+ };
+
+ ethernet@e8000 {
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
+@@ -1,22 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 1g port #5 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman@1a00000 {
+ fman0_rx_0x0d: port@8d000 {
+ cell-index = <0xd>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8d000 0x1000>;
+ };
+
+ fman0_tx_0x2d: port@ad000 {
+ cell-index = <0x2d>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
+ reg = <0xad000 0x1000>;
++ fsl,qman-channel-id = <0x807>;
+ };
+
+ ethernet@ea000 {
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
+@@ -0,0 +1,47 @@
++/*
++ * QorIQ FMan v3 OH ports device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++fman@1a00000 {
++
++ fman0_oh1: port@82000 {
++ cell-index = <0>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x82000 0x1000>;
++ };
++
++ fman0_oh2: port@83000 {
++ cell-index = <1>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x83000 0x1000>;
++ };
++
++ fman0_oh3: port@84000 {
++ cell-index = <2>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x84000 0x1000>;
++ };
++
++ fman0_oh4: port@85000 {
++ cell-index = <3>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x85000 0x1000>;
++ };
++
++ fman0_oh5: port@86000 {
++ cell-index = <4>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x86000 0x1000>;
++ };
++
++ fman0_oh6: port@87000 {
++ cell-index = <5>;
++ compatible = "fsl,fman-port-oh";
++ reg = <0x87000 0x1000>;
++ };
++
++};
+--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
+@@ -1,9 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ FMan v3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ fman0: fman@1a00000 {
+@@ -19,45 +19,95 @@ fman0: fman@1a00000 {
+ clock-names = "fmanclk";
+ fsl,qman-channel-range = <0x800 0x10>;
+
++ cc {
++ compatible = "fsl,fman-cc";
++ };
++
+ muram@0 {
+ compatible = "fsl,fman-muram";
+ reg = <0x0 0x60000>;
+ };
+
++ bmi@80000 {
++ compatible = "fsl,fman-bmi";
++ reg = <0x80000 0x400>;
++ };
++
++ qmi@80400 {
++ compatible = "fsl,fman-qmi";
++ reg = <0x80400 0x400>;
++ };
++
+ fman0_oh_0x2: port@82000 {
+ cell-index = <0x2>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x82000 0x1000>;
++ fsl,qman-channel-id = <0x809>;
+ };
+
+ fman0_oh_0x3: port@83000 {
+ cell-index = <0x3>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x83000 0x1000>;
++ fsl,qman-channel-id = <0x80a>;
+ };
+
+ fman0_oh_0x4: port@84000 {
+ cell-index = <0x4>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x84000 0x1000>;
++ fsl,qman-channel-id = <0x80b>;
+ };
+
+ fman0_oh_0x5: port@85000 {
+ cell-index = <0x5>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x85000 0x1000>;
++ fsl,qman-channel-id = <0x80c>;
+ };
+
+ fman0_oh_0x6: port@86000 {
+ cell-index = <0x6>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x86000 0x1000>;
++ fsl,qman-channel-id = <0x80d>;
+ };
+
+ fman0_oh_0x7: port@87000 {
+ cell-index = <0x7>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x87000 0x1000>;
++ fsl,qman-channel-id = <0x80e>;
++ };
++
++ policer@c0000 {
++ compatible = "fsl,fman-policer";
++ reg = <0xc0000 0x1000>;
++ };
++
++ keygen@c1000 {
++ compatible = "fsl,fman-keygen";
++ reg = <0xc1000 0x1000>;
++ };
++
++ dma@c2000 {
++ compatible = "fsl,fman-dma";
++ reg = <0xc2000 0x1000>;
++ };
++
++ fpm@c3000 {
++ compatible = "fsl,fman-fpm";
++ reg = <0xc3000 0x1000>;
++ };
++
++ parser@c7000 {
++ compatible = "fsl,fman-parser";
++ reg = <0xc7000 0x1000>;
++ };
++
++ vsps@dc000 {
++ compatible = "fsl,fman-vsps";
++ reg = <0xdc000 0x1000>;
+ };
+
+ mdio0: mdio@fc000 {
+@@ -75,7 +125,7 @@ fman0: fman@1a00000 {
+ };
+
+ ptp_timer0: ptp-timer@fe000 {
+- compatible = "fsl,fman-ptp-timer";
++ compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
+ reg = <0xfe000 0x1000>;
+ };
+ };
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
+@@ -0,0 +1,38 @@
++/*
++ * QorIQ QMan SDK Portals device tree nodes
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++&qportals {
++ qman-fqids@0 {
++ compatible = "fsl,fqid-range";
++ fsl,fqid-range = <256 256>;
++ };
++
++ qman-fqids@1 {
++ compatible = "fsl,fqid-range";
++ fsl,fqid-range = <32768 32768>;
++ };
++
++ qman-pools@0 {
++ compatible = "fsl,pool-channel-range";
++ fsl,pool-channel-range = <0x401 0xf>;
++ };
++
++ qman-cgrids@0 {
++ compatible = "fsl,cgrid-range";
++ fsl,cgrid-range = <0 256>;
++ };
++
++ qman-ceetm@0 {
++ compatible = "fsl,qman-ceetm";
++ fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
++ fsl,ceetm-sp-range = <0 16>;
++ fsl,ceetm-lni-range = <0 8>;
++ fsl,ceetm-channel-range = <0 32>;
++ };
++};
+--- a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
++++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
+@@ -1,9 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ /*
+ * QorIQ QMan Portals device tree
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+ &qportals {
+@@ -77,4 +77,11 @@
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <8>;
+ };
++
++ qportal9: qman-portal@90000 {
++ compatible = "fsl,qman-portal";
++ reg = <0x90000 0x4000>, <0x4090000 0x4000>;
++ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++ cell-index = <9>;
++ };
+ };
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x10: port@90000 {
+ cell-index = <0x10>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ };
+
+ fman0_tx_0x30: port@b0000 {
+ cell-index = <0x30>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x08: port@88000 {
+ cell-index = <0x8>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+
+ fman0_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x09: port@89000 {
+ cell-index = <0x9>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+
+ fman0_tx_0x29: port@a9000 {
+ cell-index = <0x29>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x0a: port@8a000 {
+ cell-index = <0xa>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+
+ fman0_tx_0x2a: port@aa000 {
+ cell-index = <0x2a>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x0b: port@8b000 {
+ cell-index = <0xb>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+
+ fman0_tx_0x2b: port@ab000 {
+ cell-index = <0x2b>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x0c: port@8c000 {
+ cell-index = <0xc>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+
+ fman0_tx_0x2c: port@ac000 {
+ cell-index = <0x2c>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x10: port@90000 {
+ cell-index = <0x10>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ };
+
+ fman1_tx_0x30: port@b0000 {
+ cell-index = <0x30>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x08: port@88000 {
+ cell-index = <0x8>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+
+ fman1_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x09: port@89000 {
+ cell-index = <0x9>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+
+ fman1_tx_0x29: port@a9000 {
+ cell-index = <0x29>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x0a: port@8a000 {
+ cell-index = <0xa>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+
+ fman1_tx_0x2a: port@aa000 {
+ cell-index = <0x2a>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x0b: port@8b000 {
+ cell-index = <0xb>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+
+ fman1_tx_0x2b: port@ab000 {
+ cell-index = <0x2b>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x0c: port@8c000 {
+ cell-index = <0xc>;
+- compatible = "fsl,fman-v2-port-rx";
++ compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+
+ fman1_tx_0x2c: port@ac000 {
+ cell-index = <0x2c>;
+- compatible = "fsl,fman-v2-port-tx";
++ compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
+@@ -35,7 +35,7 @@
+ fman@400000 {
+ fman0_rx_0x08: port@88000 {
+ cell-index = <0x8>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
+ reg = <0x88000 0x1000>;
+ fsl,fman-10g-port;
+ fsl,fman-best-effort-port;
+@@ -43,7 +43,7 @@ fman@400000 {
+
+ fman0_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
+ reg = <0xa8000 0x1000>;
+ fsl,fman-10g-port;
+ fsl,fman-best-effort-port;
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
+@@ -35,14 +35,14 @@
+ fman@400000 {
+ fman0_rx_0x10: port@90000 {
+ cell-index = <0x10>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman0_tx_0x30: port@b0000 {
+ cell-index = <0x30>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ fsl,fman-10g-port;
+ };
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
+@@ -35,7 +35,7 @@
+ fman@400000 {
+ fman0_rx_0x09: port@89000 {
+ cell-index = <0x9>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
+ reg = <0x89000 0x1000>;
+ fsl,fman-10g-port;
+ fsl,fman-best-effort-port;
+@@ -43,7 +43,7 @@ fman@400000 {
+
+ fman0_tx_0x29: port@a9000 {
+ cell-index = <0x29>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
+ reg = <0xa9000 0x1000>;
+ fsl,fman-10g-port;
+ fsl,fman-best-effort-port;
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
+@@ -35,14 +35,14 @@
+ fman@400000 {
+ fman0_rx_0x11: port@91000 {
+ cell-index = <0x11>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
+ reg = <0x91000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman0_tx_0x31: port@b1000 {
+ cell-index = <0x31>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
+ reg = <0xb1000 0x1000>;
+ fsl,fman-10g-port;
+ };
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x08: port@88000 {
+ cell-index = <0x8>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+
+ fman0_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x09: port@89000 {
+ cell-index = <0x9>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+
+ fman0_tx_0x29: port@a9000 {
+ cell-index = <0x29>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x0a: port@8a000 {
+ cell-index = <0xa>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+
+ fman0_tx_0x2a: port@aa000 {
+ cell-index = <0x2a>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x0b: port@8b000 {
+ cell-index = <0xb>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+
+ fman0_tx_0x2b: port@ab000 {
+ cell-index = <0x2b>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x0c: port@8c000 {
+ cell-index = <0xc>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+
+ fman0_tx_0x2c: port@ac000 {
+ cell-index = <0x2c>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
+@@ -35,13 +35,13 @@
+ fman@400000 {
+ fman0_rx_0x0d: port@8d000 {
+ cell-index = <0xd>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8d000 0x1000>;
+ };
+
+ fman0_tx_0x2d: port@ad000 {
+ cell-index = <0x2d>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xad000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
+@@ -35,14 +35,14 @@
+ fman@500000 {
+ fman1_rx_0x10: port@90000 {
+ cell-index = <0x10>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman1_tx_0x30: port@b0000 {
+ cell-index = <0x30>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ fsl,fman-10g-port;
+ };
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
+@@ -35,14 +35,14 @@
+ fman@500000 {
+ fman1_rx_0x11: port@91000 {
+ cell-index = <0x11>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
+ reg = <0x91000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman1_tx_0x31: port@b1000 {
+ cell-index = <0x31>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
+ reg = <0xb1000 0x1000>;
+ fsl,fman-10g-port;
+ };
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x08: port@88000 {
+ cell-index = <0x8>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+
+ fman1_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x09: port@89000 {
+ cell-index = <0x9>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+
+ fman1_tx_0x29: port@a9000 {
+ cell-index = <0x29>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x0a: port@8a000 {
+ cell-index = <0xa>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+
+ fman1_tx_0x2a: port@aa000 {
+ cell-index = <0x2a>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x0b: port@8b000 {
+ cell-index = <0xb>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+
+ fman1_tx_0x2b: port@ab000 {
+ cell-index = <0x2b>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x0c: port@8c000 {
+ cell-index = <0xc>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+
+ fman1_tx_0x2c: port@ac000 {
+ cell-index = <0x2c>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
+ };
+
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
+@@ -35,13 +35,13 @@
+ fman@500000 {
+ fman1_rx_0x0d: port@8d000 {
+ cell-index = <0xd>;
+- compatible = "fsl,fman-v3-port-rx";
++ compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
+ reg = <0x8d000 0x1000>;
+ };
+
+ fman1_tx_0x2d: port@ad000 {
+ cell-index = <0x2d>;
+- compatible = "fsl,fman-v3-port-tx";
++ compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
+ reg = <0xad000 0x1000>;
+ };
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 12:34:43 +0000