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authorBirger Koblitz <git@birger-koblitz.de>2022-04-24 22:01:31 +0200
committerSander Vanheule <sander@svanheule.net>2022-05-14 21:26:14 +0200
commita374a959b9125e5771a7b82a98444c300a04bb22 (patch)
tree261d24cd7dcaa134f960b0d7bc104aeb9b4a28c0 /target/linux/lantiq
parent7b4702afef64b71c6c103b962535d390f3b7f240 (diff)
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realtek: do not reset SerDes on link change
Do not reset the RTL930x SerDes on link changes, instead set up the SDS with internal PHYs for the SFP+ ports only. This fixes the 8 1GBit ports on the Zyxel XGS1250 which do not work without this patch. A complete SerDes reset was performed on all SerDes links. For copper 1Gbit ports, this is commonly a single XGMII link to an RTL8218D. There is however no support for setting up the XGMII link on RTL9300/RTL9310, thereby wiping the (RX/TX) setup done by u-boot and breaking the 1GBit ports. No SerDes reset should be done for these links. The handling of SGMII/HiSGMII, 1000BX or 10GR links is actually entirely different. All these modes need to be suitably RX calibrated and the pre- main and post- amplifiers set up properly for TX. The 10GBit SFP+ fiber links are recalibrated instead of reset, which e.g. is necessary when someone pulls a module out and puts another in. This makes swapping out 10GBit fiber modules possible. 1GBit modules are not yet supported, nor any modules with an internal phy. Tested-by: Stijn Segers <foss@volatilesystems.org> Signed-off-by: Birger Koblitz <git@birger-koblitz.de> [rewrite commit message based on discussion] Link: http://lists.infradead.org/pipermail/openwrt-devel/2022-May/038623.html Signed-off-by: Sander Vanheule <sander@svanheule.net> (cherry picked from commit d1b824650f1ee694ec2dbdd2f4f9ec64e650cf86)
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