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authorJohn Crispin <john@openwrt.org>2015-03-11 17:08:46 +0000
committerJohn Crispin <john@openwrt.org>2015-03-11 17:08:46 +0000
commitda3fd5dbf9754b9bb933ae935b3f63d2cef8c4a7 (patch)
tree3b580b5d62f5aa6e2f585d9e4c644c4c257553c8 /target/linux/lantiq
parentd5c250b91a20b91bf2f5816b92d4ce46cf5e43e4 (diff)
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kenrel: refresh patches
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44678
Diffstat (limited to 'target/linux/lantiq')
-rw-r--r--target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch16
-rw-r--r--target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch4
-rw-r--r--target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch8
-rw-r--r--target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch4
-rw-r--r--target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch8
-rw-r--r--target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch8
-rw-r--r--target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch480
-rw-r--r--target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch6
-rw-r--r--target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch2
9 files changed, 268 insertions, 268 deletions
diff --git a/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch
index 2fef09af77..2cc0814194 100644
--- a/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch
+++ b/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch
@@ -41,7 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
-@@ -17,6 +17,7 @@
+@@ -17,6 +17,7 @@ config SOC_XWAY
bool "XWAY"
select SOC_TYPE_XWAY
select HW_HAS_PCI
@@ -49,7 +49,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
config SOC_FALCON
bool "FALCON"
-@@ -37,6 +38,15 @@
+@@ -37,6 +38,15 @@ config PCI_LANTIQ
bool "PCI Support"
depends on SOC_XWAY && PCI
@@ -67,7 +67,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
depends on SOC_XWAY
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
-@@ -377,6 +377,8 @@
+@@ -377,6 +377,8 @@ void __init ltq_soc_init(void)
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_PPE_TOP);
clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
@@ -78,7 +78,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
ltq_ar9_fpi_hz(), CLOCK_250M);
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
-@@ -43,6 +43,8 @@
+@@ -43,6 +43,8 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
@@ -188,7 +188,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
if (ltq_pci_plat_dev_init)
return ltq_pci_plat_dev_init(dev);
-@@ -25,5 +26,7 @@
+@@ -25,5 +26,7 @@ int pcibios_plat_dev_init(struct pci_dev
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
@@ -4161,7 +4161,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
-@@ -251,6 +251,31 @@
+@@ -251,6 +251,31 @@ static int __init pcibios_init(void)
subsys_initcall(pcibios_init);
@@ -5503,7 +5503,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
--- a/drivers/pci/pcie/aer/Kconfig
+++ b/drivers/pci/pcie/aer/Kconfig
-@@ -19,6 +19,7 @@
+@@ -19,6 +19,7 @@ config PCIEAER
config PCIE_ECRC
bool "PCI Express ECRC settings control"
depends on PCIEAER
@@ -5513,7 +5513,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
(transaction layer end-to-end CRC checking).
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
-@@ -1160,6 +1160,8 @@
+@@ -1160,6 +1160,8 @@ void pci_walk_bus(struct pci_bus *top, i
void *userdata);
int pci_cfg_space_size(struct pci_dev *dev);
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
diff --git a/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch b/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
index 98fe4c2b77..203eb9495e 100644
--- a/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
+++ b/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
@@ -22,7 +22,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
-@@ -198,6 +199,10 @@
+@@ -198,6 +199,10 @@ static int m25p_probe(struct spi_device
enum read_mode mode = SPI_NOR_NORMAL;
char *flash_name = NULL;
int ret;
@@ -33,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
data = dev_get_platdata(&spi->dev);
-@@ -229,6 +234,8 @@
+@@ -229,6 +234,8 @@ static int m25p_probe(struct spi_device
if (data && data->name)
flash->mtd.name = data->name;
diff --git a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
index 3854d3a6bd..04c2071f32 100644
--- a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
+++ b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
@@ -30,7 +30,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#endif /* _PCI_ATH_FIXUP */
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-@@ -90,5 +90,8 @@
+@@ -90,5 +90,8 @@ int xrx200_gphy_boot(struct device *dev,
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
@@ -41,7 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#endif /* _LTQ_XWAY_H__ */
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
-@@ -2,4 +2,7 @@
+@@ -2,4 +2,7 @@ obj-y := prom.o sysctrl.o clk.o reset.o
obj-y += vmmc.o tffs.o
@@ -590,7 +590,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+device_initcall(of_ralink_eeprom_init);
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
-@@ -161,7 +161,7 @@
+@@ -161,7 +161,7 @@ struct ltq_etop_priv {
int tx_irq;
int rx_irq;
@@ -599,7 +599,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
int mii_mode;
spinlock_t lock;
-@@ -840,7 +840,11 @@
+@@ -840,7 +840,11 @@ ltq_etop_init(struct net_device *dev)
if (err)
goto err_hw;
diff --git a/target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch b/target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch
index cf9f00b5db..052e45e91b 100644
--- a/target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch
+++ b/target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch
@@ -38,7 +38,7 @@
/* remapped base addr of the reset control unit */
static void __iomem *ltq_rcu_membase;
static struct device_node *ltq_rcu_np;
-@@ -200,6 +231,45 @@
+@@ -200,6 +231,45 @@ static void ltq_machine_power_off(void)
unreachable();
}
@@ -84,7 +84,7 @@
static int __init mips_reboot_setup(void)
{
struct resource res;
-@@ -223,6 +293,9 @@
+@@ -223,6 +293,9 @@ static int __init mips_reboot_setup(void
if (!ltq_rcu_membase)
panic("Failed to remap core memory");
diff --git a/target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch b/target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch
index 4e51d3ee5e..76fbb7bac7 100644
--- a/target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch
+++ b/target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch
@@ -1,5 +1,5 @@
---- a/drivers/usb/dwc2/platform.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/platform.c 2015-02-09 19:22:41.974089626 +0200
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
@@ -40,6 +40,7 @@
#include <linux/device.h>
#include <linux/dma-mapping.h>
@@ -8,7 +8,7 @@
#include <linux/platform_device.h>
#include <linux/usb/of.h>
-@@ -154,6 +155,7 @@
+@@ -154,6 +155,7 @@ static int dwc2_driver_probe(struct plat
struct resource *res;
int retval;
int irq;
@@ -16,7 +16,7 @@
if (usb_disabled())
return -ENODEV;
-@@ -173,6 +175,16 @@
+@@ -173,6 +175,16 @@ static int dwc2_driver_probe(struct plat
defparams.dma_desc_enable = 0;
}
diff --git a/target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch b/target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch
index 74e9ecc2a5..396aa7d2e8 100644
--- a/target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch
+++ b/target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch
@@ -1,6 +1,6 @@
---- a/drivers/usb/dwc2/platform.c 2015-02-09 19:37:34.553109992 +0200
-+++ b/drivers/usb/dwc2/platform.c 2015-02-09 19:38:30.090111260 +0200
-@@ -105,6 +105,34 @@
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -106,6 +106,34 @@ static const struct dwc2_core_params par
.uframe_sched = -1,
};
@@ -35,7 +35,7 @@
/**
* dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
* DWC_otg driver
-@@ -128,6 +156,7 @@
+@@ -129,6 +157,7 @@ static int dwc2_driver_remove(struct pla
static const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
diff --git a/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch b/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch
index 38f75c8342..d1b23fc21c 100644
--- a/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch
+++ b/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch
@@ -1,6 +1,6 @@
---- a/drivers/usb/dwc2/core.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/core.c 2015-02-09 19:34:42.863106075 +0200
-@@ -67,10 +67,10 @@
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -67,10 +67,10 @@ static void dwc2_enable_common_interrupt
u32 intmsk;
/* Clear any pending OTG Interrupts */
@@ -13,7 +13,7 @@
/* Enable the interrupts in the GINTMSK */
intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
-@@ -81,7 +81,7 @@
+@@ -81,7 +81,7 @@ static void dwc2_enable_common_interrupt
intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP |
GINTSTS_SESSREQINT;
@@ -22,7 +22,7 @@
}
/*
-@@ -104,10 +104,10 @@
+@@ -104,10 +104,10 @@ static void dwc2_init_fs_ls_pclk_sel(str
}
dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
@@ -35,7 +35,7 @@
}
/*
-@@ -125,7 +125,7 @@
+@@ -125,7 +125,7 @@ static int dwc2_core_reset(struct dwc2_h
/* Wait for AHB master IDLE state */
do {
usleep_range(20000, 40000);
@@ -44,7 +44,7 @@
if (++count > 50) {
dev_warn(hsotg->dev,
"%s() HANG! AHB Idle GRSTCTL=%0x\n",
-@@ -137,10 +137,10 @@
+@@ -137,10 +137,10 @@ static int dwc2_core_reset(struct dwc2_h
/* Core Soft Reset */
count = 0;
greset |= GRSTCTL_CSFTRST;
@@ -57,7 +57,7 @@
if (++count > 50) {
dev_warn(hsotg->dev,
"%s() HANG! Soft Reset GRSTCTL=%0x\n",
-@@ -150,20 +150,20 @@
+@@ -150,20 +150,20 @@ static int dwc2_core_reset(struct dwc2_h
} while (greset & GRSTCTL_CSFTRST);
if (hsotg->dr_mode == USB_DR_MODE_HOST) {
@@ -84,7 +84,7 @@
}
/*
-@@ -186,9 +186,9 @@
+@@ -186,9 +186,9 @@ static int dwc2_fs_phy_init(struct dwc2_
*/
if (select_phy) {
dev_dbg(hsotg->dev, "FS PHY selected\n");
@@ -96,7 +96,7 @@
/* Reset after a PHY select */
retval = dwc2_core_reset(hsotg);
-@@ -211,18 +211,18 @@
+@@ -211,18 +211,18 @@ static int dwc2_fs_phy_init(struct dwc2_
dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
/* Program GUSBCFG.OtgUtmiFsSel to I2C */
@@ -120,7 +120,7 @@
}
return retval;
-@@ -236,7 +236,7 @@
+@@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_
if (!select_phy)
return 0;
@@ -129,7 +129,7 @@
/*
* HS PHY parameters. These parameters are preserved during soft reset
-@@ -264,7 +264,7 @@
+@@ -264,7 +264,7 @@ static int dwc2_hs_phy_init(struct dwc2_
break;
}
@@ -138,7 +138,7 @@
/* Reset after setting the PHY parameters */
retval = dwc2_core_reset(hsotg);
-@@ -299,15 +299,15 @@
+@@ -299,15 +299,15 @@ static int dwc2_phy_init(struct dwc2_hso
hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
hsotg->core_params->ulpi_fs_ls > 0) {
dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
@@ -158,7 +158,7 @@
}
return retval;
-@@ -315,7 +315,7 @@
+@@ -315,7 +315,7 @@ static int dwc2_phy_init(struct dwc2_hso
static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
{
@@ -167,7 +167,7 @@
switch (hsotg->hw_params.arch) {
case GHWCFG2_EXT_DMA_ARCH:
-@@ -354,7 +354,7 @@
+@@ -354,7 +354,7 @@ static int dwc2_gahbcfg_init(struct dwc2
if (hsotg->core_params->dma_enable > 0)
ahbcfg |= GAHBCFG_DMA_EN;
@@ -176,7 +176,7 @@
return 0;
}
-@@ -363,7 +363,7 @@
+@@ -363,7 +363,7 @@ static void dwc2_gusbcfg_init(struct dwc
{
u32 usbcfg;
@@ -185,7 +185,7 @@
usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
switch (hsotg->hw_params.op_mode) {
-@@ -391,7 +391,7 @@
+@@ -391,7 +391,7 @@ static void dwc2_gusbcfg_init(struct dwc
break;
}
@@ -194,7 +194,7 @@
}
/**
-@@ -409,7 +409,7 @@
+@@ -409,7 +409,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs
dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
@@ -203,7 +203,7 @@
/* Set ULPI External VBUS bit if needed */
usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
-@@ -422,7 +422,7 @@
+@@ -422,7 +422,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs
if (hsotg->core_params->ts_dline > 0)
usbcfg |= GUSBCFG_TERMSELDLPULSE;
@@ -212,7 +212,7 @@
/* Reset the Controller */
retval = dwc2_core_reset(hsotg);
-@@ -448,11 +448,11 @@
+@@ -448,11 +448,11 @@ int dwc2_core_init(struct dwc2_hsotg *hs
dwc2_gusbcfg_init(hsotg);
/* Program the GOTGCTL register */
@@ -226,7 +226,7 @@
dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
/* Clear the SRP success bit for FS-I2c */
-@@ -498,16 +498,16 @@
+@@ -498,16 +498,16 @@ void dwc2_enable_host_interrupts(struct
dev_dbg(hsotg->dev, "%s()\n", __func__);
/* Disable all interrupts */
@@ -247,7 +247,7 @@
}
/**
-@@ -517,12 +517,12 @@
+@@ -517,12 +517,12 @@ void dwc2_enable_host_interrupts(struct
*/
void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
{
@@ -262,7 +262,7 @@
}
/*
-@@ -602,36 +602,36 @@
+@@ -602,36 +602,36 @@ static void dwc2_config_fifos(struct dwc
dwc2_calculate_dynamic_fifo(hsotg);
/* Rx FIFO */
@@ -308,7 +308,7 @@
if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
-@@ -639,14 +639,14 @@
+@@ -639,14 +639,14 @@ static void dwc2_config_fifos(struct dwc
* Global DFIFOCFG calculation for Host mode -
* include RxFIFO, NPTXFIFO and HPTXFIFO
*/
@@ -325,7 +325,7 @@
}
}
-@@ -667,14 +667,14 @@
+@@ -667,14 +667,14 @@ void dwc2_core_host_init(struct dwc2_hso
dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
/* Restart the Phy Clock */
@@ -343,7 +343,7 @@
}
/*
-@@ -683,9 +683,9 @@
+@@ -683,9 +683,9 @@ void dwc2_core_host_init(struct dwc2_hso
* and its value must not be changed during runtime.
*/
if (hsotg->core_params->reload_ctl > 0) {
@@ -355,7 +355,7 @@
}
if (hsotg->core_params->dma_desc_enable > 0) {
-@@ -701,9 +701,9 @@
+@@ -701,9 +701,9 @@ void dwc2_core_host_init(struct dwc2_hso
"falling back to buffer DMA mode.\n");
hsotg->core_params->dma_desc_enable = 0;
} else {
@@ -367,7 +367,7 @@
}
}
-@@ -712,18 +712,18 @@
+@@ -712,18 +712,18 @@ void dwc2_core_host_init(struct dwc2_hso
/* TODO - check this */
/* Clear Host Set HNP Enable in the OTG Control Register */
@@ -390,7 +390,7 @@
if (hsotg->core_params->dma_desc_enable <= 0) {
int num_channels, i;
-@@ -732,25 +732,25 @@
+@@ -732,25 +732,25 @@ void dwc2_core_host_init(struct dwc2_hso
/* Flush out any leftover queued requests */
num_channels = hsotg->core_params->host_channels;
for (i = 0; i < num_channels; i++) {
@@ -421,7 +421,7 @@
if (++count > 1000) {
dev_err(hsotg->dev,
"Unable to clear enable on channel %d\n",
-@@ -771,7 +771,7 @@
+@@ -771,7 +771,7 @@ void dwc2_core_host_init(struct dwc2_hso
!!(hprt0 & HPRT0_PWR));
if (!(hprt0 & HPRT0_PWR)) {
hprt0 |= HPRT0_PWR;
@@ -430,7 +430,7 @@
}
}
-@@ -851,7 +851,7 @@
+@@ -851,7 +851,7 @@ static void dwc2_hc_enable_slave_ints(st
break;
}
@@ -439,7 +439,7 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
}
-@@ -888,7 +888,7 @@
+@@ -888,7 +888,7 @@ static void dwc2_hc_enable_dma_ints(stru
}
}
@@ -448,7 +448,7 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
}
-@@ -909,16 +909,16 @@
+@@ -909,16 +909,16 @@ static void dwc2_hc_enable_ints(struct d
}
/* Enable the top level host channel interrupt */
@@ -469,7 +469,7 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
}
-@@ -947,7 +947,7 @@
+@@ -947,7 +947,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
/* Clear old interrupt conditions for this host channel */
hcintmsk = 0xffffffff;
hcintmsk &= ~HCINTMSK_RESERVED14_31;
@@ -478,7 +478,7 @@
/* Enable channel interrupts required for this transfer */
dwc2_hc_enable_ints(hsotg, chan);
-@@ -964,7 +964,7 @@
+@@ -964,7 +964,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
hcchar |= HCCHAR_LSPDDEV;
hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
@@ -487,7 +487,7 @@
if (dbg_hc(chan)) {
dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
hc_num, hcchar);
-@@ -1018,7 +1018,7 @@
+@@ -1018,7 +1018,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
}
}
@@ -496,7 +496,7 @@
}
/**
-@@ -1070,14 +1070,14 @@
+@@ -1070,14 +1070,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
u32 hcintmsk = HCINTMSK_CHHLTD;
dev_vdbg(hsotg->dev, "dequeue/error\n");
@@ -513,7 +513,7 @@
/*
* Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
-@@ -1086,7 +1086,7 @@
+@@ -1086,7 +1086,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
*/
chan->halt_status = halt_status;
@@ -522,7 +522,7 @@
if (!(hcchar & HCCHAR_CHENA)) {
/*
* The channel is either already halted or it hasn't
-@@ -1114,7 +1114,7 @@
+@@ -1114,7 +1114,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
return;
}
@@ -531,7 +531,7 @@
/* No need to set the bit in DDMA for disabling the channel */
/* TODO check it everywhere channel is disabled */
-@@ -1137,7 +1137,7 @@
+@@ -1137,7 +1137,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
chan->ep_type == USB_ENDPOINT_XFER_BULK) {
dev_vdbg(hsotg->dev, "control/bulk\n");
@@ -540,7 +540,7 @@
if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
dev_vdbg(hsotg->dev, "Disabling channel\n");
hcchar &= ~HCCHAR_CHENA;
-@@ -1145,7 +1145,7 @@
+@@ -1145,7 +1145,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
} else {
if (dbg_perio())
dev_vdbg(hsotg->dev, "isoc/intr\n");
@@ -549,7 +549,7 @@
if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
hsotg->queuing_high_bandwidth) {
if (dbg_perio())
-@@ -1158,7 +1158,7 @@
+@@ -1158,7 +1158,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
dev_vdbg(hsotg->dev, "DMA enabled\n");
}
@@ -558,7 +558,7 @@
chan->halt_status = halt_status;
if (hcchar & HCCHAR_CHENA) {
-@@ -1205,10 +1205,10 @@
+@@ -1205,10 +1205,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *
* Clear channel interrupt enables and any unhandled channel interrupt
* conditions
*/
@@ -571,7 +571,7 @@
}
/**
-@@ -1294,13 +1294,13 @@
+@@ -1294,13 +1294,13 @@ static void dwc2_hc_write_packet(struct
if (((unsigned long)data_buf & 0x3) == 0) {
/* xfer_buf is DWORD aligned */
for (i = 0; i < dword_count; i++, data_buf++)
@@ -587,7 +587,7 @@
}
}
-@@ -1453,7 +1453,7 @@
+@@ -1453,7 +1453,7 @@ void dwc2_hc_start_transfer(struct dwc2_
hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
TSIZ_SC_MC_PID_MASK;
@@ -596,7 +596,7 @@
if (dbg_hc(chan)) {
dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
hctsiz, chan->hc_num);
-@@ -1481,7 +1481,7 @@
+@@ -1481,7 +1481,7 @@ void dwc2_hc_start_transfer(struct dwc2_
} else {
dma_addr = chan->xfer_dma;
}
@@ -605,7 +605,7 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
(unsigned long)dma_addr, chan->hc_num);
-@@ -1489,13 +1489,13 @@
+@@ -1489,13 +1489,13 @@ void dwc2_hc_start_transfer(struct dwc2_
/* Start the split */
if (chan->do_split) {
@@ -622,7 +622,7 @@
hcchar &= ~HCCHAR_MULTICNT_MASK;
hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
HCCHAR_MULTICNT_MASK;
-@@ -1515,7 +1515,7 @@
+@@ -1515,7 +1515,7 @@ void dwc2_hc_start_transfer(struct dwc2_
(hcchar & HCCHAR_MULTICNT_MASK) >>
HCCHAR_MULTICNT_SHIFT);
@@ -631,7 +631,7 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
chan->hc_num);
-@@ -1574,18 +1574,18 @@
+@@ -1574,18 +1574,18 @@ void dwc2_hc_start_transfer_ddma(struct
dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
}
@@ -653,7 +653,7 @@
hcchar &= ~HCCHAR_MULTICNT_MASK;
hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
HCCHAR_MULTICNT_MASK;
-@@ -1604,7 +1604,7 @@
+@@ -1604,7 +1604,7 @@ void dwc2_hc_start_transfer_ddma(struct
(hcchar & HCCHAR_MULTICNT_MASK) >>
HCCHAR_MULTICNT_SHIFT);
@@ -662,7 +662,7 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
chan->hc_num);
-@@ -1661,7 +1661,7 @@
+@@ -1661,7 +1661,7 @@ int dwc2_hc_continue_transfer(struct dwc
* transfer completes, the extra requests for the channel will
* be flushed.
*/
@@ -671,7 +671,7 @@
dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
hcchar |= HCCHAR_CHENA;
-@@ -1669,7 +1669,7 @@
+@@ -1669,7 +1669,7 @@ int dwc2_hc_continue_transfer(struct dwc
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
hcchar);
@@ -680,7 +680,7 @@
chan->requests++;
return 1;
}
-@@ -1679,7 +1679,7 @@
+@@ -1679,7 +1679,7 @@ int dwc2_hc_continue_transfer(struct dwc
if (chan->xfer_count < chan->xfer_len) {
if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
@@ -689,7 +689,7 @@
HCCHAR(chan->hc_num));
dwc2_hc_set_even_odd_frame(hsotg, chan,
-@@ -1716,12 +1716,12 @@
+@@ -1716,12 +1716,12 @@ void dwc2_hc_do_ping(struct dwc2_hsotg *
hctsiz = TSIZ_DOPNG;
hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
@@ -705,7 +705,7 @@
}
/**
-@@ -1740,8 +1740,8 @@
+@@ -1740,8 +1740,8 @@ u32 dwc2_calc_frame_interval(struct dwc2
u32 hprt0;
int clock = 60; /* default value */
@@ -716,7 +716,7 @@
if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
!(usbcfg & GUSBCFG_PHYIF16))
-@@ -1797,7 +1797,7 @@
+@@ -1797,7 +1797,7 @@ void dwc2_read_packet(struct dwc2_hsotg
dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
for (i = 0; i < word_count; i++, data_buf++)
@@ -725,7 +725,7 @@
}
/**
-@@ -1817,56 +1817,56 @@
+@@ -1817,56 +1817,56 @@ void dwc2_dump_host_registers(struct dwc
dev_dbg(hsotg->dev, "Host Global Registers\n");
addr = hsotg->regs + HCFG;
dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
@@ -797,7 +797,7 @@
}
}
#endif
-@@ -1888,80 +1888,80 @@
+@@ -1888,80 +1888,80 @@ void dwc2_dump_global_registers(struct d
dev_dbg(hsotg->dev, "Core Global Registers\n");
addr = hsotg->regs + GOTGCTL;
dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
@@ -903,7 +903,7 @@
#endif
}
-@@ -1980,15 +1980,15 @@
+@@ -1980,15 +1980,15 @@ void dwc2_flush_tx_fifo(struct dwc2_hsot
greset = GRSTCTL_TXFFLSH;
greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
@@ -922,7 +922,7 @@
break;
}
udelay(1);
-@@ -2011,10 +2011,10 @@
+@@ -2011,10 +2011,10 @@ void dwc2_flush_rx_fifo(struct dwc2_hsot
dev_vdbg(hsotg->dev, "%s()\n", __func__);
greset = GRSTCTL_RXFFLSH;
@@ -935,7 +935,7 @@
if (++count > 10000) {
dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
__func__, greset);
-@@ -2676,7 +2676,7 @@
+@@ -2676,7 +2676,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg
* 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
* as in "OTG version 2.xx" or "OTG version 3.xx".
*/
@@ -944,7 +944,7 @@
if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
(hw->snpsid & 0xfffff000) != 0x4f543000) {
dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
-@@ -2688,11 +2688,11 @@
+@@ -2688,11 +2688,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg
hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
@@ -961,7 +961,7 @@
dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
-@@ -2701,18 +2701,18 @@
+@@ -2701,18 +2701,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg
dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
/* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
@@ -986,7 +986,7 @@
usleep_range(100000, 150000);
/* hwcfg2 */
-@@ -2831,7 +2831,7 @@
+@@ -2831,7 +2831,7 @@ u16 dwc2_get_otg_version(struct dwc2_hso
bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
{
@@ -995,7 +995,7 @@
return false;
else
return true;
-@@ -2845,10 +2845,10 @@
+@@ -2845,10 +2845,10 @@ bool dwc2_is_controller_alive(struct dwc
*/
void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
{
@@ -1008,7 +1008,7 @@
}
/**
-@@ -2859,10 +2859,10 @@
+@@ -2859,10 +2859,10 @@ void dwc2_enable_global_interrupts(struc
*/
void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
{
@@ -1021,8 +1021,8 @@
}
MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
---- a/drivers/usb/dwc2/core.h 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/core.h 2015-02-09 19:34:09.985105325 +0200
+--- a/drivers/usb/dwc2/core.h
++++ b/drivers/usb/dwc2/core.h
@@ -44,16 +44,28 @@
#include <linux/usb/phy.h>
#include "hw.h"
@@ -1058,9 +1058,9 @@
/* Maximum number of Endpoints/HostChannels */
#define MAX_EPS_CHANNELS 16
---- a/drivers/usb/dwc2/core_intr.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/core_intr.c 2015-02-09 19:34:42.865106075 +0200
-@@ -80,15 +80,15 @@
+--- a/drivers/usb/dwc2/core_intr.c
++++ b/drivers/usb/dwc2/core_intr.c
+@@ -80,15 +80,15 @@ static const char *dwc2_op_state_str(str
*/
static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
{
@@ -1079,7 +1079,7 @@
}
/**
-@@ -102,7 +102,7 @@
+@@ -102,7 +102,7 @@ static void dwc2_handle_mode_mismatch_in
dwc2_is_host_mode(hsotg) ? "Host" : "Device");
/* Clear interrupt */
@@ -1088,7 +1088,7 @@
}
/**
-@@ -117,8 +117,8 @@
+@@ -117,8 +117,8 @@ static void dwc2_handle_otg_intr(struct
u32 gotgctl;
u32 gintmsk;
@@ -1099,7 +1099,7 @@
dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
dwc2_op_state_str(hsotg));
-@@ -126,7 +126,7 @@
+@@ -126,7 +126,7 @@ static void dwc2_handle_otg_intr(struct
dev_dbg(hsotg->dev,
" ++OTG Interrupt: Session End Detected++ (%s)\n",
dwc2_op_state_str(hsotg));
@@ -1108,7 +1108,7 @@
if (hsotg->op_state == OTG_STATE_B_HOST) {
hsotg->op_state = OTG_STATE_B_PERIPHERAL;
-@@ -149,15 +149,15 @@
+@@ -149,15 +149,15 @@ static void dwc2_handle_otg_intr(struct
hsotg->lx_state = DWC2_L0;
}
@@ -1127,7 +1127,7 @@
if (gotgctl & GOTGCTL_SESREQSCS) {
if (hsotg->core_params->phy_type ==
DWC2_PHY_TYPE_PARAM_FS
-@@ -165,9 +165,9 @@
+@@ -165,9 +165,9 @@ static void dwc2_handle_otg_intr(struct
hsotg->srp_success = 1;
} else {
/* Clear Session Request */
@@ -1139,7 +1139,7 @@
}
}
}
-@@ -177,7 +177,7 @@
+@@ -177,7 +177,7 @@ static void dwc2_handle_otg_intr(struct
* Print statements during the HNP interrupt handling
* can cause it to fail
*/
@@ -1148,7 +1148,7 @@
/*
* WA for 3.00a- HW is not setting cur_mode, even sometimes
* this does not help
-@@ -197,9 +197,9 @@
+@@ -197,9 +197,9 @@ static void dwc2_handle_otg_intr(struct
* interrupt does not get handled and Linux
* complains loudly.
*/
@@ -1160,7 +1160,7 @@
/*
* Call callback function with spin lock
-@@ -213,9 +213,9 @@
+@@ -213,9 +213,9 @@ static void dwc2_handle_otg_intr(struct
hsotg->op_state = OTG_STATE_B_HOST;
}
} else {
@@ -1172,7 +1172,7 @@
dev_dbg(hsotg->dev, "HNP Failed\n");
dev_err(hsotg->dev,
"Device Not Connected/Responding\n");
-@@ -241,9 +241,9 @@
+@@ -241,9 +241,9 @@ static void dwc2_handle_otg_intr(struct
hsotg->op_state = OTG_STATE_A_PERIPHERAL;
} else {
/* Need to disable SOF interrupt immediately */
@@ -1184,7 +1184,7 @@
spin_unlock(&hsotg->lock);
dwc2_hcd_start(hsotg);
spin_lock(&hsotg->lock);
-@@ -258,7 +258,7 @@
+@@ -258,7 +258,7 @@ static void dwc2_handle_otg_intr(struct
dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
/* Clear GOTGINT */
@@ -1193,7 +1193,7 @@
}
/**
-@@ -273,11 +273,11 @@
+@@ -273,11 +273,11 @@ static void dwc2_handle_otg_intr(struct
*/
static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
{
@@ -1207,7 +1207,7 @@
dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
dwc2_is_host_mode(hsotg) ? "Host" : "Device");
-@@ -292,7 +292,7 @@
+@@ -292,7 +292,7 @@ static void dwc2_handle_conn_id_status_c
spin_lock(&hsotg->lock);
/* Clear interrupt */
@@ -1216,7 +1216,7 @@
}
/**
-@@ -311,7 +311,7 @@
+@@ -311,7 +311,7 @@ static void dwc2_handle_session_req_intr
dev_dbg(hsotg->dev, "++Session Request Interrupt++\n");
/* Clear interrupt */
@@ -1225,7 +1225,7 @@
}
/*
-@@ -327,23 +327,23 @@
+@@ -327,23 +327,23 @@ static void dwc2_handle_wakeup_detected_
dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
if (dwc2_is_device_mode(hsotg)) {
@@ -1254,7 +1254,7 @@
mod_timer(&hsotg->wkp_timer,
jiffies + msecs_to_jiffies(71));
} else {
-@@ -353,7 +353,7 @@
+@@ -353,7 +353,7 @@ static void dwc2_handle_wakeup_detected_
}
/* Clear interrupt */
@@ -1263,7 +1263,7 @@
}
/*
-@@ -369,7 +369,7 @@
+@@ -369,7 +369,7 @@ static void dwc2_handle_disconnect_intr(
/* Change to L3 (OFF) state */
hsotg->lx_state = DWC2_L3;
@@ -1272,7 +1272,7 @@
}
/*
-@@ -391,7 +391,7 @@
+@@ -391,7 +391,7 @@ static void dwc2_handle_usb_suspend_intr
* Check the Device status register to determine if the Suspend
* state is active
*/
@@ -1281,7 +1281,7 @@
dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
dev_dbg(hsotg->dev,
"DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
-@@ -413,7 +413,7 @@
+@@ -413,7 +413,7 @@ static void dwc2_handle_usb_suspend_intr
hsotg->lx_state = DWC2_L2;
/* Clear interrupt */
@@ -1290,7 +1290,7 @@
}
#define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
-@@ -431,9 +431,9 @@
+@@ -431,9 +431,9 @@ static u32 dwc2_read_common_intr(struct
u32 gahbcfg;
u32 gintmsk_common = GINTMSK_COMMON;
@@ -1303,9 +1303,9 @@
/* If any common interrupts set */
if (gintsts & gintmsk_common)
---- a/drivers/usb/dwc2/gadget.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/gadget.c 2015-02-09 19:34:42.891106076 +0200
-@@ -55,12 +55,12 @@
+--- a/drivers/usb/dwc2/gadget.c
++++ b/drivers/usb/dwc2/gadget.c
+@@ -55,12 +55,12 @@ static inline struct s3c_hsotg *to_hsotg
static inline void __orr32(void __iomem *ptr, u32 val)
{
@@ -1320,7 +1320,7 @@
}
/* forward decleration of functions */
-@@ -97,14 +97,14 @@
+@@ -97,14 +97,14 @@ static inline bool using_dma(struct s3c_
*/
static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
{
@@ -1337,7 +1337,7 @@
}
}
-@@ -115,13 +115,13 @@
+@@ -115,13 +115,13 @@ static void s3c_hsotg_en_gsint(struct s3
*/
static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
{
@@ -1353,7 +1353,7 @@
}
/**
-@@ -146,12 +146,12 @@
+@@ -146,12 +146,12 @@ static void s3c_hsotg_ctrl_epint(struct
bit <<= 16;
local_irq_save(flags);
@@ -1368,7 +1368,7 @@
local_irq_restore(flags);
}
-@@ -169,8 +169,8 @@
+@@ -169,8 +169,8 @@ static void s3c_hsotg_init_fifo(struct s
/* set FIFO sizes to 2048/1024 */
@@ -1379,7 +1379,7 @@
(1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
/*
-@@ -200,7 +200,7 @@
+@@ -200,7 +200,7 @@ static void s3c_hsotg_init_fifo(struct s
"insufficient fifo memory");
addr += size;
@@ -1388,7 +1388,7 @@
}
/* 768*4=3072 bytes FIFO length */
size = 768;
-@@ -211,7 +211,7 @@
+@@ -211,7 +211,7 @@ static void s3c_hsotg_init_fifo(struct s
"insufficient fifo memory");
addr += size;
@@ -1397,7 +1397,7 @@
}
/*
-@@ -219,13 +219,13 @@
+@@ -219,13 +219,13 @@ static void s3c_hsotg_init_fifo(struct s
* all fifos are flushed before continuing
*/
@@ -1413,7 +1413,7 @@
if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
break;
-@@ -317,7 +317,7 @@
+@@ -317,7 +317,7 @@ static int s3c_hsotg_write_fifo(struct s
struct s3c_hsotg_req *hs_req)
{
bool periodic = is_ep_periodic(hs_ep);
@@ -1422,7 +1422,7 @@
int buf_pos = hs_req->req.actual;
int to_write = hs_ep->size_loaded;
void *data;
-@@ -332,7 +332,7 @@
+@@ -332,7 +332,7 @@ static int s3c_hsotg_write_fifo(struct s
return 0;
if (periodic && !hsotg->dedicated_fifos) {
@@ -1431,7 +1431,7 @@
int size_left;
int size_done;
-@@ -373,7 +373,7 @@
+@@ -373,7 +373,7 @@ static int s3c_hsotg_write_fifo(struct s
return -ENOSPC;
}
} else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
@@ -1440,7 +1440,7 @@
can_write &= 0xffff;
can_write *= 4;
-@@ -550,11 +550,11 @@
+@@ -550,11 +550,11 @@ static void s3c_hsotg_start_req(struct s
epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
@@ -1454,7 +1454,7 @@
if (ctrl & DXEPCTL_STALL) {
dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
-@@ -622,7 +622,7 @@
+@@ -622,7 +622,7 @@ static void s3c_hsotg_start_req(struct s
hs_ep->req = hs_req;
/* write size / packets */
@@ -1463,7 +1463,7 @@
if (using_dma(hsotg) && !continuing) {
unsigned int dma_reg;
-@@ -633,7 +633,7 @@
+@@ -633,7 +633,7 @@ static void s3c_hsotg_start_req(struct s
*/
dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
@@ -1472,7 +1472,7 @@
dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
__func__, &ureq->dma, dma_reg);
-@@ -652,7 +652,7 @@
+@@ -652,7 +652,7 @@ static void s3c_hsotg_start_req(struct s
dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
@@ -1481,7 +1481,7 @@
/*
* set these, it seems that DMA support increments past the end
-@@ -674,7 +674,7 @@
+@@ -674,7 +674,7 @@ static void s3c_hsotg_start_req(struct s
* to debugging to see what is going on.
*/
if (dir_in)
@@ -1490,7 +1490,7 @@
hsotg->regs + DIEPINT(index));
/*
-@@ -683,13 +683,13 @@
+@@ -683,13 +683,13 @@ static void s3c_hsotg_start_req(struct s
*/
/* check ep is enabled */
@@ -1507,7 +1507,7 @@
/* enable ep interrupts */
s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
-@@ -1051,14 +1051,14 @@
+@@ -1051,14 +1051,14 @@ static void s3c_hsotg_stall_ep0(struct s
* taken effect, so no need to clear later.
*/
@@ -1525,7 +1525,7 @@
/*
* complete won't be called, so we enqueue
-@@ -1108,11 +1108,11 @@
+@@ -1108,11 +1108,11 @@ static void s3c_hsotg_process_control(st
switch (ctrl->bRequest) {
case USB_REQ_SET_ADDRESS:
s3c_hsotg_disconnect(hsotg);
@@ -1539,7 +1539,7 @@
dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
-@@ -1302,7 +1302,7 @@
+@@ -1302,7 +1302,7 @@ static void s3c_hsotg_rx_data(struct s3c
if (!hs_req) {
@@ -1548,7 +1548,7 @@
int ptr;
dev_warn(hsotg->dev,
-@@ -1311,7 +1311,7 @@
+@@ -1311,7 +1311,7 @@ static void s3c_hsotg_rx_data(struct s3c
/* dump the data from the FIFO, we've nothing we can do */
for (ptr = 0; ptr < size; ptr += 4)
@@ -1557,7 +1557,7 @@
return;
}
-@@ -1378,14 +1378,14 @@
+@@ -1378,14 +1378,14 @@ static void s3c_hsotg_send_zlp(struct s3
dev_dbg(hsotg->dev, "sending zero-length packet\n");
/* issue a zero-sized packet to terminate this */
@@ -1575,7 +1575,7 @@
}
/**
-@@ -1401,7 +1401,7 @@
+@@ -1401,7 +1401,7 @@ static void s3c_hsotg_send_zlp(struct s3
static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
int epnum, bool was_setup)
{
@@ -1584,7 +1584,7 @@
struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
struct s3c_hsotg_req *hs_req = hs_ep->req;
struct usb_request *req = &hs_req->req;
-@@ -1475,7 +1475,7 @@
+@@ -1475,7 +1475,7 @@ static u32 s3c_hsotg_read_frameno(struct
{
u32 dsts;
@@ -1593,7 +1593,7 @@
dsts &= DSTS_SOFFN_MASK;
dsts >>= DSTS_SOFFN_SHIFT;
-@@ -1500,7 +1500,7 @@
+@@ -1500,7 +1500,7 @@ static u32 s3c_hsotg_read_frameno(struct
*/
static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
{
@@ -1602,7 +1602,7 @@
u32 epnum, status, size;
WARN_ON(using_dma(hsotg));
-@@ -1532,7 +1532,7 @@
+@@ -1532,7 +1532,7 @@ static void s3c_hsotg_handle_rx(struct s
dev_dbg(hsotg->dev,
"SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
s3c_hsotg_read_frameno(hsotg),
@@ -1611,7 +1611,7 @@
s3c_hsotg_handle_outdone(hsotg, epnum, true);
break;
-@@ -1545,7 +1545,7 @@
+@@ -1545,7 +1545,7 @@ static void s3c_hsotg_handle_rx(struct s
dev_dbg(hsotg->dev,
"SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
s3c_hsotg_read_frameno(hsotg),
@@ -1620,7 +1620,7 @@
s3c_hsotg_rx_data(hsotg, epnum, size);
break;
-@@ -1622,16 +1622,16 @@
+@@ -1622,16 +1622,16 @@ static void s3c_hsotg_set_ep_maxpacket(s
* if one of the directions may not be in use.
*/
@@ -1641,7 +1641,7 @@
}
return;
-@@ -1650,14 +1650,14 @@
+@@ -1650,14 +1650,14 @@ static void s3c_hsotg_txfifo_flush(struc
int timeout;
int val;
@@ -1658,7 +1658,7 @@
if ((val & (GRSTCTL_TXFFLSH)) == 0)
break;
-@@ -1718,7 +1718,7 @@
+@@ -1718,7 +1718,7 @@ static void s3c_hsotg_complete_in(struct
struct s3c_hsotg_ep *hs_ep)
{
struct s3c_hsotg_req *hs_req = hs_ep->req;
@@ -1667,7 +1667,7 @@
int size_left, size_done;
if (!hs_req) {
-@@ -1801,11 +1801,11 @@
+@@ -1801,11 +1801,11 @@ static void s3c_hsotg_epint(struct s3c_h
u32 ints;
u32 ctrl;
@@ -1682,7 +1682,7 @@
dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
__func__, idx, dir_in ? "in" : "out", ints);
-@@ -1816,13 +1816,13 @@
+@@ -1816,13 +1816,13 @@ static void s3c_hsotg_epint(struct s3c_h
ctrl |= DXEPCTL_SETEVENFR;
else
ctrl |= DXEPCTL_SETODDFR;
@@ -1699,7 +1699,7 @@
/*
* we get OutDone from the FIFO, so we only need to look
-@@ -1847,16 +1847,16 @@
+@@ -1847,16 +1847,16 @@ static void s3c_hsotg_epint(struct s3c_h
dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
if (dir_in) {
@@ -1719,7 +1719,7 @@
}
}
}
-@@ -1918,7 +1918,7 @@
+@@ -1918,7 +1918,7 @@ static void s3c_hsotg_epint(struct s3c_h
*/
static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
{
@@ -1728,7 +1728,7 @@
int ep0_mps = 0, ep_mps = 8;
/*
-@@ -1979,8 +1979,8 @@
+@@ -1979,8 +1979,8 @@ static void s3c_hsotg_irq_enumdone(struc
s3c_hsotg_enqueue_setup(hsotg);
dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
@@ -1739,7 +1739,7 @@
}
/**
-@@ -2014,7 +2014,7 @@
+@@ -2014,7 +2014,7 @@ static void kill_all_requests(struct s3c
}
if (!hsotg->dedicated_fifos)
return;
@@ -1748,7 +1748,7 @@
if (size < ep->fifo_size)
s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
}
-@@ -2084,11 +2084,11 @@
+@@ -2084,11 +2084,11 @@ static int s3c_hsotg_corereset(struct s3
dev_dbg(hsotg->dev, "resetting core\n");
/* issue soft reset */
@@ -1762,7 +1762,7 @@
} while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
if (grstctl & GRSTCTL_CSFTRST) {
-@@ -2099,7 +2099,7 @@
+@@ -2099,7 +2099,7 @@ static int s3c_hsotg_corereset(struct s3
timeout = 10000;
while (1) {
@@ -1771,7 +1771,7 @@
if (timeout-- < 0) {
dev_info(hsotg->dev,
-@@ -2134,22 +2134,22 @@
+@@ -2134,22 +2134,22 @@ static void s3c_hsotg_core_init(struct s
*/
/* set the PLL on, remove the HNP/SRP and set the PHY */
@@ -1799,7 +1799,7 @@
GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
GINTSTS_ENUMDONE | GINTSTS_OTGINT |
-@@ -2157,11 +2157,11 @@
+@@ -2157,11 +2157,11 @@ static void s3c_hsotg_core_init(struct s
hsotg->regs + GINTMSK);
if (using_dma(hsotg))
@@ -1813,7 +1813,7 @@
GAHBCFG_P_TXF_EMP_LVL) : 0) |
GAHBCFG_GLBL_INTR_EN,
hsotg->regs + GAHBCFG);
-@@ -2172,7 +2172,7 @@
+@@ -2172,7 +2172,7 @@ static void s3c_hsotg_core_init(struct s
* interrupts.
*/
@@ -1822,7 +1822,7 @@
DIEPMSK_INTKNTXFEMPMSK : 0) |
DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
-@@ -2183,17 +2183,17 @@
+@@ -2183,17 +2183,17 @@ static void s3c_hsotg_core_init(struct s
* don't need XferCompl, we get that from RXFIFO in slave mode. In
* DMA mode we may need this.
*/
@@ -1844,7 +1844,7 @@
/* enable in and out endpoint interrupts */
s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
-@@ -2214,7 +2214,7 @@
+@@ -2214,7 +2214,7 @@ static void s3c_hsotg_core_init(struct s
udelay(10); /* see openiboot */
__bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
@@ -1853,7 +1853,7 @@
/*
* DxEPCTL_USBActEp says RO in manual, but seems to be set by
-@@ -2222,26 +2222,26 @@
+@@ -2222,26 +2222,26 @@ static void s3c_hsotg_core_init(struct s
*/
/* set to read 1 8byte packet */
@@ -1886,7 +1886,7 @@
hsotg->regs + DCTL);
/* must be at-least 3ms to allow bus to see disconnect */
-@@ -2265,8 +2265,8 @@
+@@ -2265,8 +2265,8 @@ static irqreturn_t s3c_hsotg_irq(int irq
spin_lock(&hsotg->lock);
irq_retry:
@@ -1897,7 +1897,7 @@
dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
__func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
-@@ -2274,35 +2274,35 @@
+@@ -2274,35 +2274,35 @@ irq_retry:
gintsts &= gintmsk;
if (gintsts & GINTSTS_OTGINT) {
@@ -1942,7 +1942,7 @@
u32 daint_out, daint_in;
int ep;
-@@ -2325,13 +2325,13 @@
+@@ -2325,13 +2325,13 @@ irq_retry:
if (gintsts & GINTSTS_USBRST) {
@@ -1959,7 +1959,7 @@
if (usb_status & GOTGCTL_BSESVLD) {
if (time_after(jiffies, hsotg->last_rst +
-@@ -2382,26 +2382,26 @@
+@@ -2382,26 +2382,26 @@ irq_retry:
if (gintsts & GINTSTS_MODEMIS) {
dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
@@ -1990,7 +1990,7 @@
}
/*
-@@ -2413,7 +2413,7 @@
+@@ -2413,7 +2413,7 @@ irq_retry:
if (gintsts & GINTSTS_GOUTNAKEFF) {
dev_info(hsotg->dev, "GOUTNakEff triggered\n");
@@ -1999,7 +1999,7 @@
s3c_hsotg_dump(hsotg);
}
-@@ -2421,7 +2421,7 @@
+@@ -2421,7 +2421,7 @@ irq_retry:
if (gintsts & GINTSTS_GINNAKEFF) {
dev_info(hsotg->dev, "GINNakEff triggered\n");
@@ -2008,7 +2008,7 @@
s3c_hsotg_dump(hsotg);
}
-@@ -2479,7 +2479,7 @@
+@@ -2479,7 +2479,7 @@ static int s3c_hsotg_ep_enable(struct us
/* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
@@ -2017,7 +2017,7 @@
dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
__func__, epctrl, epctrl_reg);
-@@ -2550,7 +2550,7 @@
+@@ -2550,7 +2550,7 @@ static int s3c_hsotg_ep_enable(struct us
for (i = 1; i <= 8; ++i) {
if (hsotg->fifo_map & (1<<i))
continue;
@@ -2026,7 +2026,7 @@
val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
if (val < size)
continue;
-@@ -2574,9 +2574,9 @@
+@@ -2574,9 +2574,9 @@ static int s3c_hsotg_ep_enable(struct us
dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
__func__, epctrl);
@@ -2038,7 +2038,7 @@
/* enable the endpoint interrupt */
s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
-@@ -2617,13 +2617,13 @@
+@@ -2617,13 +2617,13 @@ static int s3c_hsotg_ep_disable(struct u
hs_ep->fifo_index = 0;
hs_ep->fifo_size = 0;
@@ -2054,7 +2054,7 @@
/* disable endpoint interrupts */
s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
-@@ -2704,7 +2704,7 @@
+@@ -2704,7 +2704,7 @@ static int s3c_hsotg_ep_sethalt(struct u
/* write both IN and OUT control registers */
epreg = DIEPCTL(index);
@@ -2063,7 +2063,7 @@
if (value) {
epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
-@@ -2718,10 +2718,10 @@
+@@ -2718,10 +2718,10 @@ static int s3c_hsotg_ep_sethalt(struct u
epctl |= DXEPCTL_SETD0PID;
}
@@ -2076,7 +2076,7 @@
if (value)
epctl |= DXEPCTL_STALL;
-@@ -2733,7 +2733,7 @@
+@@ -2733,7 +2733,7 @@ static int s3c_hsotg_ep_sethalt(struct u
epctl |= DXEPCTL_SETD0PID;
}
@@ -2085,7 +2085,7 @@
hs_ep->halted = value;
-@@ -2822,38 +2822,38 @@
+@@ -2822,38 +2822,38 @@ static void s3c_hsotg_init(struct s3c_hs
{
/* unmask subset of endpoint interrupts */
@@ -2132,7 +2132,7 @@
hsotg->regs + GAHBCFG);
}
-@@ -3045,8 +3045,8 @@
+@@ -3045,8 +3045,8 @@ static void s3c_hsotg_initep(struct s3c_
if (using_dma(hsotg)) {
u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
@@ -2143,7 +2143,7 @@
}
}
-@@ -3061,13 +3061,13 @@
+@@ -3061,13 +3061,13 @@ static void s3c_hsotg_hw_cfg(struct s3c_
u32 cfg2, cfg3, cfg4;
/* check hardware configuration */
@@ -2160,7 +2160,7 @@
hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
-@@ -3089,19 +3089,19 @@
+@@ -3089,19 +3089,19 @@ static void s3c_hsotg_dump(struct s3c_hs
int idx;
dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
@@ -2185,7 +2185,7 @@
dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
val >> FIFOSIZE_DEPTH_SHIFT,
val & FIFOSIZE_STARTADDR_MASK);
-@@ -3110,21 +3110,21 @@
+@@ -3110,21 +3110,21 @@ static void s3c_hsotg_dump(struct s3c_hs
for (idx = 0; idx < 15; idx++) {
dev_info(dev,
"ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
@@ -2215,7 +2215,7 @@
#endif
}
-@@ -3144,38 +3144,38 @@
+@@ -3144,38 +3144,38 @@ static int state_show(struct seq_file *s
int idx;
seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
@@ -2268,7 +2268,7 @@
seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
in, out);
-@@ -3215,9 +3215,9 @@
+@@ -3215,9 +3215,9 @@ static int fifo_show(struct seq_file *se
int idx;
seq_puts(seq, "Non-periodic FIFOs:\n");
@@ -2280,7 +2280,7 @@
seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
val >> FIFOSIZE_DEPTH_SHIFT,
val & FIFOSIZE_DEPTH_MASK);
-@@ -3225,7 +3225,7 @@
+@@ -3225,7 +3225,7 @@ static int fifo_show(struct seq_file *se
seq_puts(seq, "\nPeriodic TXFIFOs:\n");
for (idx = 1; idx <= 15; idx++) {
@@ -2289,7 +2289,7 @@
seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
val >> FIFOSIZE_DEPTH_SHIFT,
-@@ -3278,20 +3278,20 @@
+@@ -3278,20 +3278,20 @@ static int ep_show(struct seq_file *seq,
/* first show the register state */
seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
@@ -2318,9 +2318,9 @@
seq_puts(seq, "\n");
seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
---- a/drivers/usb/dwc2/hcd.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/hcd.c 2015-02-09 19:34:42.911106076 +0200
-@@ -80,10 +80,10 @@
+--- a/drivers/usb/dwc2/hcd.c
++++ b/drivers/usb/dwc2/hcd.c
+@@ -80,10 +80,10 @@ static void dwc2_dump_channel_info(struc
if (chan == NULL)
return;
@@ -2335,7 +2335,7 @@
dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
-@@ -207,7 +207,7 @@
+@@ -207,7 +207,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *h
*/
hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_RST;
@@ -2344,7 +2344,7 @@
}
queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
-@@ -228,11 +228,11 @@
+@@ -228,11 +228,11 @@ static void dwc2_hcd_cleanup_channels(st
channel = hsotg->hc_ptr_array[i];
if (!list_empty(&channel->hc_list_entry))
continue;
@@ -2358,7 +2358,7 @@
}
}
}
-@@ -241,11 +241,11 @@
+@@ -241,11 +241,11 @@ static void dwc2_hcd_cleanup_channels(st
channel = hsotg->hc_ptr_array[i];
if (!list_empty(&channel->hc_list_entry))
continue;
@@ -2372,7 +2372,7 @@
}
dwc2_hc_cleanup(hsotg, channel);
-@@ -279,11 +279,11 @@
+@@ -279,11 +279,11 @@ void dwc2_hcd_disconnect(struct dwc2_hso
* interrupt mask and status bits and disabling subsequent host
* channel interrupts.
*/
@@ -2387,7 +2387,7 @@
/*
* Turn off the vbus power only if the core has transitioned to device
-@@ -293,7 +293,7 @@
+@@ -293,7 +293,7 @@ void dwc2_hcd_disconnect(struct dwc2_hso
if (dwc2_is_device_mode(hsotg)) {
if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
@@ -2396,7 +2396,7 @@
}
dwc2_disable_host_interrupts(hsotg);
-@@ -344,7 +344,7 @@
+@@ -344,7 +344,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hs
/* Turn off the vbus power */
dev_dbg(hsotg->dev, "PortPower off\n");
@@ -2405,7 +2405,7 @@
}
static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
-@@ -369,7 +369,7 @@
+@@ -369,7 +369,7 @@ static int dwc2_hcd_urb_enqueue(struct d
if ((dev_speed == USB_SPEED_LOW) &&
(hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
(hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
@@ -2414,7 +2414,7 @@
u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
if (prtspd == HPRT0_SPD_FULL_SPEED)
-@@ -391,7 +391,7 @@
+@@ -391,7 +391,7 @@ static int dwc2_hcd_urb_enqueue(struct d
return retval;
}
@@ -2423,7 +2423,7 @@
if (!(intr_mask & GINTSTS_SOF)) {
enum dwc2_transaction_type tr_type;
-@@ -1059,7 +1059,7 @@
+@@ -1059,7 +1059,7 @@ static void dwc2_process_periodic_channe
if (dbg_perio())
dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
@@ -2432,7 +2432,7 @@
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
-@@ -1074,7 +1074,7 @@
+@@ -1074,7 +1074,7 @@ static void dwc2_process_periodic_channe
qh_ptr = hsotg->periodic_sched_assigned.next;
while (qh_ptr != &hsotg->periodic_sched_assigned) {
@@ -2441,7 +2441,7 @@
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT;
if (qspcavail == 0) {
-@@ -1134,7 +1134,7 @@
+@@ -1134,7 +1134,7 @@ static void dwc2_process_periodic_channe
}
if (hsotg->core_params->dma_enable <= 0) {
@@ -2450,7 +2450,7 @@
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
-@@ -1157,9 +1157,9 @@
+@@ -1157,9 +1157,9 @@ static void dwc2_process_periodic_channe
* level to ensure that new requests are loaded as
* soon as possible.)
*/
@@ -2462,7 +2462,7 @@
} else {
/*
* Disable the Tx FIFO empty interrupt since there are
-@@ -1168,9 +1168,9 @@
+@@ -1168,9 +1168,9 @@ static void dwc2_process_periodic_channe
* handlers to queue more transactions as transfer
* states change.
*/
@@ -2474,7 +2474,7 @@
}
}
}
-@@ -1199,7 +1199,7 @@
+@@ -1199,7 +1199,7 @@ static void dwc2_process_non_periodic_ch
dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
@@ -2483,7 +2483,7 @@
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
-@@ -1222,7 +1222,7 @@
+@@ -1222,7 +1222,7 @@ static void dwc2_process_non_periodic_ch
* available in the request queue or the Tx FIFO
*/
do {
@@ -2492,7 +2492,7 @@
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT;
if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
-@@ -1259,7 +1259,7 @@
+@@ -1259,7 +1259,7 @@ next:
} while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
if (hsotg->core_params->dma_enable <= 0) {
@@ -2501,7 +2501,7 @@
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
TXSTS_QSPCAVAIL_SHIFT;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
-@@ -1279,9 +1279,9 @@
+@@ -1279,9 +1279,9 @@ next:
* level to ensure that new requests are loaded as
* soon as possible.)
*/
@@ -2513,7 +2513,7 @@
} else {
/*
* Disable the Tx FIFO empty interrupt since there are
-@@ -1290,9 +1290,9 @@
+@@ -1290,9 +1290,9 @@ next:
* handlers to queue more transactions as transfer
* states change.
*/
@@ -2525,7 +2525,7 @@
}
}
}
-@@ -1330,10 +1330,10 @@
+@@ -1330,10 +1330,10 @@ void dwc2_hcd_queue_transactions(struct
* Ensure NP Tx FIFO empty interrupt is disabled when
* there are no non-periodic transfers to process
*/
@@ -2538,7 +2538,7 @@
}
}
}
-@@ -1347,7 +1347,7 @@
+@@ -1347,7 +1347,7 @@ static void dwc2_conn_id_status_change(s
dev_dbg(hsotg->dev, "%s()\n", __func__);
@@ -2547,7 +2547,7 @@
dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
!!(gotgctl & GOTGCTL_CONID_B));
-@@ -1408,9 +1408,9 @@
+@@ -1408,9 +1408,9 @@ static void dwc2_wakeup_detected(unsigne
hprt0 = dwc2_read_hprt0(hsotg);
dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
hprt0 &= ~HPRT0_RES;
@@ -2559,7 +2559,7 @@
dwc2_hcd_rem_wakeup(hsotg);
-@@ -1438,30 +1438,30 @@
+@@ -1438,30 +1438,30 @@ static void dwc2_port_suspend(struct dwc
spin_lock_irqsave(&hsotg->lock, flags);
if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
@@ -2597,7 +2597,7 @@
spin_unlock_irqrestore(&hsotg->lock, flags);
-@@ -1510,23 +1510,23 @@
+@@ -1510,23 +1510,23 @@ static int dwc2_hcd_hub_control(struct d
"ClearPortFeature USB_PORT_FEAT_ENABLE\n");
hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_ENA;
@@ -2625,7 +2625,7 @@
break;
case USB_PORT_FEAT_POWER:
-@@ -1534,7 +1534,7 @@
+@@ -1534,7 +1534,7 @@ static int dwc2_hcd_hub_control(struct d
"ClearPortFeature USB_PORT_FEAT_POWER\n");
hprt0 = dwc2_read_hprt0(hsotg);
hprt0 &= ~HPRT0_PWR;
@@ -2634,7 +2634,7 @@
break;
case USB_PORT_FEAT_INDICATOR:
-@@ -1653,7 +1653,7 @@
+@@ -1653,7 +1653,7 @@ static int dwc2_hcd_hub_control(struct d
break;
}
@@ -2643,7 +2643,7 @@
dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
if (hprt0 & HPRT0_CONNSTS)
-@@ -1718,18 +1718,18 @@
+@@ -1718,18 +1718,18 @@ static int dwc2_hcd_hub_control(struct d
"SetPortFeature - USB_PORT_FEAT_POWER\n");
hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_PWR;
@@ -2666,7 +2666,7 @@
hprt0 = dwc2_read_hprt0(hsotg);
/* Clear suspend bit if resetting from suspend state */
-@@ -1744,13 +1744,13 @@
+@@ -1744,13 +1744,13 @@ static int dwc2_hcd_hub_control(struct d
hprt0 |= HPRT0_PWR | HPRT0_RST;
dev_dbg(hsotg->dev,
"In host mode, hprt0=%08x\n", hprt0);
@@ -2682,7 +2682,7 @@
hsotg->lx_state = DWC2_L0; /* Now back to On state */
break;
-@@ -1814,7 +1814,7 @@
+@@ -1814,7 +1814,7 @@ static int dwc2_hcd_is_status_changed(st
int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
{
@@ -2691,7 +2691,7 @@
#ifdef DWC2_DEBUG_SOF
dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
-@@ -1917,11 +1917,11 @@
+@@ -1917,11 +1917,11 @@ void dwc2_hcd_dump_state(struct dwc2_hso
if (chan->xfer_started) {
u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
@@ -2708,7 +2708,7 @@
dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
-@@ -1969,12 +1969,12 @@
+@@ -1969,12 +1969,12 @@ void dwc2_hcd_dump_state(struct dwc2_hso
dev_dbg(hsotg->dev, " periodic_channels: %d\n",
hsotg->periodic_channels);
dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
@@ -2723,7 +2723,7 @@
dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
(p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
-@@ -2238,7 +2238,7 @@
+@@ -2238,7 +2238,7 @@ static void dwc2_hcd_reset_func(struct w
dev_dbg(hsotg->dev, "USB RESET function called\n");
hprt0 = dwc2_read_hprt0(hsotg);
hprt0 &= ~HPRT0_RST;
@@ -2732,7 +2732,7 @@
hsotg->flags.b.port_reset_change = 1;
}
-@@ -2715,17 +2715,17 @@
+@@ -2715,17 +2715,17 @@ static void dwc2_hcd_free(struct dwc2_hs
hsotg->status_buf = NULL;
}
@@ -2755,7 +2755,7 @@
}
if (hsotg->wq_otg) {
-@@ -2788,7 +2788,7 @@
+@@ -2788,7 +2788,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
retval = -ENOMEM;
@@ -2764,9 +2764,9 @@
dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
---- a/drivers/usb/dwc2/hcd_ddma.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/hcd_ddma.c 2015-02-09 19:34:42.921106076 +0200
-@@ -169,19 +169,19 @@
+--- a/drivers/usb/dwc2/hcd_ddma.c
++++ b/drivers/usb/dwc2/hcd_ddma.c
+@@ -169,19 +169,19 @@ static void dwc2_per_sched_enable(struct
spin_lock_irqsave(&hsotg->lock, flags);
@@ -2789,7 +2789,7 @@
spin_unlock_irqrestore(&hsotg->lock, flags);
}
-@@ -193,7 +193,7 @@
+@@ -193,7 +193,7 @@ static void dwc2_per_sched_disable(struc
spin_lock_irqsave(&hsotg->lock, flags);
@@ -2798,7 +2798,7 @@
if (!(hcfg & HCFG_PERSCHEDENA)) {
/* already disabled */
spin_unlock_irqrestore(&hsotg->lock, flags);
-@@ -202,7 +202,7 @@
+@@ -202,7 +202,7 @@ static void dwc2_per_sched_disable(struc
hcfg &= ~HCFG_PERSCHEDENA;
dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
@@ -2807,9 +2807,9 @@
spin_unlock_irqrestore(&hsotg->lock, flags);
}
---- a/drivers/usb/dwc2/hcd.h 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/hcd.h 2015-02-09 19:34:42.949106077 +0200
-@@ -371,10 +371,10 @@
+--- a/drivers/usb/dwc2/hcd.h
++++ b/drivers/usb/dwc2/hcd.h
+@@ -371,10 +371,10 @@ static inline struct usb_hcd *dwc2_hsotg
*/
static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
{
@@ -2822,7 +2822,7 @@
}
/*
-@@ -382,11 +382,11 @@
+@@ -382,11 +382,11 @@ static inline void disable_hc_int(struct
*/
static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
{
@@ -2836,7 +2836,7 @@
}
/*
-@@ -395,7 +395,7 @@
+@@ -395,7 +395,7 @@ static inline int dwc2_is_device_mode(st
*/
static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
{
@@ -2845,7 +2845,7 @@
hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
return hprt0;
-@@ -582,7 +582,7 @@
+@@ -582,7 +582,7 @@ static inline u16 dwc2_micro_frame_num(u
*/
static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
{
@@ -2854,7 +2854,7 @@
}
static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
-@@ -744,7 +744,7 @@
+@@ -744,7 +744,7 @@ do { \
qtd_list_entry); \
if (usb_pipeint(_qtd_->urb->pipe) && \
(_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \
@@ -2863,9 +2863,9 @@
switch (_hfnum_.b.frnum & 0x7) { \
case 7: \
(_hcd_)->hfnum_7_samples_##_letter_++; \
---- a/drivers/usb/dwc2/hcd_intr.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/hcd_intr.c 2015-02-09 19:34:42.935106077 +0200
-@@ -148,7 +148,7 @@
+--- a/drivers/usb/dwc2/hcd_intr.c
++++ b/drivers/usb/dwc2/hcd_intr.c
+@@ -148,7 +148,7 @@ static void dwc2_sof_intr(struct dwc2_hs
dwc2_hcd_queue_transactions(hsotg, tr_type);
/* Clear interrupt */
@@ -2874,7 +2874,7 @@
}
/*
-@@ -164,7 +164,7 @@
+@@ -164,7 +164,7 @@ static void dwc2_rx_fifo_level_intr(stru
if (dbg_perio())
dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
@@ -2883,7 +2883,7 @@
chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
chan = hsotg->hc_ptr_array[chnum];
if (!chan) {
-@@ -247,11 +247,11 @@
+@@ -247,11 +247,11 @@ static void dwc2_hprt0_enable(struct dwc
dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
/* Every time when port enables calculate HFIR.FrInterval */
@@ -2897,7 +2897,7 @@
/* Check if we need to adjust the PHY clock speed for low power */
if (!params->host_support_fs_ls_low_power) {
-@@ -260,7 +260,7 @@
+@@ -260,7 +260,7 @@ static void dwc2_hprt0_enable(struct dwc
return;
}
@@ -2906,7 +2906,7 @@
prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
-@@ -268,11 +268,11 @@
+@@ -268,11 +268,11 @@ static void dwc2_hprt0_enable(struct dwc
if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
/* Set PHY low power clock select for FS/LS devices */
usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
@@ -2920,7 +2920,7 @@
fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
HCFG_FSLSPCLKSEL_SHIFT;
-@@ -286,7 +286,7 @@
+@@ -286,7 +286,7 @@ static void dwc2_hprt0_enable(struct dwc
fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
@@ -2929,7 +2929,7 @@
do_reset = 1;
}
} else {
-@@ -297,7 +297,7 @@
+@@ -297,7 +297,7 @@ static void dwc2_hprt0_enable(struct dwc
fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
@@ -2938,7 +2938,7 @@
do_reset = 1;
}
}
-@@ -305,7 +305,7 @@
+@@ -305,7 +305,7 @@ static void dwc2_hprt0_enable(struct dwc
/* Not low power */
if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
@@ -2947,7 +2947,7 @@
do_reset = 1;
}
}
-@@ -332,7 +332,7 @@
+@@ -332,7 +332,7 @@ static void dwc2_port_intr(struct dwc2_h
dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
@@ -2956,7 +2956,7 @@
hprt0_modify = hprt0;
/*
-@@ -385,7 +385,7 @@
+@@ -385,7 +385,7 @@ static void dwc2_port_intr(struct dwc2_h
}
/* Clear Port Interrupts */
@@ -2965,7 +2965,7 @@
}
/*
-@@ -405,7 +405,7 @@
+@@ -405,7 +405,7 @@ static u32 dwc2_get_actual_xfer_length(s
{
u32 hctsiz, count, length;
@@ -2974,7 +2974,7 @@
if (halt_status == DWC2_HC_XFER_COMPLETE) {
if (chan->ep_is_in) {
-@@ -483,7 +483,7 @@
+@@ -483,7 +483,7 @@ static int dwc2_update_urb_state(struct
urb->status = 0;
}
@@ -2983,7 +2983,7 @@
dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
__func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
-@@ -506,7 +506,7 @@
+@@ -506,7 +506,7 @@ void dwc2_hcd_save_data_toggle(struct dw
struct dwc2_host_chan *chan, int chnum,
struct dwc2_qtd *qtd)
{
@@ -2992,7 +2992,7 @@
u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
-@@ -753,9 +753,9 @@
+@@ -753,9 +753,9 @@ cleanup:
}
}
@@ -3004,7 +3004,7 @@
/* Try to queue more transfers now that there's a free channel */
tr_type = dwc2_hcd_select_transactions(hsotg);
-@@ -802,9 +802,9 @@
+@@ -802,9 +802,9 @@ static void dwc2_halt_channel(struct dwc
* is enabled so that the non-periodic schedule will
* be processed
*/
@@ -3016,7 +3016,7 @@
} else {
dev_vdbg(hsotg->dev, "isoc/intr\n");
/*
-@@ -821,9 +821,9 @@
+@@ -821,9 +821,9 @@ static void dwc2_halt_channel(struct dwc
* enabled so that the periodic schedule will be
* processed
*/
@@ -3028,7 +3028,7 @@
}
}
}
-@@ -888,7 +888,7 @@
+@@ -888,7 +888,7 @@ static void dwc2_complete_periodic_xfer(
struct dwc2_qtd *qtd,
enum dwc2_halt_status halt_status)
{
@@ -3037,7 +3037,7 @@
qtd->error_count = 0;
-@@ -1158,7 +1158,7 @@
+@@ -1158,7 +1158,7 @@ static void dwc2_update_urb_state_abn(st
urb->actual_length += xfer_length;
@@ -3046,7 +3046,7 @@
dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
__func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
-@@ -1469,10 +1469,10 @@
+@@ -1469,10 +1469,10 @@ static void dwc2_hc_ahberr_intr(struct d
dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
@@ -3061,7 +3061,7 @@
dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
-@@ -1685,10 +1685,10 @@
+@@ -1685,10 +1685,10 @@ static bool dwc2_halt_status_ok(struct d
* This code is here only as a check. This condition should
* never happen. Ignore the halt if it does occur.
*/
@@ -3076,7 +3076,7 @@
dev_dbg(hsotg->dev,
"%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
__func__);
-@@ -1712,7 +1712,7 @@
+@@ -1712,7 +1712,7 @@ static bool dwc2_halt_status_ok(struct d
* when the halt interrupt occurs. Halt the channel again if it does
* occur.
*/
@@ -3085,7 +3085,7 @@
if (hcchar & HCCHAR_CHDIS) {
dev_warn(hsotg->dev,
"%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
-@@ -1772,7 +1772,7 @@
+@@ -1772,7 +1772,7 @@ static void dwc2_hc_chhltd_intr_dma(stru
return;
}
@@ -3094,7 +3094,7 @@
if (chan->hcint & HCINTMSK_XFERCOMPL) {
/*
-@@ -1867,7 +1867,7 @@
+@@ -1867,7 +1867,7 @@ static void dwc2_hc_chhltd_intr_dma(stru
dev_err(hsotg->dev,
"hcint 0x%08x, intsts 0x%08x\n",
chan->hcint,
@@ -3103,7 +3103,7 @@
goto error;
}
}
-@@ -1922,11 +1922,11 @@
+@@ -1922,11 +1922,11 @@ static void dwc2_hc_n_intr(struct dwc2_h
chan = hsotg->hc_ptr_array[chnum];
@@ -3118,7 +3118,7 @@
return;
}
-@@ -1938,7 +1938,7 @@
+@@ -1938,7 +1938,7 @@ static void dwc2_hc_n_intr(struct dwc2_h
hcint, hcintmsk, hcint & hcintmsk);
}
@@ -3127,7 +3127,7 @@
chan->hcint = hcint;
hcint &= hcintmsk;
-@@ -2030,7 +2030,7 @@
+@@ -2030,7 +2030,7 @@ static void dwc2_hc_intr(struct dwc2_hso
u32 haint;
int i;
@@ -3136,7 +3136,7 @@
if (dbg_perio()) {
dev_vdbg(hsotg->dev, "%s()\n", __func__);
-@@ -2098,8 +2098,8 @@
+@@ -2098,8 +2098,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct
"DWC OTG HCD Finished Servicing Interrupts\n");
dev_vdbg(hsotg->dev,
"DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
@@ -3147,9 +3147,9 @@
}
}
---- a/drivers/usb/dwc2/hcd_queue.c 2015-02-06 16:53:48.000000000 +0200
-+++ b/drivers/usb/dwc2/hcd_queue.c 2015-02-09 19:34:42.941106077 +0200
-@@ -115,7 +115,7 @@
+--- a/drivers/usb/dwc2/hcd_queue.c
++++ b/drivers/usb/dwc2/hcd_queue.c
+@@ -115,7 +115,7 @@ static void dwc2_qh_init(struct dwc2_hso
if (qh->ep_type == USB_ENDPOINT_XFER_INT)
qh->interval = 8;
#endif
@@ -3158,7 +3158,7 @@
prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
if (prtspd == HPRT0_SPD_HIGH_SPEED &&
(dev_speed == USB_SPEED_LOW ||
-@@ -593,9 +593,9 @@
+@@ -593,9 +593,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *h
if (status)
return status;
if (!hsotg->periodic_qh_count) {
@@ -3170,7 +3170,7 @@
}
hsotg->periodic_qh_count++;
-@@ -630,9 +630,9 @@
+@@ -630,9 +630,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsot
dwc2_deschedule_periodic(hsotg, qh);
hsotg->periodic_qh_count--;
if (!hsotg->periodic_qh_count) {
diff --git a/target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch
index f276d7bfc0..c09323104d 100644
--- a/target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch
+++ b/target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch
@@ -8,7 +8,7 @@
#include <linux/of.h>
#include <lantiq_soc.h>
-@@ -38,10 +39,12 @@
+@@ -38,10 +39,12 @@ enum {
LTQ_NOR_NORMAL
};
@@ -24,7 +24,7 @@
};
static const char ltq_map_name[] = "ltq_nor";
-@@ -109,12 +112,44 @@
+@@ -109,12 +112,44 @@ ltq_copy_to(struct map_info *map, unsign
}
static int
@@ -70,7 +70,7 @@
if (of_machine_is_compatible("lantiq,falcon") &&
(ltq_boot_select() != BS_FLASH)) {
-@@ -128,76 +163,88 @@
+@@ -128,76 +163,88 @@ ltq_mtd_probe(struct platform_device *pd
platform_set_drvdata(pdev, ltq_mtd);
diff --git a/target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
index fdd065d6fb..d153c521d3 100644
--- a/target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
+++ b/target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
@@ -1,6 +1,6 @@
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
-@@ -40,7 +40,7 @@
+@@ -39,7 +39,7 @@
/* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
// debugging, turns off buffer write mode if set to 1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 11:00:49 +0000