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author | Mathias Kresin <dev@kresin.me> | 2020-03-01 08:09:19 +0100 |
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committer | Mathias Kresin <dev@kresin.me> | 2020-03-16 22:28:16 +0100 |
commit | 005dedd3480f47ff1049e132ec8d83bc0e24fbef (patch) | |
tree | 56fdc5bdf6c715d63fc5acb963eab4e747747920 /target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch | |
parent | 0dbe8b9029df1c1b254101bacbc20c3418eb956f (diff) | |
download | upstream-005dedd3480f47ff1049e132ec8d83bc0e24fbef.tar.gz upstream-005dedd3480f47ff1049e132ec8d83bc0e24fbef.tar.bz2 upstream-005dedd3480f47ff1049e132ec8d83bc0e24fbef.zip |
lantiq: copy target to kernel 5.4
Duplicate kernel 4.19 config and patches for kernel 5.4.
Duplicate the devicetree source files as well, they need kernel 5.4
specific adjustments.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch')
-rw-r--r-- | target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..b98abe8b4b --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -424,6 +424,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -587,4 +601,6 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } + usb_set_clock(); ++ ++ set_phy_clock_source(np_cgu); + } |