lantiq: add Linux 5.4 support as testing kernel version

Switch to the mainline Lantiq PCIe PHY driver and update the vr9.dtsi
accordingly.

The Lantiq IRQ SMP support added upstream required changes to the SoC
dtsi as well.

Following changes are made to the Lantiq kernel patches:

  0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch
  0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch
    applied upstream

  0008-MIPS-lantiq-backport-old-timer-code.patch
    access_ok API update because it lost it's type (which was the first)
    parameter in upstream commit 96d4f267e40f95 ("Remove 'type' argument
    from access_ok() function")

  0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch
    merged into 0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch

  0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
    revert upstream changes required for upstream xrx200 ethernet and
    xrx200 (DSA) switch driver but breaking our driver

  0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
    required for our driver but dropped upstream, add former upstream
    version

  0028-NET-lantiq-various-etop-fixes.patch
    now has to use the phy_set_max_speed API instead of modifying
    phydev->supported. Also call ltq_dma_enable_irq() in
    ltq_etop_open() based on upstream commit cc973aecf0b054 ("MIPS:
    lantiq: Do not enable IRQs in dma open")

Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

1 files changed, 206 insertions, 10 deletions

diff --git a/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch
index b081871191..bc02a58b1c 100644
--- a/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch
+++ b/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -1,7 +1,13 @@
 --- a/arch/mips/pci/ifxmips_pcie.c
 +++ b/arch/mips/pci/ifxmips_pcie.c
-@@ -18,6 +18,9 @@
+@@ -16,8 +16,15 @@
+ #include <asm/paccess.h>
+ #include <linux/pci.h>
  #include <linux/pci_regs.h>
++#include <linux/phy/phy.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/mfd/syscon.h>
  #include <linux/module.h>
  
 +#include <linux/of_gpio.h>
@@ -10,15 +16,18 @@
  #include "ifxmips_pcie.h"
  #include "ifxmips_pcie_reg.h"
  
-@@ -40,6 +43,7 @@
+@@ -40,6 +47,10 @@
  static DEFINE_SPINLOCK(ifx_pcie_lock);
  
  u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
 +static int pcie_reset_gpio;
++static struct phy *ltq_pcie_phy;
++static struct reset_control *ltq_pcie_reset;
++static struct regmap *ltq_rcu_regmap;
  
  static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
      {
-@@ -82,6 +86,22 @@ void ifx_pcie_debug(const char *fmt, ...
+@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...
  	printk("%s", buf);
  }
  
@@ -41,7 +50,80 @@
  
  static inline int pcie_ltssm_enable(int pcie_port)
  {
-@@ -1045,17 +1065,52 @@ pcie_rc_initialize(int pcie_port)
+@@ -988,10 +1015,22 @@ int  ifx_pcie_bios_plat_dev_init(struct
+ static int
+ pcie_rc_initialize(int pcie_port)
+ {
+-	int i;
++	int i, ret;
+ #define IFX_PCIE_PHY_LOOP_CNT  5
+ 
+-	pcie_rcu_endian_setup(pcie_port);
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M,
++			   IFX_RCU_AHB_BE_PCIE_M);
++
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   IFX_RCU_AHB_BE_PCIE_S);
++#else
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   0x0);
++#endif
++
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M,
++			   0x0);
+ 
+ 	pcie_ep_gpio_rst_init(pcie_port);
+ 
+@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)
+ 	* reset PCIe PHY will solve this issue 
+ 	*/
+ 	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
+-		/* Disable PCIe PHY Analog part for sanity check */
+-		pcie_phy_pmu_disable(pcie_port);
+-
+-		pcie_phy_rst_assert(pcie_port);
+-		pcie_phy_rst_deassert(pcie_port);
+-
+-		/* Make sure PHY PLL is stable */
+-		udelay(20);
+-
+-		/* PCIe Core reset enabled, low active, sw programmed */
+-		pcie_core_rst_assert(pcie_port);
++		ret = phy_init(ltq_pcie_phy);
++		if (ret)
++			continue;
+ 
+ 		/* Put PCIe EP in reset status */
+ 		pcie_device_rst_assert(pcie_port);
+ 
+-		/* PCI PHY & Core reset disabled, high active, sw programmed */
+-		pcie_core_rst_deassert(pcie_port);
++		udelay(1);
++		reset_control_deassert(ltq_pcie_reset);
+ 
+-		/* Already in a quiet state, program PLL, enable PHY, check ready bit */
+-		pcie_phy_clock_mode_setup(pcie_port);
++		ret = phy_power_on(ltq_pcie_phy);
++		if (ret) {
++			phy_exit(ltq_pcie_phy);
++			continue;
++		}
+ 
+ 		/* Enable PCIe PHY and Clock */
+ 		pcie_core_pmu_setup(pcie_port);
+@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)
+ 		/* Once link is up, break out */
+ 		if (pcie_app_loigc_setup(pcie_port) == 0)
+ 			break;
++
++		phy_power_off(ltq_pcie_phy);
++		reset_control_assert(ltq_pcie_reset);
++		phy_exit(ltq_pcie_phy);
+ 	}
+ 	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
+ 		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
+@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)
  	return 0;
  }
  
@@ -52,7 +134,6 @@
      void __iomem *io_map_base;
      int pcie_port;
      int startup_port;
- 
 +    struct device_node *np;
 +    struct pci_bus *bus;
 +
@@ -76,13 +157,29 @@
 +        if (!bus)
 +	     return -EPROBE_DEFER;
 +    }
-+
+ 
      /* Enable AHB Master/ Slave */
      pcie_ahb_pmu_setup();
  
      startup_port = IFX_PCIE_PORT0;
 -    
 +
++    ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
++    if (IS_ERR(ltq_pcie_phy)) {
++        dev_err(&pdev->dev, "failed to get the PCIe PHY\n");
++        return PTR_ERR(ltq_pcie_phy);
++    }
++
++    ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
++    if (IS_ERR(ltq_pcie_reset)) {
++        dev_err(&pdev->dev, "failed to get the PCIe reset line\n");
++        return PTR_ERR(ltq_pcie_reset);
++    }
++
++    ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
++    if (IS_ERR(ltq_rcu_regmap))
++        return PTR_ERR(ltq_rcu_regmap);
++
 +    pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
 +    if (gpio_is_valid(pcie_reset_gpio)) {
 +        int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
@@ -96,7 +193,7 @@
      for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
  	if (pcie_rc_initialize(pcie_port) == 0) {
  	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
-@@ -1067,6 +1122,7 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi
                  return -ENOMEM;
              }
              ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
@@ -104,7 +201,7 @@
  
              register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
              /* XXX, clear error status */
-@@ -1083,6 +1139,30 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi
  
      return 0;
  }
@@ -168,10 +265,98 @@
  static inline void pcie_ahb_pmu_setup(void) 
  {
  	/* Enable AHB bus master/slave */
-@@ -180,20 +163,6 @@ static inline void pcie_phy_rst_deassert
-     IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo
+     //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+ 
+-static inline void pcie_rcu_endian_setup(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-#ifdef CONFIG_IFX_PCIE_HW_SWAP
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg |= IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#else 
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#endif /* CONFIG_IFX_PCIE_HW_SWAP */
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
+-}
+-
+ static inline void pcie_phy_pmu_enable(int pcie_port)
+ {
+ 	struct clk *clk;
+@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable(
+ //    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
+ }
+ 
+-static inline void pcie_pdi_big_endian(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* SRAM2PDI endianness control. */
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-    /* Config AHB->PCIe and PDI endianness */
+-    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-}
+-
+ static inline void pcie_pdi_pmu_enable(int pcie_port)
+ {
+     /* Enable PDI to access PCIe PHY register */
+@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i
+     //PDI_PMU_SETUP(IFX_PMU_ENABLE);
  }
  
+-static inline void pcie_core_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-
+-    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
+-    reg |= 0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_core_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    /* Reset PCIe PHY & Core, bit 22 */
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg |= 0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
 -static inline void pcie_device_rst_assert(int pcie_port)
 -{
 -	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
@@ -189,3 +374,14 @@
  static inline void pcie_core_pmu_setup(int pcie_port)
  {
  	struct clk *clk;
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -51,7 +51,7 @@ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
+-obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie.o fixup-lantiq-pcie.o
+ obj-$(CONFIG_PCIE_LANTIQ_MSI)	+= pcie-lantiq-msi.o
+ obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o