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author | Mathias Kresin <dev@kresin.me> | 2020-12-27 10:26:37 +0100 |
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committer | Mathias Kresin <dev@kresin.me> | 2021-04-12 23:23:09 +0200 |
commit | e44e454ee65bb0631fbea64ea1e30b40735ed97b (patch) | |
tree | 6581a14c92f5732db1d42bbe649c65ccdd4a30ee /target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch | |
parent | 276c85825c859f93d3f7ce501630af631e4d9e32 (diff) | |
download | upstream-e44e454ee65bb0631fbea64ea1e30b40735ed97b.tar.gz upstream-e44e454ee65bb0631fbea64ea1e30b40735ed97b.tar.bz2 upstream-e44e454ee65bb0631fbea64ea1e30b40735ed97b.zip |
lantiq: copy target to kernel 5.10
Duplicate kernel 5.4 config and patches for kernel 5.10.
Duplicate the devicetree source files as well, they need kernel 5.10
specific adjustments.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch')
-rw-r--r-- | target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..1beef0e1fe --- /dev/null +++ b/target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -422,6 +422,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -585,4 +599,6 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } + usb_set_clock(); ++ ++ set_phy_clock_source(np_cgu); + } |