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| author | Mathias Kresin <dev@kresin.me> | 2018-03-22 20:00:13 +0100 |
|---|---|---|
| committer | Mathias Kresin <dev@kresin.me> | 2018-03-23 20:31:49 +0100 |
| commit | af3a9566fe83dbfad6d587a4000b264d315d9374 (patch) | |
| tree | 090b69ff523e8736091fb74c658a6698aeb78ef2 /target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch | |
| parent | e3bf92edf5564cf72de8234b32364f0d4919524f (diff) | |
| download | upstream-af3a9566fe83dbfad6d587a4000b264d315d9374.tar.gz upstream-af3a9566fe83dbfad6d587a4000b264d315d9374.tar.bz2 upstream-af3a9566fe83dbfad6d587a4000b264d315d9374.zip | |
lantiq: intel-xway: add vr9 v1.1 phy support
During upstreaming the intel phy driver, support for the vr9 v1.1
embedded phys got lost. Backport the upstream send patch adding support
for the vr9 v1.1 embbeded phys to the driver.
Signed-off-by: Mathias Kresin <dev@kresin.me>
cosmetic fixes
Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch')
| -rw-r--r-- | target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch b/target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch new file mode 100644 index 0000000000..9a92532908 --- /dev/null +++ b/target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch @@ -0,0 +1,71 @@ +From f452518c982e57538e6d49da0a2c80eef22087ab Mon Sep 17 00:00:00 2001 +From: Mathias Kresin <dev@kresin.me> +Date: Thu, 22 Mar 2018 23:31:39 +0100 +Subject: [PATCH 2/2] net: phy: intel-xway: add VR9 v1.1 phy ids + +The phys embedded into the v1.1 of the VR9 SoC are using different phy +ids. Add the phy ids to use the driver for this VR9 version as well. + +Signed-off-by: Mathias Kresin <dev@kresin.me> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + drivers/net/phy/intel-xway.c | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/drivers/net/phy/intel-xway.c ++++ b/drivers/net/phy/intel-xway.c +@@ -149,6 +149,8 @@ + #define PHY_ID_PHY22F_1_4 0xD565A410 + #define PHY_ID_PHY11G_1_5 0xD565A401 + #define PHY_ID_PHY22F_1_5 0xD565A411 ++#define PHY_ID_PHY11G_VR9_1_1 0xD565A408 ++#define PHY_ID_PHY22F_VR9_1_1 0xD565A418 + #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 + #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 + +@@ -372,6 +374,36 @@ static struct phy_driver xway_gphy[] = { + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { ++ .phy_id = PHY_ID_PHY11G_VR9_1_1, ++ .phy_id_mask = 0xffffffff, ++ .name = "Intel XWAY PHY11G (xRX v1.1 integrated)", ++ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause), ++ .flags = PHY_HAS_INTERRUPT, ++ .config_init = xway_gphy_config_init, ++ .config_aneg = genphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = xway_gphy_ack_interrupt, ++ .did_interrupt = xway_gphy_did_interrupt, ++ .config_intr = xway_gphy_config_intr, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { ++ .phy_id = PHY_ID_PHY22F_VR9_1_1, ++ .phy_id_mask = 0xffffffff, ++ .name = "Intel XWAY PHY22F (xRX v1.1 integrated)", ++ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | ++ SUPPORTED_Asym_Pause), ++ .flags = PHY_HAS_INTERRUPT, ++ .config_init = xway_gphy_config_init, ++ .config_aneg = genphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = xway_gphy_ack_interrupt, ++ .did_interrupt = xway_gphy_did_interrupt, ++ .config_intr = xway_gphy_config_intr, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { + .phy_id = PHY_ID_PHY11G_VR9_1_2, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY11G (xRX v1.2 integrated)", +@@ -412,6 +444,8 @@ static struct mdio_device_id __maybe_unu + { PHY_ID_PHY22F_1_4, 0xffffffff }, + { PHY_ID_PHY11G_1_5, 0xffffffff }, + { PHY_ID_PHY22F_1_5, 0xffffffff }, ++ { PHY_ID_PHY11G_VR9_1_1, 0xffffffff }, ++ { PHY_ID_PHY22F_VR9_1_1, 0xffffffff }, + { PHY_ID_PHY11G_VR9_1_2, 0xffffffff }, + { PHY_ID_PHY22F_VR9_1_2, 0xffffffff }, + { } |