lantiq: update USB controller initialization

This adds USB initialization fixes for Danube, Amazon SE and xrx300 and
should fix the clock on at least Danube which hopefully closes FS#351.

The xrx200 usb driver now uses more memory for the dwc2 fifos, this was
increased in the chip compared to ar9.

This is based in part on the vendor documentation and the vendor code
base as a reference.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

1 files changed, 78 insertions, 0 deletions

diff --git a/target/linux/lantiq/patches-4.4/0060-usb-dwc2-Add-support-for-Lantiq-ARX-and-XRX-SoCs.patch b/target/linux/lantiq/patches-4.4/0060-usb-dwc2-Add-support-for-Lantiq-ARX-and-XRX-SoCs.patch
new file mode 100644
index 0000000000..91d6ac92e7
--- /dev/null
+++ b/target/linux/lantiq/patches-4.4/0060-usb-dwc2-Add-support-for-Lantiq-ARX-and-XRX-SoCs.patch
@@ -0,0 +1,78 @@
+From 6c0c0951bbf8c2c216675fe277fba4c42aa0a2bf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Antti=20Sepp=C3=A4l=C3=A4?= <a.seppala@gmail.com>
+Date: Sat, 27 Feb 2016 12:31:24 +0200
+Subject: [PATCH] usb: dwc2: Add support for Lantiq ARX and XRX SoCs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add support for Lantiq ARX and XRX SoC families to the dwc2 driver.
+
+Acked-by: John Youn <johnyoun@synopsys.com>
+Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
+Signed-off-by: Felipe Balbi <balbi@kernel.org>
+---
+ Documentation/devicetree/bindings/usb/dwc2.txt |  2 ++
+ drivers/usb/dwc2/platform.c                    | 34 ++++++++++++++++++++++++++
+ 2 files changed, 36 insertions(+)
+
+--- a/Documentation/devicetree/bindings/usb/dwc2.txt
++++ b/Documentation/devicetree/bindings/usb/dwc2.txt
+@@ -7,6 +7,8 @@ Required properties:
+   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+   - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
+   - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
++  - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
++  - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
+   - snps,dwc2: A generic DWC2 USB controller with default parameters.
+ - reg : Should contain 1 register range (address and length)
+ - interrupts : Should contain 1 interrupt
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -116,6 +116,37 @@ static const struct dwc2_core_params par
+ 	.hibernation			= -1,
+ };
+ 
++static const struct dwc2_core_params params_ltq = {
++	.otg_cap			= 2,	/* non-HNP/non-SRP */
++	.otg_ver			= -1,
++	.dma_enable			= -1,
++	.dma_desc_enable		= -1,
++	.speed				= -1,
++	.enable_dynamic_fifo		= -1,
++	.en_multiple_tx_fifo		= -1,
++	.host_rx_fifo_size		= 288,	/* 288 DWORDs */
++	.host_nperio_tx_fifo_size	= 128,	/* 128 DWORDs */
++	.host_perio_tx_fifo_size	= 96,	/* 96 DWORDs */
++	.max_transfer_size		= 65535,
++	.max_packet_count		= 511,
++	.host_channels			= -1,
++	.phy_type			= -1,
++	.phy_utmi_width			= -1,
++	.phy_ulpi_ddr			= -1,
++	.phy_ulpi_ext_vbus		= -1,
++	.i2c_enable			= -1,
++	.ulpi_fs_ls			= -1,
++	.host_support_fs_ls_low_power	= -1,
++	.host_ls_low_power_phy_clk	= -1,
++	.ts_dline			= -1,
++	.reload_ctl			= -1,
++	.ahbcfg				= GAHBCFG_HBSTLEN_INCR16 <<
++					  GAHBCFG_HBSTLEN_SHIFT,
++	.uframe_sched			= -1,
++	.external_id_pin_ctl		= -1,
++	.hibernation			= -1,
++};
++
+ static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
+ {
+ 	struct platform_device *pdev = to_platform_device(hsotg->dev);
+@@ -310,6 +341,8 @@ static int dwc2_driver_remove(struct pla
+ static const struct of_device_id dwc2_of_match_table[] = {
+ 	{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
+ 	{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
++	{ .compatible = "lantiq,arx100-usb", .data = &params_ltq },
++	{ .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
+ 	{ .compatible = "snps,dwc2", .data = NULL },
+ 	{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
+ 	{},