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| author | John Crispin <john@openwrt.org> | 2012-12-15 01:59:45 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2012-12-15 01:59:45 +0000 |
| commit | 3a948770cf46732ba4e2ebe667efc3be164780e3 (patch) | |
| tree | a332a0212fc1d8831ea73fa20841bd252c468916 /target/linux/lantiq/patches-3.7/0112-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch | |
| parent | 240a3a38e1711857921d31b73a81a4ef9e8a3117 (diff) | |
| download | upstream-3a948770cf46732ba4e2ebe667efc3be164780e3.tar.gz upstream-3a948770cf46732ba4e2ebe667efc3be164780e3.tar.bz2 upstream-3a948770cf46732ba4e2ebe667efc3be164780e3.zip | |
add linux-v3.7
SVN-Revision: 34687
Diffstat (limited to 'target/linux/lantiq/patches-3.7/0112-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.7/0112-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.7/0112-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch b/target/linux/lantiq/patches-3.7/0112-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch new file mode 100644 index 0000000000..447c0615c0 --- /dev/null +++ b/target/linux/lantiq/patches-3.7/0112-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch @@ -0,0 +1,47 @@ +From d8d9b9055d704d6f84ef6346d6826b8a9640f209 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 22 Oct 2012 10:25:39 +0200 +Subject: [PATCH 112/123] MTD: lantiq: xway: fix NAND reset timeout handling + +Fixes a possible deadlock in the code that resets the NAND flash. + +http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/mtd/nand/xway_nand.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c +index 3f81dc8..4731300 100644 +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -58,15 +58,23 @@ static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; + unsigned long flags; ++ unsigned long timeout; + + nandaddr &= ~NAND_WRITE_ADDR; + nandaddr |= NAND_WRITE_CMD; + + /* finish with a reset */ ++ timeout = jiffies + msecs_to_jiffies(200); ++ + spin_lock_irqsave(&ebu_lock, flags); ++ + writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr); +- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) +- ; ++ do { ++ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) ++ break; ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ + spin_unlock_irqrestore(&ebu_lock, flags); + } + +-- +1.7.10.4 + |