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| author | John Crispin <blogic@openwrt.org> | 2015-06-05 14:11:51 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2015-06-05 14:11:51 +0000 |
| commit | 2a0f4f1f4ea30e65205fdeb244e5aa0c3dd8ac77 (patch) | |
| tree | 76b14d1b726ac9f08952f30ecf9e65c6992eadf2 /target/linux/lantiq/patches-3.18 | |
| parent | da88531354ada83ca9b04175bd05722f826a44f4 (diff) | |
| download | upstream-2a0f4f1f4ea30e65205fdeb244e5aa0c3dd8ac77.tar.gz upstream-2a0f4f1f4ea30e65205fdeb244e5aa0c3dd8ac77.tar.bz2 upstream-2a0f4f1f4ea30e65205fdeb244e5aa0c3dd8ac77.zip | |
lantiq: Backport gpio-stp-xway to fix the highest bits of the PHY LEDs
This fixes the LAN2 LED on Arcadyan VGV7510KW22.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45899 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/patches-3.18')
| -rw-r--r-- | target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch new file mode 100644 index 0000000000..967045db02 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch @@ -0,0 +1,25 @@ +From 08b085a07efe12568d86dff064e6f089e2971744 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Date: Mon, 25 May 2015 22:39:50 +0200 +Subject: gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs + +0x3 only masks two bits, but three bits have to be allowed. This fixes +GPHY0 LED2 (which is the highest bit of phy2) on my board. + +Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Acked-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> + +diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c +index 202361e..6d4148f 100644 +--- a/drivers/gpio/gpio-stp-xway.c ++++ b/drivers/gpio/gpio-stp-xway.c +@@ -58,7 +58,7 @@ + #define XWAY_STP_ADSL_MASK 0x3 + + /* 2 groups of 3 bits can be driven by the phys */ +-#define XWAY_STP_PHY_MASK 0x3 ++#define XWAY_STP_PHY_MASK 0x7 + #define XWAY_STP_PHY1_SHIFT 27 + #define XWAY_STP_PHY2_SHIFT 15 + |