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authorJohn Crispin <john@openwrt.org>2015-02-14 20:48:32 +0000
committerJohn Crispin <john@openwrt.org>2015-02-14 20:48:32 +0000
commite07c4f21506e33c5467aafeb4dbd11d9ad87201b (patch)
tree097dbc2e8e770b6e83da024bb77dd5ca17ebcdd9 /target/linux/lantiq/patches-3.14
parenta15dd8ec78ca8acbec00f5535538961f0ec23f71 (diff)
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lantiq: disable buffered writes on Intel command set flash
Some Lantiq SoCs are not able to use buffered writes properly with Intel command set flash due to the way NOR addresses on EBU are manipulated. This patch disables buffered writes on those devices. The only device affected at the moment is ARV4510PW, others use AMD/Fujitsu command set. Signed-off-by: Matti Laakso <malaakso@elisanet.fi> SVN-Revision: 44451
Diffstat (limited to 'target/linux/lantiq/patches-3.14')
-rw-r--r--target/linux/lantiq/patches-3.14/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch11
1 files changed, 11 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.14/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-3.14/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
new file mode 100644
index 0000000000..fdd065d6fb
--- /dev/null
+++ b/target/linux/lantiq/patches-3.14/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
@@ -0,0 +1,11 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -40,7 +40,7 @@
+ /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
+
+ // debugging, turns off buffer write mode if set to 1
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+
+ /* Intel chips */
+ #define I82802AB 0x00ad