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author | John Crispin <blogic@openwrt.org> | 2012-11-02 20:07:02 +0000 |
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committer | John Crispin <blogic@openwrt.org> | 2012-11-02 20:07:02 +0000 |
commit | 5a5e4b27825721f902e64a0d993d71a6b8fd48a4 (patch) | |
tree | 9042a707f9a1efd86b4873f9ad1e0116e209f93c /target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h | |
parent | bd7dc4e3eae386a0d79e7586ea73ebd6feb74ef0 (diff) | |
download | upstream-5a5e4b27825721f902e64a0d993d71a6b8fd48a4.tar.gz upstream-5a5e4b27825721f902e64a0d993d71a6b8fd48a4.tar.bz2 upstream-5a5e4b27825721f902e64a0d993d71a6b8fd48a4.zip |
[lantiq] move files/ -> files-3.3/
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34060 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h')
-rw-r--r-- | target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h deleted file mode 100644 index b0298ec2ea..0000000000 --- a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : dwc_otg_cil_ifx.h -** PROJECT : Twinpass/Danube -** MODULES : DWC OTG USB -** -** DATE : 07 Sep. 2007 -** AUTHOR : Sung Winder -** DESCRIPTION : Default param value. -** COPYRIGHT : Copyright (c) 2007 -** Infineon Technologies AG -** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, -** Hsin-chu City, 300 Taiwan. -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 12 April 2007 Sung Winder Initiate Version -*******************************************************************************/ -#if !defined(__DWC_OTG_CIL_IFX_H__) -#define __DWC_OTG_CIL_IFX_H__ - -/* ================ Default param value ================== */ -#define dwc_param_opt_default 1 -#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE -#define dwc_param_dma_enable_default 1 -#define dwc_param_dma_burst_size_default 32 -#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH -#define dwc_param_host_support_fs_ls_low_power_default 0 -#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ -#define dwc_param_enable_dynamic_fifo_default 1 -#define dwc_param_data_fifo_size_default 2048 -#define dwc_param_dev_rx_fifo_size_default 1024 -#define dwc_param_dev_nperio_tx_fifo_size_default 1024 -#define dwc_param_dev_perio_tx_fifo_size_default 768 -#define dwc_param_host_rx_fifo_size_default 640 -#define dwc_param_host_nperio_tx_fifo_size_default 640 -#define dwc_param_host_perio_tx_fifo_size_default 768 -#define dwc_param_max_transfer_size_default 65535 -#define dwc_param_max_packet_count_default 511 -#define dwc_param_host_channels_default 16 -#define dwc_param_dev_endpoints_default 6 -#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI -#define dwc_param_phy_utmi_width_default 16 -#define dwc_param_phy_ulpi_ddr_default 0 -#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS -#define dwc_param_i2c_enable_default 0 -#define dwc_param_ulpi_fs_ls_default 0 -#define dwc_param_ts_dline_default 0 - -/* ======================================================= */ - -#endif // __DWC_OTG_CIL_IFX_H__ - |