strip the kernel version suffix from target directories, except for brcm-2.4 (the -2.4 will be included in the board name here). CONFIG_LINUX_<ver>_<board> becomes CONFIG_TARGET_<board>, same for profiles.

SVN-Revision: 8653

38 files changed, 10107 insertions, 0 deletions

diff --git a/target/linux/ixp4xx/patches/050-dsmg600_upstream_support.patch b/target/linux/ixp4xx/patches/050-dsmg600_upstream_support.patch
new file mode 100644
index 0000000000..b214ef2b5f
--- /dev/null
+++ b/target/linux/ixp4xx/patches/050-dsmg600_upstream_support.patch
@@ -0,0 +1,551 @@
+This patch adds support for the D-Link DSM-G600 Rev A.
+This is an ARM XScale IXP4xx system relatively similar to
+the NSLU2 and NAS-100D already supported by mainline. An
+important difference is Gigabit Ethernet support using
+the Via Velocity chipset.
+
+This patch is the combined work of Michael Westerhof and
+Alessandro Zummo, with contributions from Michael-Luke
+Jones. This version addresses review comments from rmk
+and Deepak Saxena.
+
+Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
+Signed-off-by: Alessandro Zummo <a.zummo@towertech.it>
+Signed-off-by: Michael Westerhof <mwester@dls.net>
+
+---
+ arch/arm/mach-ixp4xx/Kconfig           |    9 +
+ arch/arm/mach-ixp4xx/Makefile          |    2 
+ arch/arm/mach-ixp4xx/dsmg600-pci.c     |   74 +++++++++++++
+ arch/arm/mach-ixp4xx/dsmg600-power.c   |  130 ++++++++++++++++++++++++
+ arch/arm/mach-ixp4xx/dsmg600-setup.c   |  175 +++++++++++++++++++++++++++++++++
+ include/asm-arm/arch-ixp4xx/dsmg600.h  |   57 ++++++++++
+ include/asm-arm/arch-ixp4xx/hardware.h |    1 
+ include/asm-arm/arch-ixp4xx/irqs.h     |   10 +
+ 8 files changed, 458 insertions(+)
+
+Index: linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/Kconfig
+===================================================================
+--- linux-2.6.21.1-armeb.orig/arch/arm/mach-ixp4xx/Kconfig
++++ linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/Kconfig
+@@ -89,6 +89,15 @@
+ 	  NAS 100d device. For more information on this platform,
+ 	  see http://www.nslu2-linux.org/wiki/NAS100d/HomePage
+ 
++config MACH_DSMG600
++	bool
++	prompt "D-Link DSM-G600 RevA"
++	select PCI
++	help
++	  Say 'Y' here if you want your kernel to support D-Link's
++	  DSM-G600 RevA device. For more information on this platform,
++	  see http://www.nslu2-linux.org/wiki/DSMG600/HomePage
++
+ #
+ # Avila and IXDP share the same source for now. Will change in future
+ #
+Index: linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/Makefile
+===================================================================
+--- linux-2.6.21.1-armeb.orig/arch/arm/mach-ixp4xx/Makefile
++++ linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/Makefile
+@@ -12,6 +12,7 @@
+ obj-pci-$(CONFIG_MACH_GTWX5715)		+= gtwx5715-pci.o
+ obj-pci-$(CONFIG_MACH_NSLU2)		+= nslu2-pci.o
+ obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
++obj-pci-$(CONFIG_MACH_DSMG600)		+= dsmg600-pci.o
+ 
+ obj-y	+= common.o
+ 
+@@ -22,5 +23,6 @@
+ obj-$(CONFIG_MACH_GTWX5715)	+= gtwx5715-setup.o
+ obj-$(CONFIG_MACH_NSLU2)	+= nslu2-setup.o nslu2-power.o
+ obj-$(CONFIG_MACH_NAS100D)	+= nas100d-setup.o nas100d-power.o
++obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o dsmg600-power.o
+ 
+ obj-$(CONFIG_PCI)		+= $(obj-pci-$(CONFIG_PCI)) common-pci.o
+Index: linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/dsmg600-pci.c
+===================================================================
+--- /dev/null
++++ linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/dsmg600-pci.c
+@@ -0,0 +1,74 @@
++/*
++ * DSM-G600 board-level PCI initialization
++ *
++ * Copyright (C) 2006 Tower Technologies
++ * Author: Alessandro Zummo <a.zummo@towertech.it>
++ *
++ * based on ixdp425-pci.c:
++ *	Copyright (C) 2002 Intel Corporation.
++ *	Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * Maintainer: http://www.nslu2-linux.org/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach/pci.h>
++#include <asm/mach-types.h>
++
++void __init dsmg600_pci_preinit(void)
++{
++	set_irq_type(IRQ_DSMG600_PCI_INTA, IRQT_LOW);
++	set_irq_type(IRQ_DSMG600_PCI_INTB, IRQT_LOW);
++	set_irq_type(IRQ_DSMG600_PCI_INTC, IRQT_LOW);
++	set_irq_type(IRQ_DSMG600_PCI_INTD, IRQT_LOW);
++	set_irq_type(IRQ_DSMG600_PCI_INTE, IRQT_LOW);
++	set_irq_type(IRQ_DSMG600_PCI_INTF, IRQT_LOW);
++
++	ixp4xx_pci_preinit();
++}
++
++static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] =
++	{
++		{ IRQ_DSMG600_PCI_INTE, -1, -1 },
++		{ IRQ_DSMG600_PCI_INTA, -1, -1 },
++		{ IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD },
++		{ IRQ_DSMG600_PCI_INTF, -1, -1 },
++	};
++
++	int irq = -1;
++
++	if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV &&
++		pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES)
++		irq = pci_irq_table[slot-1][pin-1];
++
++	return irq;
++}
++
++struct hw_pci __initdata dsmg600_pci = {
++	.nr_controllers = 1,
++	.preinit	= dsmg600_pci_preinit,
++	.swizzle	= pci_std_swizzle,
++	.setup		= ixp4xx_setup,
++	.scan		= ixp4xx_scan_bus,
++	.map_irq	= dsmg600_map_irq,
++};
++
++int __init dsmg600_pci_init(void)
++{
++	if (machine_is_dsmg600())
++		pci_common_init(&dsmg600_pci);
++
++	return 0;
++}
++
++subsys_initcall(dsmg600_pci_init);
+Index: linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/dsmg600-power.c
+===================================================================
+--- /dev/null
++++ linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/dsmg600-power.c
+@@ -0,0 +1,130 @@
++/*
++ * arch/arm/mach-ixp4xx/dsmg600-power.c
++ *
++ * DSM-G600 Power/Reset driver
++ * Author: Michael Westerhof <mwester@dls.net>
++ *
++ * Based on nslu2-power.c
++ *  Copyright (C) 2005 Tower Technologies
++ *  Author: Alessandro Zummo <a.zummo@towertech.it>
++ *
++ * which was based on nslu2-io.c
++ *  Copyright (C) 2004 Karen Spearel
++ *
++ * Maintainers: http://www.nslu2-linux.org/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/reboot.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/jiffies.h>
++#include <linux/timer.h>
++
++#include <asm/mach-types.h>
++
++extern void ctrl_alt_del(void);
++
++/* This is used to make sure the power-button pusher is serious.  The button
++ * must be held until the value of this counter reaches zero.
++ */
++static volatile int power_button_countdown;
++
++/* Must hold the button down for at least this many counts to be processed */
++#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
++
++static void dsmg600_power_handler(unsigned long data);
++static DEFINE_TIMER(dsmg600_power_timer, dsmg600_power_handler, 0, 0);
++
++static void dsmg600_power_handler(unsigned long data)
++{
++	/* This routine is called twice per second to check the
++	 * state of the power button.
++	 */
++
++	if (*IXP4XX_GPIO_GPINR & DSMG600_PB_BM) {
++
++		/* IO Pin is 1 (button pushed) */
++		if (power_button_countdown > 0) {
++			power_button_countdown--;
++		}
++
++	} else {
++
++		/* Done on button release, to allow for auto-power-on mods. */
++		if (power_button_countdown == 0) {
++			/* Signal init to do the ctrlaltdel action, this will bypass
++			 * init if it hasn't started and do a kernel_restart.
++			 */
++			ctrl_alt_del();
++
++			/* Change the state of the power LED to "blink" */
++			gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW);
++		} else {
++			power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
++		}
++	}
++
++	mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
++}
++
++static irqreturn_t dsmg600_reset_handler(int irq, void *dev_id)
++{
++	/* This is the paper-clip reset, it shuts the machine down directly. */
++	machine_power_off();
++
++	return IRQ_HANDLED;
++}
++
++static int __init dsmg600_power_init(void)
++{
++	if (!(machine_is_dsmg600()))
++		return 0;
++
++	if (request_irq(DSMG600_RB_IRQ, &dsmg600_reset_handler,
++		IRQF_DISABLED | IRQF_TRIGGER_LOW, "DSM-G600 reset button",
++		NULL) < 0) {
++
++		printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
++			DSMG600_RB_IRQ);
++
++		return -EIO;
++	}
++
++	/* The power button on the D-Link DSM-G600 is on GPIO 15, but
++	 * it cannot handle interrupts on that GPIO line.  So we'll
++	 * have to poll it with a kernel timer.
++	 */
++
++	/* Make sure that the power button GPIO is set up as an input */
++	gpio_line_config(DSMG600_PB_GPIO, IXP4XX_GPIO_IN);
++
++	/* Set the initial value for the power button IRQ handler */
++	power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
++
++	mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
++
++	return 0;
++}
++
++static void __exit dsmg600_power_exit(void)
++{
++	if (!(machine_is_dsmg600()))
++		return;
++
++	del_timer_sync(&dsmg600_power_timer);
++
++	free_irq(DSMG600_RB_IRQ, NULL);
++}
++
++module_init(dsmg600_power_init);
++module_exit(dsmg600_power_exit);
++
++MODULE_AUTHOR("Michael Westerhof <mwester@dls.net>");
++MODULE_DESCRIPTION("DSM-G600 Power/Reset driver");
++MODULE_LICENSE("GPL");
+Index: linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c
+===================================================================
+--- /dev/null
++++ linux-2.6.21.1-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c
+@@ -0,0 +1,175 @@
++/*
++ * DSM-G600 board-setup
++ *
++ * Copyright (C) 2006 Tower Technologies
++ * Author: Alessandro Zummo <a.zummo@towertech.it>
++ *
++ * based ixdp425-setup.c:
++ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * Author: Alessandro Zummo <a.zummo@towertech.it>
++ * Maintainers: http://www.nslu2-linux.org/
++ */
++
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data dsmg600_flash_data = {
++	.map_name		= "cfi_probe",
++	.width			= 2,
++};
++
++static struct resource dsmg600_flash_resource = {
++	.flags			= IORESOURCE_MEM,
++};
++
++static struct platform_device dsmg600_flash = {
++	.name			= "IXP4XX-Flash",
++	.id			= 0,
++	.dev.platform_data	= &dsmg600_flash_data,
++	.num_resources		= 1,
++	.resource		= &dsmg600_flash_resource,
++};
++
++static struct ixp4xx_i2c_pins dsmg600_i2c_gpio_pins = {
++	.sda_pin		= DSMG600_SDA_PIN,
++	.scl_pin		= DSMG600_SCL_PIN,
++};
++
++static struct platform_device dsmg600_i2c_controller = {
++	.name			= "IXP4XX-I2C",
++	.id			= 0,
++	.dev.platform_data	= &dsmg600_i2c_gpio_pins,
++};
++
++#ifdef CONFIG_LEDS_CLASS
++static struct resource dsmg600_led_resources[] = {
++	{
++		.name           = "power",
++		.start          = DSMG600_LED_PWR_GPIO,
++		.end            = DSMG600_LED_PWR_GPIO,
++		.flags          = IXP4XX_GPIO_HIGH,
++	},
++	{
++		.name           = "wlan",
++		.start		= DSMG600_LED_WLAN_GPIO,
++		.end            = DSMG600_LED_WLAN_GPIO,
++		.flags          = IXP4XX_GPIO_LOW,
++	},
++};
++
++static struct platform_device dsmg600_leds = {
++        .name                   = "IXP4XX-GPIO-LED",
++        .id                     = -1,
++        .num_resources          = ARRAY_SIZE(dsmg600_led_resources),
++        .resource               = dsmg600_led_resources,
++};
++#endif
++
++static struct resource dsmg600_uart_resources[] = {
++	{
++		.start		= IXP4XX_UART1_BASE_PHYS,
++		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= IXP4XX_UART2_BASE_PHYS,
++		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
++		.flags		= IORESOURCE_MEM,
++	}
++};
++
++static struct plat_serial8250_port dsmg600_uart_data[] = {
++	{
++		.mapbase	= IXP4XX_UART1_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART1,
++		.flags		= UPF_BOOT_AUTOCONF,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{
++		.mapbase	= IXP4XX_UART2_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART2,
++		.flags		= UPF_BOOT_AUTOCONF,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{ }
++};
++
++static struct platform_device dsmg600_uart = {
++	.name			= "serial8250",
++	.id			= PLAT8250_DEV_PLATFORM,
++	.dev.platform_data	= dsmg600_uart_data,
++	.num_resources		= ARRAY_SIZE(dsmg600_uart_resources),
++	.resource		= dsmg600_uart_resources,
++};
++
++static struct platform_device *dsmg600_devices[] __initdata = {
++	&dsmg600_i2c_controller,
++	&dsmg600_flash,
++};
++
++static void dsmg600_power_off(void)
++{
++	/* enable the pwr cntl gpio */
++	gpio_line_config(DSMG600_PO_GPIO, IXP4XX_GPIO_OUT);
++
++	/* poweroff */
++	gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH);
++}
++
++static void __init dsmg600_init(void)
++{
++	ixp4xx_sys_init();
++
++	/* Make sure that GPIO14 and GPIO15 are not used as clocks */
++	*IXP4XX_GPIO_GPCLKR = 0;
++
++	dsmg600_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++	dsmg600_flash_resource.end =
++		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
++
++	pm_power_off = dsmg600_power_off;
++
++	/* The UART is required on the DSM-G600 (Redboot cannot use the
++	 * NIC) -- do it here so that it does *not* get removed if
++	 * platform_add_devices fails!
++         */
++        (void)platform_device_register(&dsmg600_uart);
++
++	platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices));
++
++#ifdef CONFIG_LEDS_CLASS
++        /* We don't care whether or not this works. */
++        (void)platform_device_register(&dsmg600_leds);
++#endif
++}
++
++static void __init dsmg600_fixup(struct machine_desc *desc,
++                struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++       /* The xtal on this machine is non-standard. */
++        ixp4xx_timer_freq = DSMG600_FREQ;
++}
++
++MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
++	/* Maintainer: www.nslu2-linux.org */
++	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
++	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
++	.boot_params	= 0x00000100,
++	.fixup          = dsmg600_fixup,
++	.map_io		= ixp4xx_map_io,
++	.init_irq	= ixp4xx_init_irq,
++	.timer          = &ixp4xx_timer,
++	.init_machine	= dsmg600_init,
++MACHINE_END
+Index: linux-2.6.21.1-armeb/include/asm-arm/arch-ixp4xx/dsmg600.h
+===================================================================
+--- /dev/null
++++ linux-2.6.21.1-armeb/include/asm-arm/arch-ixp4xx/dsmg600.h
+@@ -0,0 +1,57 @@
++/*
++ * DSM-G600 platform specific definitions
++ *
++ * Copyright (C) 2006 Tower Technologies
++ * Author: Alessandro Zummo <a.zummo@towertech.it>
++ *
++ * based on ixdp425.h:
++ *	Copyright 2004 (C) MontaVista, Software, Inc.
++ *
++ * This file is licensed under  the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __ASM_ARCH_HARDWARE_H__
++#error "Do not include this directly, instead #include <asm/hardware.h>"
++#endif
++
++#define DSMG600_SDA_PIN		5
++#define DSMG600_SCL_PIN		4
++
++/*
++ * DSMG600 PCI IRQs
++ */
++#define DSMG600_PCI_MAX_DEV	4
++#define DSMG600_PCI_IRQ_LINES	3
++
++
++/* PCI controller GPIO to IRQ pin mappings */
++#define DSMG600_PCI_INTA_PIN	11
++#define DSMG600_PCI_INTB_PIN	10
++#define DSMG600_PCI_INTC_PIN	9
++#define DSMG600_PCI_INTD_PIN	8
++#define DSMG600_PCI_INTE_PIN	7
++#define DSMG600_PCI_INTF_PIN	6
++
++/* DSM-G600 Timer Setting */
++#define DSMG600_FREQ 66000000
++
++/* Buttons */
++
++#define DSMG600_PB_GPIO		15	/* power button */
++#define DSMG600_PB_BM		(1L << DSMG600_PB_GPIO)
++
++#define DSMG600_RB_GPIO		3	/* reset button */
++
++#define DSMG600_RB_IRQ		IRQ_IXP4XX_GPIO3
++
++#define DSMG600_PO_GPIO		2	/* power off */
++
++/* LEDs */
++
++#define DSMG600_LED_PWR_GPIO	0
++#define DSMG600_LED_PWR_BM	(1L << DSMG600_LED_PWR_GPIO)
++
++#define DSMG600_LED_WLAN_GPIO	14
++#define DSMG600_LED_WLAN_BM	(1L << DSMG600_LED_WLAN_GPIO)
+Index: linux-2.6.21.1-armeb/include/asm-arm/arch-ixp4xx/hardware.h
+===================================================================
+--- linux-2.6.21.1-armeb.orig/include/asm-arm/arch-ixp4xx/hardware.h
++++ linux-2.6.21.1-armeb/include/asm-arm/arch-ixp4xx/hardware.h
+@@ -47,5 +47,6 @@
+ #include "prpmc1100.h"
+ #include "nslu2.h"
+ #include "nas100d.h"
++#include "dsmg600.h"
+ 
+ #endif  /* _ASM_ARCH_HARDWARE_H */
+Index: linux-2.6.21.1-armeb/include/asm-arm/arch-ixp4xx/irqs.h
+===================================================================
+--- linux-2.6.21.1-armeb.orig/include/asm-arm/arch-ixp4xx/irqs.h
++++ linux-2.6.21.1-armeb/include/asm-arm/arch-ixp4xx/irqs.h
+@@ -118,4 +118,14 @@
+ #define        IRQ_NAS100D_PCI_INTD    IRQ_IXP4XX_GPIO8
+ #define        IRQ_NAS100D_PCI_INTE    IRQ_IXP4XX_GPIO7
+ 
++/*
++ * D-Link DSM-G600 RevA board IRQs
++ */
++#define        IRQ_DSMG600_PCI_INTA    IRQ_IXP4XX_GPIO11
++#define        IRQ_DSMG600_PCI_INTB    IRQ_IXP4XX_GPIO10
++#define        IRQ_DSMG600_PCI_INTC    IRQ_IXP4XX_GPIO9
++#define        IRQ_DSMG600_PCI_INTD    IRQ_IXP4XX_GPIO8
++#define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
++#define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
++
+ #endif
diff --git a/target/linux/ixp4xx/patches/070-ixp4xx_freq_fixup.patch b/target/linux/ixp4xx/patches/070-ixp4xx_freq_fixup.patch
new file mode 100644
index 0000000000..5b406a7bc7
--- /dev/null
+++ b/target/linux/ixp4xx/patches/070-ixp4xx_freq_fixup.patch
@@ -0,0 +1,131 @@
+This patch is required as the frequency fixup in nslu2_init does not
+run sufficiently early in the boot sequence to take effect. In
+addition the dsmg600 setup code behaviour has been improved such
+that a 'fixup' routine is avoided.
+
+Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
+
+Index: linux-2.6.21-arm/arch/arm/mach-ixp4xx/nslu2-setup.c
+===================================================================
+--- linux-2.6.21-arm.orig/arch/arm/mach-ixp4xx/nslu2-setup.c	2007-05-07 12:05:40.000000000 -0700
++++ linux-2.6.21-arm/arch/arm/mach-ixp4xx/nslu2-setup.c	2007-05-07 12:15:56.000000000 -0700
+@@ -22,6 +22,7 @@
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
++#include <asm/mach/time.h>
+ 
+ static struct flash_platform_data nslu2_flash_data = {
+ 	.map_name		= "cfi_probe",
+@@ -157,10 +158,21 @@
+ 	gpio_line_set(NSLU2_PO_GPIO, IXP4XX_GPIO_HIGH);
+ }
+ 
+-static void __init nslu2_init(void)
++static void __init nslu2_timer_init(void)
+ {
+-	ixp4xx_timer_freq = NSLU2_FREQ;
++    /* The xtal on this machine is non-standard. */
++    ixp4xx_timer_freq = NSLU2_FREQ;
++
++    /* Call standard timer_init function. */
++    ixp4xx_timer_init();
++}
+ 
++static struct sys_timer nslu2_timer = {
++    .init   = nslu2_timer_init,
++};
++
++static void __init nslu2_init(void)
++{
+ 	ixp4xx_sys_init();
+ 
+ 	nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+@@ -185,6 +197,6 @@
+ 	.boot_params	= 0x00000100,
+ 	.map_io		= ixp4xx_map_io,
+ 	.init_irq	= ixp4xx_init_irq,
+-	.timer          = &ixp4xx_timer,
++	.timer          = &nslu2_timer,
+ 	.init_machine	= nslu2_init,
+ MACHINE_END
+Index: linux-2.6.21-arm/arch/arm/mach-ixp4xx/common.c
+===================================================================
+--- linux-2.6.21-arm.orig/arch/arm/mach-ixp4xx/common.c	2007-05-07 12:05:40.000000000 -0700
++++ linux-2.6.21-arm/arch/arm/mach-ixp4xx/common.c	2007-05-07 12:15:16.000000000 -0700
+@@ -269,7 +269,7 @@
+ 	.handler	= ixp4xx_timer_interrupt,
+ };
+ 
+-static void __init ixp4xx_timer_init(void)
++void __init ixp4xx_timer_init(void)
+ {
+ 	/* Clear Pending Interrupt by writing '1' to it */
+ 	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
+Index: linux-2.6.21-arm/include/asm-arm/arch-ixp4xx/platform.h
+===================================================================
+--- linux-2.6.21-arm.orig/include/asm-arm/arch-ixp4xx/platform.h	2007-05-07 12:05:40.000000000 -0700
++++ linux-2.6.21-arm/include/asm-arm/arch-ixp4xx/platform.h	2007-05-07 12:15:16.000000000 -0700
+@@ -113,6 +113,7 @@
+ extern void ixp4xx_map_io(void);
+ extern void ixp4xx_init_irq(void);
+ extern void ixp4xx_sys_init(void);
++extern void ixp4xx_timer_init(void);
+ extern struct sys_timer ixp4xx_timer;
+ extern void ixp4xx_pci_preinit(void);
+ struct pci_sys_data;
+Index: linux-2.6.21-arm/arch/arm/mach-ixp4xx/dsmg600-setup.c
+===================================================================
+--- linux-2.6.21-arm.orig/arch/arm/mach-ixp4xx/dsmg600-setup.c	2007-05-07 12:05:42.000000000 -0700
++++ linux-2.6.21-arm/arch/arm/mach-ixp4xx/dsmg600-setup.c	2007-05-07 12:16:07.000000000 -0700
+@@ -18,6 +18,7 @@
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
++#include <asm/mach/time.h>
+ 
+ static struct flash_platform_data dsmg600_flash_data = {
+ 	.map_name		= "cfi_probe",
+@@ -128,6 +129,19 @@
+ 	gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH);
+ }
+ 
++static void __init dsmg600_timer_init(void)
++{
++    /* The xtal on this machine is non-standard. */
++    ixp4xx_timer_freq = DSMG600_FREQ;
++
++    /* Call standard timer_init function. */
++    ixp4xx_timer_init();
++}
++
++static struct sys_timer dsmg600_timer = {
++    .init   = dsmg600_timer_init,
++};
++
+ static void __init dsmg600_init(void)
+ {
+ 	ixp4xx_sys_init();
+@@ -155,21 +169,13 @@
+ #endif
+ }
+ 
+-static void __init dsmg600_fixup(struct machine_desc *desc,
+-                struct tag *tags, char **cmdline, struct meminfo *mi)
+-{
+-       /* The xtal on this machine is non-standard. */
+-        ixp4xx_timer_freq = DSMG600_FREQ;
+-}
+-
+ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
+ 	/* Maintainer: www.nslu2-linux.org */
+ 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+ 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+ 	.boot_params	= 0x00000100,
+-	.fixup          = dsmg600_fixup,
+ 	.map_io		= ixp4xx_map_io,
+ 	.init_irq	= ixp4xx_init_irq,
+-	.timer          = &ixp4xx_timer,
++	.timer          = &dsmg600_timer,
+ 	.init_machine	= dsmg600_init,
+ MACHINE_END
diff --git a/target/linux/ixp4xx/patches/080-trivial_nslu2_nas100d_cleanup.patch b/target/linux/ixp4xx/patches/080-trivial_nslu2_nas100d_cleanup.patch
new file mode 100644
index 0000000000..f0bfcdec5f
--- /dev/null
+++ b/target/linux/ixp4xx/patches/080-trivial_nslu2_nas100d_cleanup.patch
@@ -0,0 +1,196 @@
+This trivial patch updates the nslu2 and nas-100d headers to
+remove pointless GPIO defines, and updates nslu2-setup.c
+accordingly. In addition minor style cleanups to some comments
+are included.
+
+Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
+
+Index: linux-2.6.21-armeb/arch/arm/mach-ixp4xx/nslu2-setup.c
+===================================================================
+--- linux-2.6.21-armeb.orig/arch/arm/mach-ixp4xx/nslu2-setup.c	2007-05-09 07:32:43.000000000 -0700
++++ linux-2.6.21-armeb/arch/arm/mach-ixp4xx/nslu2-setup.c	2007-05-09 07:32:46.000000000 -0700
+@@ -50,26 +50,26 @@
+ static struct resource nslu2_led_resources[] = {
+ 	{
+ 		.name		= "ready",  /* green led */
+-		.start		= NSLU2_LED_GRN,
+-		.end		= NSLU2_LED_GRN,
++		.start		= NSLU2_LED_GRN_GPIO,
++		.end		= NSLU2_LED_GRN_GPIO,
+ 		.flags		= IXP4XX_GPIO_HIGH,
+ 	},
+ 	{
+ 		.name		= "status", /* red led */
+-		.start		= NSLU2_LED_RED,
+-		.end		= NSLU2_LED_RED,
++		.start		= NSLU2_LED_RED_GPIO,
++		.end		= NSLU2_LED_RED_GPIO,
+ 		.flags		= IXP4XX_GPIO_HIGH,
+ 	},
+ 	{
+ 		.name		= "disk-1",
+-		.start		= NSLU2_LED_DISK1,
+-		.end		= NSLU2_LED_DISK1,
++		.start		= NSLU2_LED_DISK1_GPIO,
++		.end		= NSLU2_LED_DISK1_GPIO,
+ 		.flags		= IXP4XX_GPIO_LOW,
+ 	},
+ 	{
+ 		.name		= "disk-2",
+-		.start		= NSLU2_LED_DISK2,
+-		.end		= NSLU2_LED_DISK2,
++		.start		= NSLU2_LED_DISK2_GPIO,
++		.end		= NSLU2_LED_DISK2_GPIO,
+ 		.flags		= IXP4XX_GPIO_LOW,
+ 	},
+ };
+@@ -181,7 +181,8 @@
+ 
+ 	pm_power_off = nslu2_power_off;
+ 
+-	/* This is only useful on a modified machine, but it is valuable
++	/*
++	 * This is only useful on a modified machine, but it is valuable
+ 	 * to have it first in order to see debug messages, and so that
+ 	 * it does *not* get removed if platform_add_devices fails!
+ 	 */
+Index: linux-2.6.21-armeb/include/asm-arm/arch-ixp4xx/nslu2.h
+===================================================================
+--- linux-2.6.21-armeb.orig/include/asm-arm/arch-ixp4xx/nslu2.h	2007-05-09 07:32:43.000000000 -0700
++++ linux-2.6.21-armeb/include/asm-arm/arch-ixp4xx/nslu2.h	2007-05-09 07:32:46.000000000 -0700
+@@ -9,7 +9,7 @@
+  * based on ixdp425.h:
+  *	Copyright 2004 (c) MontaVista, Software, Inc.
+  *
+- * This file is licensed under  the terms of the GNU General Public
++ * This file is licensed under the terms of the GNU General Public
+  * License version 2. This program is licensed "as is" without any
+  * warranty of any kind, whether express or implied.
+  */
+@@ -34,36 +34,14 @@
+ #define NSLU2_PCI_INTC_PIN	9
+ #define NSLU2_PCI_INTD_PIN	8
+ 
+-
+ /* NSLU2 Timer */
+ #define NSLU2_FREQ 66000000
+-#define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
+-#define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
+-
+-/* GPIO */
+-
+-#define NSLU2_GPIO0		0
+-#define NSLU2_GPIO1		1
+-#define NSLU2_GPIO2		2
+-#define NSLU2_GPIO3		3
+-#define NSLU2_GPIO4		4
+-#define NSLU2_GPIO5		5
+-#define NSLU2_GPIO6		6
+-#define NSLU2_GPIO7		7
+-#define NSLU2_GPIO8		8
+-#define NSLU2_GPIO9		9
+-#define NSLU2_GPIO10		10
+-#define NSLU2_GPIO11		11
+-#define NSLU2_GPIO12		12
+-#define NSLU2_GPIO13		13
+-#define NSLU2_GPIO14		14
+-#define NSLU2_GPIO15		15
+ 
+ /* Buttons */
+ 
+-#define NSLU2_PB_GPIO		NSLU2_GPIO5
+-#define NSLU2_PO_GPIO		NSLU2_GPIO8	/* power off */
+-#define NSLU2_RB_GPIO		NSLU2_GPIO12
++#define NSLU2_PB_GPIO		5
++#define NSLU2_PO_GPIO		8	/* power off */
++#define NSLU2_RB_GPIO		12
+ 
+ #define NSLU2_PB_IRQ		IRQ_IXP4XX_GPIO5
+ #define NSLU2_RB_IRQ		IRQ_IXP4XX_GPIO12
+@@ -79,16 +57,16 @@
+ 
+ /* LEDs */
+ 
+-#define NSLU2_LED_RED		NSLU2_GPIO0
+-#define NSLU2_LED_GRN		NSLU2_GPIO1
++#define NSLU2_LED_RED_GPIO	0
++#define NSLU2_LED_GRN_GPIO	1
+ 
+-#define NSLU2_LED_RED_BM	(1L << NSLU2_LED_RED)
+-#define NSLU2_LED_GRN_BM	(1L << NSLU2_LED_GRN)
++#define NSLU2_LED_RED_BM	(1L << NSLU2_LED_RED_GPIO)
++#define NSLU2_LED_GRN_BM	(1L << NSLU2_LED_GRN_GPIO)
+ 
+-#define NSLU2_LED_DISK1		NSLU2_GPIO3
+-#define NSLU2_LED_DISK2		NSLU2_GPIO2
++#define NSLU2_LED_DISK1_GPIO	3
++#define NSLU2_LED_DISK2_GPIO	2
+ 
+-#define NSLU2_LED_DISK1_BM	(1L << NSLU2_GPIO2)
+-#define NSLU2_LED_DISK2_BM	(1L << NSLU2_GPIO3)
++#define NSLU2_LED_DISK1_BM	(1L << NSLU2_LED_DISK1_GPIO)
++#define NSLU2_LED_DISK2_BM	(1L << NSLU2_LED_DISK2_GPIO)
+ 
+ 
+Index: linux-2.6.21-armeb/include/asm-arm/arch-ixp4xx/nas100d.h
+===================================================================
+--- linux-2.6.21-armeb.orig/include/asm-arm/arch-ixp4xx/nas100d.h	2007-04-25 20:08:32.000000000 -0700
++++ linux-2.6.21-armeb/include/asm-arm/arch-ixp4xx/nas100d.h	2007-05-09 07:34:14.000000000 -0700
+@@ -10,7 +10,7 @@
+  * based on ixdp425.h:
+  *	Copyright 2004 (c) MontaVista, Software, Inc.
+  *
+- * This file is licensed under  the terms of the GNU General Public
++ * This file is licensed under the terms of the GNU General Public
+  * License version 2. This program is licensed "as is" without any
+  * warranty of any kind, whether express or implied.
+  */
+@@ -36,31 +36,11 @@
+ #define NAS100D_PCI_INTD_PIN	8
+ #define NAS100D_PCI_INTE_PIN	7
+ 
+-/* GPIO */
+-
+-#define NAS100D_GPIO0           0
+-#define NAS100D_GPIO1           1
+-#define NAS100D_GPIO2           2
+-#define NAS100D_GPIO3           3
+-#define NAS100D_GPIO4           4
+-#define NAS100D_GPIO5           5
+-#define NAS100D_GPIO6           6
+-#define NAS100D_GPIO7           7
+-#define NAS100D_GPIO8           8
+-#define NAS100D_GPIO9           9
+-#define NAS100D_GPIO10          10
+-#define NAS100D_GPIO11          11
+-#define NAS100D_GPIO12          12
+-#define NAS100D_GPIO13          13
+-#define NAS100D_GPIO14          14
+-#define NAS100D_GPIO15          15
+-
+-
+ /* Buttons */
+ 
+-#define NAS100D_PB_GPIO         NAS100D_GPIO14
+-#define NAS100D_RB_GPIO         NAS100D_GPIO4
+-#define NAS100D_PO_GPIO         NAS100D_GPIO12   /* power off */
++#define NAS100D_PB_GPIO         14
++#define NAS100D_RB_GPIO         4
++#define NAS100D_PO_GPIO         12   /* power off */
+ 
+ #define NAS100D_PB_IRQ          IRQ_IXP4XX_GPIO14
+ #define NAS100D_RB_IRQ          IRQ_IXP4XX_GPIO4
+Index: linux-2.6.21-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c
+===================================================================
+--- linux-2.6.21-armeb.orig/arch/arm/mach-ixp4xx/nas100d-setup.c	2007-05-09 07:32:43.000000000 -0700
++++ linux-2.6.21-armeb/arch/arm/mach-ixp4xx/nas100d-setup.c	2007-05-09 07:34:55.000000000 -0700
+@@ -155,7 +155,8 @@
+ 
+ 	pm_power_off = nas100d_power_off;
+ 
+-	/* This is only useful on a modified machine, but it is valuable
++	/*
++	 * This is only useful on a modified machine, but it is valuable
+ 	 * to have it first in order to see debug messages, and so that
+ 	 * it does *not* get removed if platform_add_devices fails!
+ 	 */
diff --git a/target/linux/ixp4xx/patches/100-npe_driver.patch b/target/linux/ixp4xx/patches/100-npe_driver.patch
new file mode 100644
index 0000000000..78fb119bcd
--- /dev/null
+++ b/target/linux/ixp4xx/patches/100-npe_driver.patch
@@ -0,0 +1,4881 @@
+diff --git a/Documentation/networking/ixp4xx/IxNpeMicrocode.h b/Documentation/networking/ixp4xx/IxNpeMicrocode.h
+new file mode 100644
+index 0000000..e5a4bd3
+Index: linux-2.6.21-rc1-arm/Documentation/networking/ixp4xx/IxNpeMicrocode.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/Documentation/networking/ixp4xx/IxNpeMicrocode.h	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,143 @@
++/*
++ * IxNpeMicrocode.h - Headerfile for compiling the Intel microcode C file
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ *
++ *
++ * compile with
++ *
++ * gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
++ *
++ * Executing the resulting binary on your build-host creates the
++ * "NPE-[ABC].xxxxxxxx" files containing the selected microcode
++ *
++ * fetch the IxNpeMicrocode.c from the Intel Access Library.
++ * It will include this header.
++ *
++ * select Images for every NPE from the following
++ * (used C++ comments for easy uncommenting ....)
++ */
++
++// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_TSLOT_SWITCH
++// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
++// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
++// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
++// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
++// #define IX_NPEDL_NPEIMAGE_NPEA_DMA
++// #define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
++// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
++// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
++// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0
++// #define IX_NPEDL_NPEIMAGE_NPEA_WEP
++
++
++// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
++//#define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEB_DMA
++// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
++// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
++ #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
++
++
++// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
++// #define IX_NPEDL_NPEIMAGE_NPEC_DMA
++// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_SPAN
++// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_FIREWALL
++ #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_CCM_ETH
++// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_ETH_LEARN_FILTER_SPAN_FIREWALL
++// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
++// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
++// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
++
++
++#include <stdio.h>
++#include <unistd.h>
++#include <stdlib.h>
++#include <netinet/in.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <fcntl.h>
++#include <errno.h>
++#include <endian.h>
++#include <byteswap.h>
++#include <string.h>
++
++#if __BYTE_ORDER == __LITTLE_ENDIAN
++#define to_le32(x) (x)
++#define to_be32(x) bswap_32(x)
++#else
++#define to_be32(x) (x)
++#define to_le32(x) bswap_32(x)
++#endif
++
++struct dl_image {
++	unsigned magic;
++	unsigned id;
++	unsigned size;
++	unsigned data[0];
++};
++
++const unsigned IxNpeMicrocode_array[];
++
++int main(int argc, char *argv[])
++{
++	struct dl_image *image = (struct dl_image *)IxNpeMicrocode_array;
++	int imgsiz, i, fd, cnt;
++	const unsigned *arrayptr = IxNpeMicrocode_array;
++	const char *names[] = { "IXP425", "IXP465", "unknown" };
++	int bigendian = 1;
++
++	if (argc > 1) {
++		if (!strcmp(argv[1], "-le"))
++			bigendian = 0;
++		else if (!strcmp(argv[1], "-be"))
++			bigendian = 1;
++		else {
++			printf("Usage: %s <-le|-be>\n", argv[0]);
++			return EXIT_FAILURE;
++		}
++	}
++
++	for (image = (struct dl_image *)arrayptr, cnt=0;
++		(image->id != 0xfeedf00d) && (image->magic == 0xfeedf00d);
++		image = (struct dl_image *)(arrayptr), cnt++)
++	{
++		unsigned char field[4];
++		imgsiz = image->size + 3;
++		*(unsigned*)field = to_be32(image->id);
++		char filename[40], slnk[10];
++
++		sprintf(filename, "NPE-%c.%08x", (field[0] & 0xf) + 'A',
++			image->id);
++		sprintf(slnk, "NPE-%c", (field[0] & 0xf) + 'A');
++		printf("Writing image: %s.NPE_%c Func: %2x Rev: %02x.%02x "
++			"Size: %5d to: '%s'\n",
++			names[field[0] >> 4], (field[0] & 0xf) + 'A',
++			field[1], field[2], field[3], imgsiz*4, filename);
++		fd = open(filename, O_CREAT | O_RDWR | O_TRUNC, 0644);
++		if (fd >= 0) {
++			for (i=0; i<imgsiz; i++) {
++				*(unsigned*)field = bigendian ?
++					to_be32(arrayptr[i]) :
++					to_le32(arrayptr[i]);
++				write(fd, field, sizeof(field));
++			}
++			close(fd);
++			unlink(slnk);
++			symlink(filename, slnk);
++		} else {
++			perror(filename);
++		}
++		arrayptr += imgsiz;
++	}
++	close(fd);
++	return 0;
++}
+Index: linux-2.6.21-rc1-arm/Documentation/networking/ixp4xx/README
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/Documentation/networking/ixp4xx/README	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,62 @@
++Informations about the Networking Driver using the IXP4XX CPU internal NPEs
++and Queue manager.
++
++If this driver is used, the IAL (Intel Access Library) must not be loaded.
++However, the IAL may be loaded, if this Modules are unloaded:
++	ixp4xx_npe.ko, ixp4xx_qmgr.ko ixp4xx_mac.ko
++
++This also means that HW crypto accelleration does NOT work when using this
++driver, unless I have finished my crypto driver for NPE-C
++
++
++Adoption to your custom board:
++------------------------------
++use "arch/arm/mach-ixp4xx/ixdp425-setup.c" as template:
++
++in "static struct mac_plat_info" adopt the entry "phy_id" to your needs
++(Ask your hardware designer about the PHY id)
++
++The order of "&mac0" and "&mac1" in the "struct platform_device"
++determines which of them becomes eth0 and eth1
++
++
++The Microcode:
++---------------
++Solution 1)
++ Configure "CONFIG_HOTPLUG" and "CONFIG_FW_LOADER" and configure
++ IXP4XX_NPE as module.
++ The default hotplug script will load the Firmware from
++ /usr/lib/hotplug/firmware/NPE-[ABC]
++ see Documentation/firmware_class/hotplug-script
++
++ You should take care, that $ACTION is "add" and $SUBSYSTEM is "firmware"
++ to avoid unnessecary calls:
++ test $ACTION = "remove" -o $SUBSYSTEM != "firmware" && exit
++
++Solution 2)
++ create a char-dev: "mknod /dev/misc/npe c 10 184"
++ cat the Microcode into it:
++ cat /usr/lib/hotplug/firmware/NPE-* > /dev/misc/npe
++ This also works if the driver is linked to the kernel
++
++ Having a mix of both (e.g. solution 1 for NPE-B and solution 2 for NPE-C)
++ is perfectly ok and works.
++
++ The state of the NPEs can be seen and changed at:
++ /sys/bus/platform/devices/ixp4xx_npe.X/state
++
++
++Obtaining the Microcode:
++------------------------
++1) IxNpeMicrocode.h in this directory:
++   Download IPL_IXP400NPELIBRARYWITHCRYPTO-2_1.ZIP from Intel
++   It unpacks the Microcode IxNpeMicrocode.c
++   Read the Licence !
++   Compile it with "gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode" on your host.
++   The resulting images can be moved to "/usr/lib/hotplug/firmware"
++
++2) mc_grab.c in this directory:
++   Compile and execute it either on the host or on the target
++   to grab the microcode from a binary image like the RedBoot bootloader.
++
++
+Index: linux-2.6.21-rc1-arm/Documentation/networking/ixp4xx/mc_grab.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/Documentation/networking/ixp4xx/mc_grab.c	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,97 @@
++/*
++ * mc_grab.c  - grabs IXP4XX microcode from a binary datastream
++ * e.g. The redboot bootloader....
++ *
++ * usage: mc_grab 1010200 2010200 < /dev/mtd/0 > /dev/misc/npe
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++
++#include <stdlib.h>
++#include <stdio.h>
++#include <unistd.h>
++#include <netinet/in.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <fcntl.h>
++#include <errno.h>
++#include <string.h>
++
++#define MAX_IMG 6
++
++static void print_mc_info(unsigned id, int siz)
++{
++	unsigned char buf[sizeof(unsigned)];
++	*(unsigned*)buf = id;
++	unsigned idx;
++	const char *names[] = { "IXP425", "IXP465", "unknown" };
++
++	idx = (buf[0] >> 4) < 2 ? (buf[0] >> 4) : 2;
++
++	fprintf(stderr, "Device: %s:NPE_%c Func: %2x Rev: %02x.%02x "
++		"Size: %5d bytes ID:%08x\n", names[idx], (buf[0] & 0xf)+'A',
++		buf[1], buf[2], buf[3], siz*4, ntohl(id));
++}
++
++int main(int argc, char *argv[])
++{
++	int i,j;
++	unsigned char buf[sizeof(unsigned)];
++	unsigned magic = htonl(0xfeedf00d);
++	unsigned id, my_ids[MAX_IMG+1], siz, sizbe;
++	int ret=1, verbose=0;
++
++	for (i=0, j=0; i<argc-1 && j<MAX_IMG; i++) {
++		if (!strcmp(argv[i+1], "-v"))
++			verbose = 1;
++		else
++			my_ids[j++] = htonl(strtoul(argv[i+1], NULL, 16));
++	}
++	my_ids[j] = 0;
++	if (my_ids[0] == 0 && !verbose) {
++		fprintf(stderr, "Usage: %s <-v> [ID1] [ID2] [IDn]\n", argv[0]);
++		return 1;
++	}
++
++	while ((ret=read(0, buf, sizeof(unsigned))) == sizeof(unsigned)) {
++		if (*(unsigned*)buf != magic)
++			continue;
++		if ((ret=read(0, buf, sizeof(unsigned))) != sizeof(unsigned) )
++			break;
++		id = *(unsigned*)buf;
++
++		if (read(0, buf, sizeof(siz)) != sizeof(siz) )
++			break;
++		sizbe = *(unsigned*)buf;
++		siz = ntohl(sizbe);
++
++		if (verbose)
++			print_mc_info(id, siz);
++
++		for(i=0; my_ids[i]; i++)
++			if (id == my_ids[i])
++				break;
++		if (!my_ids[i])
++			continue;
++
++		if (!verbose)
++			print_mc_info(id, siz);
++
++		write(1, &magic, sizeof(magic));
++		write(1, &id, sizeof(id));
++		write(1, &sizbe, sizeof(sizbe));
++		for (i=0; i<siz; i++) {
++			if (read(0, buf, sizeof(unsigned)) != sizeof(unsigned))
++				break;
++			write(1, buf, sizeof(unsigned));
++		}
++		if (i != siz)
++			break;
++	}
++	if (ret)
++		fprintf(stderr, "Error reading  Microcode\n");
++	return ret;
++}
+Index: linux-2.6.21-rc1-arm/arch/arm/mach-ixp4xx/common.c
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/arch/arm/mach-ixp4xx/common.c	2007-02-21 02:24:18.000000000 -0800
++++ linux-2.6.21-rc1-arm/arch/arm/mach-ixp4xx/common.c	2007-02-21 02:24:35.000000000 -0800
+@@ -357,6 +357,90 @@
+ 	&ixp46x_i2c_controller
+ };
+ 
++static struct npe_plat_data npea = {
++	.name		= "NPE-A",
++	.data_size	= 0x800,
++	.inst_size	= 0x1000,
++	.id		= 0,
++};
++
++static struct npe_plat_data npeb = {
++	.name		= "NPE-B",
++	.data_size	= 0x800,
++	.inst_size	= 0x800,
++	.id		= 1,
++};
++
++static struct npe_plat_data npec = {
++	.name		= "NPE-C",
++	.data_size	= 0x800,
++	.inst_size	= 0x800,
++	.id		= 2,
++};
++
++static struct resource res_npea = {
++	.start		= IXP4XX_NPEA_BASE_PHYS,
++	.end		= IXP4XX_NPEA_BASE_PHYS + 0xfff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct resource res_npeb = {
++	.start		= IXP4XX_NPEB_BASE_PHYS,
++	.end		= IXP4XX_NPEB_BASE_PHYS + 0xfff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct resource res_npec = {
++	.start		= IXP4XX_NPEC_BASE_PHYS,
++	.end		= IXP4XX_NPEC_BASE_PHYS + 0xfff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct platform_device dev_npea = {
++	.name           = "ixp4xx_npe",
++	.id             = 0,
++	.dev.platform_data = &npea,
++	.num_resources  = 1,
++	.resource       = &res_npea,
++};
++
++static struct platform_device dev_npeb = {
++	.name           = "ixp4xx_npe",
++	.id             = 1,
++	.dev.platform_data = &npeb,
++	.num_resources  = 1,
++	.resource       = &res_npeb,
++};
++
++static struct platform_device dev_npec = {
++	.name           = "ixp4xx_npe",
++	.id             = 2,
++	.dev.platform_data = &npec,
++	.num_resources  = 1,
++	.resource       = &res_npec,
++};
++
++/* QMGR */
++static struct resource res_qmgr[] = {
++{
++	.start		= IXP4XX_QMGR_BASE_PHYS,
++	.end		= IXP4XX_QMGR_BASE_PHYS + IXP4XX_QMGR_REGION_SIZE -1,
++	.flags          = IORESOURCE_MEM,
++}, {
++	.start          = IRQ_IXP4XX_QM1,
++	.flags          = IORESOURCE_IRQ,
++} };
++
++static struct platform_device qmgr = {
++	.name           = "ixp4xx_qmgr",
++	.id             = 0,
++	.dev		= {
++		.coherent_dma_mask	= DMA_32BIT_MASK,
++	},
++	.num_resources  = ARRAY_SIZE(res_qmgr),
++	.resource       = res_qmgr,
++};
++
+ unsigned long ixp4xx_exp_bus_size;
+ EXPORT_SYMBOL(ixp4xx_exp_bus_size);
+ 
+@@ -378,8 +462,19 @@
+ 				break;
+ 			}
+ 		}
++		npeb.inst_size = 0x1000;
++		npec.inst_size = 0x1000;
+ 	}
+ 
++	platform_device_register(&qmgr);
++
++	if (ix_fuse() & IX_FUSE_NPEA)
++		platform_device_register(&dev_npea);
++	if (ix_fuse() & IX_FUSE_NPEB)
++		platform_device_register(&dev_npeb);
++	if (ix_fuse() & IX_FUSE_NPEC)
++		platform_device_register(&dev_npec);
++
+ 	printk("IXP4xx: Using %luMiB expansion bus window size\n",
+ 			ixp4xx_exp_bus_size >> 20);
+ }
+Index: linux-2.6.21-rc1-arm/arch/arm/mach-ixp4xx/ixdp425-setup.c
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/arch/arm/mach-ixp4xx/ixdp425-setup.c	2007-02-21 02:24:18.000000000 -0800
++++ linux-2.6.21-rc1-arm/arch/arm/mach-ixp4xx/ixdp425-setup.c	2007-02-21 02:24:35.000000000 -0800
+@@ -101,10 +101,59 @@
+ 	.resource		= ixdp425_uart_resources
+ };
+ 
++/* MACs */
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct resource res_mac1 = {
++	.start		= IXP4XX_EthC_BASE_PHYS,
++	.end		= IXP4XX_EthC_BASE_PHYS + 0x1ff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= 0,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct mac_plat_info plat_mac1 = {
++	.npe_id		= 2,
++	.phy_id		= 1,
++	.eth_id		= 1,
++	.rxq_id		= 28,
++	.txq_id		= 25,
++	.rxdoneq_id	= 5,
++};
++
++static struct platform_device mac0 = {
++	.name           = "ixp4xx_mac",
++	.id             = 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources  = 1,
++	.resource       = &res_mac0,
++};
++
++static struct platform_device mac1 = {
++	.name           = "ixp4xx_mac",
++	.id             = 1,
++	.dev.platform_data = &plat_mac1,
++	.num_resources  = 1,
++	.resource       = &res_mac1,
++};
++
+ static struct platform_device *ixdp425_devices[] __initdata = {
+ 	&ixdp425_i2c_controller,
+ 	&ixdp425_flash,
+-	&ixdp425_uart
++	&ixdp425_uart,
++	&mac0,
++	&mac1,
+ };
+ 
+ static void __init ixdp425_init(void)
+Index: linux-2.6.21-rc1-arm/drivers/net/Kconfig
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/drivers/net/Kconfig	2007-02-21 02:24:18.000000000 -0800
++++ linux-2.6.21-rc1-arm/drivers/net/Kconfig	2007-02-21 02:24:35.000000000 -0800
+@@ -201,6 +201,8 @@
+ 
+ source "drivers/net/arm/Kconfig"
+ 
++source "drivers/net/ixp4xx/Kconfig"
++
+ config MACE
+ 	tristate "MACE (Power Mac ethernet) support"
+ 	depends on NET_ETHERNET && PPC_PMAC && PPC32
+Index: linux-2.6.21-rc1-arm/drivers/net/Makefile
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/drivers/net/Makefile	2007-02-21 02:24:18.000000000 -0800
++++ linux-2.6.21-rc1-arm/drivers/net/Makefile	2007-02-21 02:24:35.000000000 -0800
+@@ -212,6 +212,7 @@
+ obj-$(CONFIG_IRDA) += irda/
+ obj-$(CONFIG_ETRAX_ETHERNET) += cris/
+ obj-$(CONFIG_ENP2611_MSF_NET) += ixp2000/
++obj-$(CONFIG_IXP4XX_NPE) += ixp4xx/
+ 
+ obj-$(CONFIG_NETCONSOLE) += netconsole.o
+ 
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/Kconfig
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/Kconfig	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,48 @@
++config IXP4XX_QMGR
++	tristate "IXP4xx Queue Manager support"
++	depends on ARCH_IXP4XX
++	depends on NET_ETHERNET
++	help
++	  The IXP4XX Queue manager is a configurable hardware ringbuffer.
++	  It is used by the NPEs to exchange data from and to the CPU.
++	  You can either use this OR the Intel Access Library (IAL)
++
++config IXP4XX_NPE
++	tristate "IXP4xx NPE support"
++	depends on ARCH_IXP4XX
++	depends on NET_ETHERNET
++	help
++	  The IXP4XX NPE driver supports the 3 CPU co-processors called
++	  "Network Processing Engines" (NPE). It adds support fo downloading
++	  the Microcode (firmware) via Hotplug or  character-special-device.
++	  More about this at: Documentation/networking/ixp4xx/README.
++	  You can either use this OR the Intel Access Library (IAL)
++
++config IXP4XX_FW_LOAD
++	bool "Use Firmware hotplug for Microcode download"
++	depends on IXP4XX_NPE
++	select HOTPLUG
++	select FW_LOADER
++	help
++	  The default hotplug script will load the Firmware from
++	  /usr/lib/hotplug/firmware/NPE-[ABC]
++	  see Documentation/firmware_class/hotplug-script
++
++config IXP4XX_MAC
++	tristate "IXP4xx MAC support"
++	depends on IXP4XX_NPE
++	depends on IXP4XX_QMGR
++	depends on NET_ETHERNET
++	select MII
++	help
++	  The IXP4XX MAC driver supports the MACs on the IXP4XX CPUs.
++	  There are 2 on ixp425 and up to 5 on ixdp465.
++	  You can either use this OR the Intel Access Library (IAL)
++
++config IXP4XX_CRYPTO
++	tristate "IXP4xx crypto support"
++	depends on IXP4XX_NPE
++	depends on IXP4XX_QMGR
++	help
++	  This driver is a generic NPE-crypto access layer.
++	  You need additional code in OCF for example.
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/Makefile
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/Makefile	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,7 @@
++obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
++obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
++obj-$(CONFIG_IXP4XX_MAC) += ixp4xx_mac.o
++obj-$(CONFIG_IXP4XX_CRYPTO) += ixp4xx_crypto.o
++
++ixp4xx_npe-objs := ucode_dl.o npe_mh.o npe.o
++ixp4xx_mac-objs := mac_driver.o phy.o
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/ixp4xx_crypto.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/ixp4xx_crypto.c	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,851 @@
++/*
++ * ixp4xx_crypto.c - interface to the HW crypto
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#include <linux/ixp_qmgr.h>
++#include <linux/ixp_npe.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/kernel.h>
++#include <linux/ixp_crypto.h>
++
++#define SEND_QID 29
++#define RECV_QID 30
++
++#define NPE_ID   2 /* NPE C */
++
++#define QUEUE_SIZE 64
++#define MY_VERSION "0.0.1"
++
++/* local head for all sa_ctx */
++static struct ix_sa_master sa_master;
++
++static const struct ix_hash_algo _hash_algos[] = {
++{
++	.name		= "MD5",
++	.cfgword	= 0xAA010004,
++	.digest_len	= 16,
++	.icv		= "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
++			"\xFE\xDC\xBA\x98\x76\x54\x32\x10",
++	.type		= HASH_TYPE_MD5,
++},{
++	.name		= "SHA1",
++	.cfgword	= 0x00000005,
++	.digest_len	= 20,
++	.icv		= "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
++			"\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
++	.type		= HASH_TYPE_SHA1,
++#if 0
++},{
++	.name		= "CBC MAC",
++	.digest_len	= 64,
++	.aad_len	= 48,
++	.type		= HASH_TYPE_CBCMAC,
++#endif
++} };
++
++static const struct ix_cipher_algo _cipher_algos[] = {
++{
++	.name		= "DES ECB",
++	.cfgword_enc	= CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
++	.cfgword_dec	= CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
++	.block_len	= 8,
++	.type		= CIPHER_TYPE_DES,
++	.mode		= CIPHER_MODE_ECB,
++},{
++	.name		= "DES CBC",
++	.cfgword_enc	= CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
++	.cfgword_dec	= CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
++	.iv_len		= 8,
++	.block_len	= 8,
++	.type		= CIPHER_TYPE_DES,
++	.mode		= CIPHER_MODE_CBC,
++},{
++	.name		= "3DES ECB",
++	.cfgword_enc	= CIPH_ENCR | MOD_TDEA3 | MOD_ECB | KEYLEN_192,
++	.cfgword_dec	= CIPH_DECR | MOD_TDEA3 | MOD_ECB | KEYLEN_192,
++	.block_len	= 8,
++	.type		= CIPHER_TYPE_3DES,
++	.mode		= CIPHER_MODE_ECB,
++},{
++	.name		= "3DES CBC",
++	.cfgword_enc	= CIPH_ENCR | MOD_TDEA3 | MOD_CBC_ENC | KEYLEN_192,
++	.cfgword_dec	= CIPH_DECR | MOD_TDEA3 | MOD_CBC_DEC | KEYLEN_192,
++	.iv_len		= 8,
++	.block_len	= 8,
++	.type		= CIPHER_TYPE_3DES,
++	.mode		= CIPHER_MODE_CBC,
++},{
++	.name		= "AES ECB",
++	.cfgword_enc	= CIPH_ENCR | ALGO_AES | MOD_ECB,
++	.cfgword_dec	= CIPH_DECR | ALGO_AES | MOD_ECB,
++	.block_len	= 16,
++	.type		= CIPHER_TYPE_AES,
++	.mode		= CIPHER_MODE_ECB,
++},{
++	.name		= "AES CBC",
++	.cfgword_enc	= CIPH_ENCR | ALGO_AES | MOD_CBC_ENC,
++	.cfgword_dec	= CIPH_DECR | ALGO_AES | MOD_CBC_DEC,
++	.block_len	= 16,
++	.iv_len		= 16,
++	.type		= CIPHER_TYPE_AES,
++	.mode		= CIPHER_MODE_CBC,
++},{
++	.name		= "AES CTR",
++	.cfgword_enc	= CIPH_ENCR | ALGO_AES | MOD_CTR,
++	.cfgword_dec	= CIPH_ENCR | ALGO_AES | MOD_CTR,
++	.block_len	= 16,
++	.iv_len		= 16,
++	.type		= CIPHER_TYPE_AES,
++	.mode		= CIPHER_MODE_CTR,
++#if 0
++},{
++	.name		= "AES CCM",
++	.cfgword_enc	= CIPH_ENCR | ALGO_AES | MOD_CCM_ENC,
++	.cfgword_dec	= CIPH_ENCR | ALGO_AES | MOD_CCM_DEC,
++	.block_len	= 16,
++	.iv_len		= 16,
++	.type		= CIPHER_TYPE_AES,
++	.mode		= CIPHER_MODE_CCM,
++#endif
++} };
++
++const struct ix_hash_algo *ix_hash_by_id(int type)
++{
++	int i;
++
++	for(i=0; i<ARRAY_SIZE(_hash_algos); i++) {
++		if (_hash_algos[i].type == type)
++			return _hash_algos + i;
++	}
++	return NULL;
++}
++
++const struct ix_cipher_algo *ix_cipher_by_id(int type, int mode)
++{
++	int i;
++
++	for(i=0; i<ARRAY_SIZE(_cipher_algos); i++) {
++		if (_cipher_algos[i].type==type && _cipher_algos[i].mode==mode)
++			return _cipher_algos + i;
++	}
++	return NULL;
++}
++
++static void irqcb_recv(struct qm_queue *queue);
++
++static int init_sa_master(struct ix_sa_master *master)
++{
++	struct npe_info *npe;
++	int ret = -ENODEV;
++
++	if (! (ix_fuse() & (IX_FUSE_HASH | IX_FUSE_AES | IX_FUSE_DES))) {
++		printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
++		return ret;
++	}
++	memset(master, 0, sizeof(struct ix_sa_master));
++	master->npe_dev = get_npe_by_id(NPE_ID);
++	if (! master->npe_dev)
++		goto err;
++
++	npe = dev_get_drvdata(master->npe_dev);
++
++	if (npe_status(npe) & IX_NPEDL_EXCTL_STATUS_RUN) {
++		switch (npe->img_info[1]) {
++		case 4:
++			printk(KERN_INFO "Crypto AES avaialable\n");
++			break;
++		case 5:
++			printk(KERN_INFO "Crypto AES and CCM avaialable\n");
++			break;
++		default:
++			printk(KERN_WARNING "Current microcode for %s has no"
++				" crypto capabilities\n", npe->plat->name);
++			break;
++		}
++	}
++	rwlock_init(&master->lock);
++	master->dmapool = dma_pool_create("ixp4xx_crypto", master->npe_dev,
++			sizeof(struct npe_crypt_cont), 32, 0);
++	if (!master->dmapool) {
++		ret = -ENOMEM;
++		goto err;
++	}
++	master->sendq = request_queue(SEND_QID, QUEUE_SIZE);
++	if (IS_ERR(master->sendq)) {
++		printk(KERN_ERR "ixp4xx_crypto: Error requesting Q: %d\n",
++				SEND_QID);
++		ret = PTR_ERR(master->sendq);
++		goto err;
++	}
++	master->recvq = request_queue(RECV_QID, QUEUE_SIZE);
++	if (IS_ERR(master->recvq)) {
++		printk(KERN_ERR "ixp4xx_crypto: Error requesting Q: %d\n",
++				RECV_QID);
++		ret = PTR_ERR(master->recvq);
++		release_queue(master->sendq);
++		goto err;
++	}
++
++	master->recvq->irq_cb = irqcb_recv;
++	queue_set_watermarks(master->recvq, 0, 0);
++	queue_set_irq_src(master->recvq, Q_IRQ_ID_NOT_E);
++	queue_enable_irq(master->recvq);
++	printk(KERN_INFO "ixp4xx_crypto " MY_VERSION " registered successfully\n");
++
++	return 0;
++err:
++	if (master->dmapool)
++		dma_pool_destroy(master->dmapool);
++	if (! master->npe_dev)
++		put_device(master->npe_dev);
++	return ret;
++
++}
++
++static void release_sa_master(struct ix_sa_master *master)
++{
++	struct npe_crypt_cont *cont;
++	unsigned long flags;
++
++	write_lock_irqsave(&master->lock, flags);
++	while (master->pool) {
++		cont = master->pool;
++		master->pool = cont->next;
++		dma_pool_free(master->dmapool, cont, cont->phys);
++		master->pool_size--;
++	}
++	write_unlock_irqrestore(&master->lock, flags);
++	if (master->pool_size) {
++		printk(KERN_ERR "ixp4xx_crypto: %d items lost from DMA pool\n",
++				master->pool_size);
++	}
++
++	dma_pool_destroy(master->dmapool);
++	release_queue(master->sendq);
++	release_queue(master->recvq);
++	return_npe_dev(master->npe_dev);
++}
++
++static struct npe_crypt_cont *ix_sa_get_cont(struct ix_sa_master *master)
++{
++	unsigned long flags;
++	struct npe_crypt_cont *cont;
++	dma_addr_t handle;
++
++	write_lock_irqsave(&master->lock, flags);
++	if (!master->pool) {
++		cont = dma_pool_alloc(master->dmapool, GFP_ATOMIC, &handle);
++		if (cont) {
++			master->pool_size++;
++			cont->phys = handle;
++			cont->virt = cont;
++		}
++	} else {
++		cont = master->pool;
++		master->pool = cont->next;
++	}
++	write_unlock_irqrestore(&master->lock, flags);
++	return cont;
++}
++
++static void
++ix_sa_return_cont(struct ix_sa_master *master,struct npe_crypt_cont *cont)
++{
++	unsigned long flags;
++
++	write_lock_irqsave(&master->lock, flags);
++	cont->next = master->pool;
++	master->pool = cont;
++	write_unlock_irqrestore(&master->lock, flags);
++}
++
++static void free_sa_dir(struct ix_sa_ctx *sa_ctx, struct ix_sa_dir *dir)
++{
++	memset(dir->npe_ctx, 0, NPE_CTX_LEN);
++	dma_pool_free(sa_ctx->master->dmapool, dir->npe_ctx,
++			dir->npe_ctx_phys);
++}
++
++static void ix_sa_ctx_destroy(struct ix_sa_ctx *sa_ctx)
++{
++	BUG_ON(sa_ctx->state != STATE_UNLOADING);
++	free_sa_dir(sa_ctx, &sa_ctx->encrypt);
++	free_sa_dir(sa_ctx, &sa_ctx->decrypt);
++	kfree(sa_ctx);
++	module_put(THIS_MODULE);
++}
++
++static void recv_pack(struct qm_queue *queue, u32 phys)
++{
++	struct ix_sa_ctx *sa_ctx;
++	struct npe_crypt_cont *cr_cont;
++	struct npe_cont *cont;
++	int failed;
++
++	failed = phys & 0x1;
++	phys &= ~0x3;
++
++	cr_cont = dma_to_virt(queue->dev, phys);
++	cr_cont = cr_cont->virt;
++	sa_ctx = cr_cont->ctl.crypt.sa_ctx;
++
++	phys = npe_to_cpu32(cr_cont->ctl.crypt.src_buf);
++	if (phys) {
++		cont = dma_to_virt(queue->dev, phys);
++		cont = cont->virt;
++	} else {
++		cont = NULL;
++	}
++	if (cr_cont->ctl.crypt.oper_type == OP_PERFORM) {
++		dma_unmap_single(sa_ctx->master->npe_dev,
++				cont->eth.phys_addr,
++				cont->eth.buf_len,
++				DMA_BIDIRECTIONAL);
++		if (sa_ctx->perf_cb)
++			sa_ctx->perf_cb(sa_ctx, cont->data, failed);
++		qmgr_return_cont(dev_get_drvdata(queue->dev), cont);
++		ix_sa_return_cont(sa_ctx->master, cr_cont);
++		if (atomic_dec_and_test(&sa_ctx->use_cnt))
++			ix_sa_ctx_destroy(sa_ctx);
++		return;
++	}
++
++	/* We are registering */
++	switch (cr_cont->ctl.crypt.mode) {
++	case NPE_OP_HASH_GEN_ICV:
++		/* 1 out of 2 HMAC preparation operations completed */
++		dma_unmap_single(sa_ctx->master->npe_dev,
++				cont->eth.phys_addr,
++				cont->eth.buf_len,
++				DMA_TO_DEVICE);
++		kfree(cont->data);
++		qmgr_return_cont(dev_get_drvdata(queue->dev), cont);
++		break;
++	case NPE_OP_ENC_GEN_KEY:
++		memcpy(sa_ctx->decrypt.npe_ctx + sizeof(u32),
++			sa_ctx->rev_aes->ctl.rev_aes_key + sizeof(u32),
++			sa_ctx->c_key.len);
++		/* REV AES data not needed anymore, free it */
++		ix_sa_return_cont(sa_ctx->master, sa_ctx->rev_aes);
++		sa_ctx->rev_aes = NULL;
++		break;
++	default:
++		printk(KERN_ERR "Unknown crypt-register mode: %x\n",
++				cr_cont->ctl.crypt.mode);
++
++	}
++	if (cr_cont->ctl.crypt.oper_type == OP_REG_DONE) {
++		if (sa_ctx->state == STATE_UNREGISTERED)
++			sa_ctx->state = STATE_REGISTERED;
++		if (sa_ctx->reg_cb)
++			sa_ctx->reg_cb(sa_ctx, failed);
++	}
++	ix_sa_return_cont(sa_ctx->master, cr_cont);
++	if (atomic_dec_and_test(&sa_ctx->use_cnt))
++		ix_sa_ctx_destroy(sa_ctx);
++}
++
++static void irqcb_recv(struct qm_queue *queue)
++{
++	u32 phys;
++
++	queue_ack_irq(queue);
++	while ((phys = queue_get_entry(queue)))
++		recv_pack(queue, phys);
++}
++
++static int init_sa_dir(struct ix_sa_ctx *sa_ctx, struct ix_sa_dir *dir)
++{
++	dir->npe_ctx = dma_pool_alloc(sa_ctx->master->dmapool,
++			sa_ctx->gfp_flags, &dir->npe_ctx_phys);
++	if (!dir->npe_ctx) {
++		return 1;
++	}
++	memset(dir->npe_ctx, 0, NPE_CTX_LEN);
++	return 0;
++}
++
++struct ix_sa_ctx *ix_sa_ctx_new(int priv_len, gfp_t flags)
++{
++	struct ix_sa_ctx *sa_ctx;
++	struct ix_sa_master *master = &sa_master;
++	struct npe_info *npe = dev_get_drvdata(master->npe_dev);
++
++	/* first check if Microcode was downloaded into this NPE */
++	if (!( npe_status(npe) & IX_NPEDL_EXCTL_STATUS_RUN)) {
++		printk(KERN_ERR "%s not running\n", npe->plat->name);
++		return NULL;
++	}
++	switch (npe->img_info[1]) {
++		case 4:
++		case 5:
++			break;
++		default:
++			/* No crypto Microcode */
++			return NULL;
++	}
++	if (!try_module_get(THIS_MODULE)) {
++		return NULL;
++	}
++
++	sa_ctx = kzalloc(sizeof(struct ix_sa_ctx) + priv_len, flags);
++	if (!sa_ctx) {
++		goto err_put;
++	}
++
++	sa_ctx->master = master;
++	sa_ctx->gfp_flags = flags;
++
++	if (init_sa_dir(sa_ctx, &sa_ctx->encrypt))
++		goto err_free;
++	if (init_sa_dir(sa_ctx, &sa_ctx->decrypt)) {
++		free_sa_dir(sa_ctx, &sa_ctx->encrypt);
++		goto err_free;
++	}
++	if (priv_len)
++		sa_ctx->priv = sa_ctx + 1;
++
++	atomic_set(&sa_ctx->use_cnt, 1);
++	return sa_ctx;
++
++err_free:
++	 kfree(sa_ctx);
++err_put:
++	 module_put(THIS_MODULE);
++	 return NULL;
++}
++
++void ix_sa_ctx_free(struct ix_sa_ctx *sa_ctx)
++{
++	sa_ctx->state = STATE_UNLOADING;
++	if (atomic_dec_and_test(&sa_ctx->use_cnt))
++		ix_sa_ctx_destroy(sa_ctx);
++	else
++		printk("ix_sa_ctx_free -> delayed: %p %d\n",
++				sa_ctx, atomic_read(&sa_ctx->use_cnt));
++}
++
++/* http://www.ietf.org/rfc/rfc2104.txt */
++#define HMAC_IPAD_VALUE 0x36
++#define HMAC_OPAD_VALUE 0x5C
++#define PAD_BLOCKLEN 64
++
++static int register_chain_var(struct ix_sa_ctx *sa_ctx,
++	unsigned char *pad, u32 target, int init_len, u32 ctx_addr, int oper)
++{
++	struct npe_crypt_cont *cr_cont;
++	struct npe_cont *cont;
++
++	cr_cont = ix_sa_get_cont(sa_ctx->master);
++	if (!cr_cont)
++		return -ENOMEM;
++
++	cr_cont->ctl.crypt.sa_ctx = sa_ctx;
++	cr_cont->ctl.crypt.auth_offs = 0;
++	cr_cont->ctl.crypt.auth_len =cpu_to_npe16(PAD_BLOCKLEN);
++	cr_cont->ctl.crypt.crypto_ctx = cpu_to_npe32(ctx_addr);
++
++	cont = qmgr_get_cont(dev_get_drvdata(sa_ctx->master->sendq->dev));
++	if (!cont) {
++		ix_sa_return_cont(sa_ctx->master, cr_cont);
++		return -ENOMEM;
++	}
++
++	cont->data = pad;
++	cont->eth.next = 0;
++	cont->eth.buf_len = cpu_to_npe16(PAD_BLOCKLEN);
++	cont->eth.pkt_len = 0;
++
++	cont->eth.phys_addr = cpu_to_npe32(dma_map_single(
++		sa_ctx->master->npe_dev, pad, PAD_BLOCKLEN, DMA_TO_DEVICE));
++
++	cr_cont->ctl.crypt.src_buf = cpu_to_npe32(cont->phys);
++	cr_cont->ctl.crypt.oper_type = oper;
++
++	cr_cont->ctl.crypt.addr.icv = cpu_to_npe32(target);
++	cr_cont->ctl.crypt.mode = NPE_OP_HASH_GEN_ICV;
++	cr_cont->ctl.crypt.init_len = init_len;
++
++	atomic_inc(&sa_ctx->use_cnt);
++	queue_put_entry(sa_ctx->master->sendq, cr_cont->phys);
++	if (queue_stat(sa_ctx->master->sendq) == 2) { /* overflow */
++		atomic_dec(&sa_ctx->use_cnt);
++		qmgr_return_cont(dev_get_drvdata(sa_ctx->master->sendq->dev),
++				cont);
++		ix_sa_return_cont(sa_ctx->master, cr_cont);
++		return -ENOMEM;
++	}
++	return 0;
++}
++
++/* Return value
++ * 0 if nothing registered,
++ * 1 if something registered and
++ * < 0 on error
++ */
++static int ix_sa_ctx_setup_auth(struct ix_sa_ctx *sa_ctx,
++		const struct ix_hash_algo *algo, int len, int oper, int encrypt)
++{
++	unsigned char *ipad, *opad;
++	u32 itarget, otarget, ctx_addr;
++	unsigned char *cinfo;
++	int init_len, i, ret = 0;
++	struct qm_qmgr *qmgr;
++	struct ix_sa_dir *dir;
++	u32 cfgword;
++
++	dir = encrypt ? &sa_ctx->encrypt : &sa_ctx->decrypt;
++	cinfo = dir->npe_ctx + dir->npe_ctx_idx;
++
++	qmgr = dev_get_drvdata(sa_ctx->master->sendq->dev);
++
++	cinfo = dir->npe_ctx + dir->npe_ctx_idx;
++	sa_ctx->h_algo = algo;
++
++	if (!algo) {
++		dir->npe_mode |= NPE_OP_HMAC_DISABLE;
++		return 0;
++	}
++	if (algo->type == HASH_TYPE_CBCMAC) {
++		dir->npe_mode |= NPE_OP_CCM_ENABLE | NPE_OP_HMAC_DISABLE;
++		return 0;
++	}
++	if (sa_ctx->h_key.len > 64 || sa_ctx->h_key.len < algo->digest_len)
++		return -EINVAL;
++	if (len > algo->digest_len || (len % 4))
++		return -EINVAL;
++	if (!len)
++		len = algo->digest_len;
++
++	sa_ctx->digest_len = len;
++
++	/* write cfg word to cryptinfo */
++	cfgword = algo->cfgword | ((len/4) << 8);
++	*(u32*)cinfo = cpu_to_be32(cfgword);
++	cinfo += sizeof(cfgword);
++
++	/* write ICV to cryptinfo */
++	memcpy(cinfo, algo->icv, algo->digest_len);
++	cinfo += algo->digest_len;
++
++	itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
++				+ sizeof(algo->cfgword);
++	otarget = itarget + algo->digest_len;
++
++	opad = kzalloc(PAD_BLOCKLEN, sa_ctx->gfp_flags | GFP_DMA);
++	if (!opad) {
++		return -ENOMEM;
++	}
++	ipad = kzalloc(PAD_BLOCKLEN, sa_ctx->gfp_flags | GFP_DMA);
++	if (!ipad) {
++		kfree(opad);
++		return -ENOMEM;
++	}
++	memcpy(ipad, sa_ctx->h_key.key, sa_ctx->h_key.len);
++	memcpy(opad, sa_ctx->h_key.key, sa_ctx->h_key.len);
++	for (i = 0; i < PAD_BLOCKLEN; i++) {
++		ipad[i] ^= HMAC_IPAD_VALUE;
++		opad[i] ^= HMAC_OPAD_VALUE;
++	}
++	init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
++	ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
++
++	dir->npe_ctx_idx += init_len;
++	dir->npe_mode |= NPE_OP_HASH_ENABLE;
++
++	if (!encrypt)
++		dir->npe_mode |= NPE_OP_HASH_VERIFY;
++
++	/* register first chainvar */
++	ret = register_chain_var(sa_ctx, opad, otarget,
++			init_len, ctx_addr, OP_REGISTER);
++	if (ret) {
++		kfree(ipad);
++		kfree(opad);
++		return ret;
++	}
++
++	/* register second chainvar */
++	ret = register_chain_var(sa_ctx, ipad, itarget,
++			init_len, ctx_addr, oper);
++	if (ret) {
++		kfree(ipad);
++		return ret;
++	}
++
++	return 1;
++}
++
++static int gen_rev_aes_key(struct ix_sa_ctx *sa_ctx,
++		u32 keylen_cfg, int cipher_op)
++{
++	unsigned char *cinfo;
++	struct npe_crypt_cont *cr_cont;
++
++	keylen_cfg |= CIPH_ENCR | ALGO_AES | MOD_ECB;
++	sa_ctx->rev_aes = ix_sa_get_cont(sa_ctx->master);
++	if (!sa_ctx->rev_aes)
++		return -ENOMEM;
++
++	cinfo = sa_ctx->rev_aes->ctl.rev_aes_key;
++	*(u32*)cinfo = cpu_to_be32(keylen_cfg);
++	cinfo += sizeof(keylen_cfg);
++
++	memcpy(cinfo, sa_ctx->c_key.key, sa_ctx->c_key.len);
++
++	cr_cont = ix_sa_get_cont(sa_ctx->master);
++	if (!cr_cont) {
++		ix_sa_return_cont(sa_ctx->master, sa_ctx->rev_aes);
++		sa_ctx->rev_aes = NULL;
++		return -ENOMEM;
++	}
++	cr_cont->ctl.crypt.sa_ctx = sa_ctx;
++	cr_cont->ctl.crypt.oper_type = cipher_op;
++
++	cr_cont->ctl.crypt.crypt_offs = 0;
++	cr_cont->ctl.crypt.crypt_len = cpu_to_npe16(AES_BLOCK128);
++	cr_cont->ctl.crypt.addr.rev_aes = cpu_to_npe32(
++			sa_ctx->rev_aes->phys + sizeof(keylen_cfg));
++
++	cr_cont->ctl.crypt.src_buf = 0;
++	cr_cont->ctl.crypt.crypto_ctx = cpu_to_npe32(sa_ctx->rev_aes->phys);
++	cr_cont->ctl.crypt.mode = NPE_OP_ENC_GEN_KEY;
++	cr_cont->ctl.crypt.init_len = sa_ctx->decrypt.npe_ctx_idx;
++
++	atomic_inc(&sa_ctx->use_cnt);
++	queue_put_entry(sa_ctx->master->sendq, cr_cont->phys);
++	if (queue_stat(sa_ctx->master->sendq) == 2) { /* overflow */
++		atomic_dec(&sa_ctx->use_cnt);
++		ix_sa_return_cont(sa_ctx->master, cr_cont);
++		ix_sa_return_cont(sa_ctx->master, sa_ctx->rev_aes);
++		sa_ctx->rev_aes = NULL;
++		return -ENOMEM;
++	}
++
++	return 1;
++}
++
++/* Return value
++ * 0 if nothing registered,
++ * 1 if something registered and
++ * < 0 on error
++ */
++static int ix_sa_ctx_setup_cipher(struct ix_sa_ctx *sa_ctx,
++		const struct ix_cipher_algo *algo, int cipher_op, int encrypt)
++{
++	unsigned char *cinfo;
++	int keylen, init_len;
++	u32 cipher_cfg;
++	u32 keylen_cfg = 0;
++	struct ix_sa_dir *dir;
++
++	dir = encrypt ? &sa_ctx->encrypt : &sa_ctx->decrypt;
++	cinfo = dir->npe_ctx + dir->npe_ctx_idx;
++
++	sa_ctx->c_algo = algo;
++
++	if (!algo)
++		return 0;
++
++	if (algo->type == CIPHER_TYPE_DES && sa_ctx->c_key.len != 8)
++		return -EINVAL;
++
++	if (algo->type == CIPHER_TYPE_3DES && sa_ctx->c_key.len != 24)
++		return -EINVAL;
++
++	keylen = 24;
++
++	if (encrypt) {
++		cipher_cfg = algo->cfgword_enc;
++		dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
++	} else {
++		cipher_cfg = algo->cfgword_dec;
++	}
++	if (algo->type == CIPHER_TYPE_AES) {
++		switch (sa_ctx->c_key.len) {
++			case 16: keylen_cfg = MOD_AES128 | KEYLEN_128; break;
++			case 24: keylen_cfg = MOD_AES192 | KEYLEN_192; break;
++			case 32: keylen_cfg = MOD_AES256 | KEYLEN_256; break;
++			default: return -EINVAL;
++		}
++		keylen = sa_ctx->c_key.len;
++		cipher_cfg |= keylen_cfg;
++	}
++
++	/* write cfg word to cryptinfo */
++	*(u32*)cinfo = cpu_to_be32(cipher_cfg);
++	cinfo += sizeof(cipher_cfg);
++
++	/* write cipher key to cryptinfo */
++	memcpy(cinfo, sa_ctx->c_key.key, sa_ctx->c_key.len);
++	cinfo += keylen;
++
++	init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
++	dir->npe_ctx_idx += init_len;
++
++	dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
++
++	if (algo->type == CIPHER_TYPE_AES && !encrypt) {
++		return gen_rev_aes_key(sa_ctx, keylen_cfg, cipher_op);
++	}
++
++	return 0;
++}
++
++/* returns 0 on OK, <0 on error and 1 on overflow */
++int ix_sa_crypto_perform(struct ix_sa_ctx *sa_ctx, u8 *data, void *ptr,
++	int datalen, int c_offs, int c_len, int a_offs, int a_len,
++	int hmac, char *iv, int encrypt)
++{
++	struct npe_crypt_cont *cr_cont;
++	struct npe_cont *cont;
++	u32 data_phys;
++	int ret = -ENOMEM;
++	struct ix_sa_dir *dir;
++
++	dir = encrypt ? &sa_ctx->encrypt : &sa_ctx->decrypt;
++
++	if (sa_ctx->state != STATE_REGISTERED)
++		return -ENOENT;
++
++	cr_cont = ix_sa_get_cont(sa_ctx->master);
++	if (!cr_cont)
++		return ret;
++
++	cr_cont->ctl.crypt.sa_ctx = sa_ctx;
++	cr_cont->ctl.crypt.crypto_ctx = cpu_to_npe32(dir->npe_ctx_phys);
++	cr_cont->ctl.crypt.oper_type = OP_PERFORM;
++	cr_cont->ctl.crypt.mode = dir->npe_mode;
++	cr_cont->ctl.crypt.init_len = dir->npe_ctx_idx;
++
++	if (sa_ctx->c_algo) {
++		cr_cont->ctl.crypt.crypt_offs = cpu_to_npe16(c_offs);
++		cr_cont->ctl.crypt.crypt_len = cpu_to_npe16(c_len);
++		if (sa_ctx->c_algo->iv_len) {
++			if (!iv) {
++				ret = -EINVAL;
++				goto err_cr;
++			}
++			memcpy(cr_cont->ctl.crypt.iv, iv,
++					sa_ctx->c_algo->iv_len);
++		}
++	}
++
++	if (sa_ctx->h_algo) {
++		/* prepare hashing */
++		cr_cont->ctl.crypt.auth_offs = cpu_to_npe16(a_offs);
++		cr_cont->ctl.crypt.auth_len = cpu_to_npe16(a_len);
++	}
++
++	data_phys = dma_map_single(sa_ctx->master->npe_dev,
++			data, datalen, DMA_BIDIRECTIONAL);
++	if (hmac)
++		cr_cont->ctl.crypt.addr.icv = cpu_to_npe32(data_phys + hmac);
++
++	/* Prepare the data ptr */
++	cont = qmgr_get_cont(dev_get_drvdata(sa_ctx->master->sendq->dev));
++	if (!cont) {
++		goto err_unmap;
++	}
++
++	cont->data = ptr;
++	cont->eth.next = 0;
++	cont->eth.buf_len = cpu_to_npe16(datalen);
++	cont->eth.pkt_len = 0;
++
++	cont->eth.phys_addr = cpu_to_npe32(data_phys);
++	cr_cont->ctl.crypt.src_buf = cpu_to_npe32(cont->phys);
++
++	atomic_inc(&sa_ctx->use_cnt);
++	queue_put_entry(sa_ctx->master->sendq, cr_cont->phys);
++	if (queue_stat(sa_ctx->master->sendq) != 2) {
++		return 0;
++	}
++
++	/* overflow */
++	printk("%s: Overflow\n", __FUNCTION__);
++	ret = -EAGAIN;
++	atomic_dec(&sa_ctx->use_cnt);
++	qmgr_return_cont(dev_get_drvdata(sa_ctx->master->sendq->dev), cont);
++
++err_unmap:
++	dma_unmap_single(sa_ctx->master->npe_dev, data_phys, datalen,
++			DMA_BIDIRECTIONAL);
++err_cr:
++	ix_sa_return_cont(sa_ctx->master, cr_cont);
++
++	return ret;
++}
++
++int ix_sa_ctx_setup_cipher_auth(struct ix_sa_ctx *sa_ctx,
++		const struct ix_cipher_algo *cipher,
++		const struct ix_hash_algo *auth, int len)
++{
++	int ret = 0, sum = 0;
++	int cipher_op;
++
++	if (sa_ctx->state != STATE_UNREGISTERED)
++		return -ENOENT;
++
++	atomic_inc(&sa_ctx->use_cnt);
++
++	cipher_op = auth ? OP_REGISTER : OP_REG_DONE;
++	if ((ret = ix_sa_ctx_setup_cipher(sa_ctx, cipher, OP_REGISTER, 1)) < 0)
++		goto out;
++	sum += ret;
++	if ((ret = ix_sa_ctx_setup_cipher(sa_ctx, cipher, cipher_op, 0)) < 0)
++		goto out;
++	sum += ret;
++	if ((ret = ix_sa_ctx_setup_auth(sa_ctx, auth, len, OP_REGISTER, 1)) < 0)
++		goto out;
++	sum += ret;
++	if ((ret = ix_sa_ctx_setup_auth(sa_ctx, auth, len, OP_REG_DONE, 0)) < 0)
++		goto out;
++	sum += ret;
++
++	/* Nothing registered ?
++	 * Ok, then we are done and call the callback here.
++	 */
++	if (!sum) {
++		if (sa_ctx->state == STATE_UNREGISTERED)
++			sa_ctx->state = STATE_REGISTERED;
++		if (sa_ctx->reg_cb)
++			sa_ctx->reg_cb(sa_ctx, 0);
++	}
++out:
++	atomic_dec(&sa_ctx->use_cnt);
++	return ret;
++}
++
++static int __init init_crypto(void)
++{
++	return init_sa_master(&sa_master);
++}
++
++static void __exit finish_crypto(void)
++{
++	release_sa_master(&sa_master);
++}
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
++
++EXPORT_SYMBOL(ix_hash_by_id);
++EXPORT_SYMBOL(ix_cipher_by_id);
++
++EXPORT_SYMBOL(ix_sa_ctx_new);
++EXPORT_SYMBOL(ix_sa_ctx_free);
++EXPORT_SYMBOL(ix_sa_ctx_setup_cipher_auth);
++EXPORT_SYMBOL(ix_sa_crypto_perform);
++
++module_init(init_crypto);
++module_exit(finish_crypto);
++
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/ixp4xx_qmgr.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/ixp4xx_qmgr.c	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,474 @@
++/*
++ * qmgr.c - reimplementation of the queue configuration interface.
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/dmapool.h>
++#include <linux/interrupt.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++
++#include <linux/ixp_qmgr.h>
++#include <linux/ixp_npe.h>
++
++#define IXQMGR_VERSION "IXP4XX Q Manager 0.2.1"
++
++static struct device *qmgr_dev = NULL;
++
++static int poll_freq = 4000;
++static int poll_enable = 0;
++static u32 timer_countup_ticks;
++
++module_param(poll_freq, int, 0644);
++module_param(poll_enable, int, 0644);
++
++int queue_len(struct qm_queue *queue)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	int diff, offs;
++	u32 val;
++
++	offs = queue->id/8 + QUE_LOW_STAT0;
++	val = *(qmgr->addr + IX_QMGR_QCFG_BASE + queue->id);
++
++	diff = (val - (val >> 7)) & 0x7f;
++	if (!diff) {
++		/* diff == 0 means either empty or full, must look at STAT0 */
++		if ((*(qmgr->addr + offs) >>  ((queue->id % 8)*4)) & 0x04)
++			diff = queue->len;
++	}
++	return diff;
++}
++
++static int request_pool(struct device *dev, int count)
++{
++	int i;
++	struct npe_cont *cont;
++	struct qm_qmgr *qmgr = dev_get_drvdata(dev);
++	dma_addr_t handle;
++
++	for (i=0; i<count; i++) {
++		cont = dma_pool_alloc(qmgr->dmapool, GFP_KERNEL, &handle);
++		if (!cont) {
++			return -ENOMEM;
++		}
++		cont->phys = handle;
++		cont->virt = cont;
++		write_lock(&qmgr->lock);
++		cont->next = qmgr->pool;
++		qmgr->pool = cont;
++		write_unlock(&qmgr->lock);
++	}
++	return 0;
++}
++
++static int free_pool(struct device *dev, int count)
++{
++	int i;
++	struct npe_cont *cont;
++	struct qm_qmgr *qmgr = dev_get_drvdata(dev);
++
++	for (i=0; i<count; i++) {
++		write_lock(&qmgr->lock);
++		cont = qmgr->pool;
++		if (!cont) {
++			write_unlock(&qmgr->lock);
++			return -1;
++		}
++		qmgr->pool = cont->next;
++		write_unlock(&qmgr->lock);
++		dma_pool_free(qmgr->dmapool, cont, cont->phys);
++	}
++	return 0;
++}
++
++static int get_free_qspace(struct qm_qmgr *qmgr, int len)
++{
++	int words = (qmgr->res->end - qmgr->res->start + 1) / 4 -
++			IX_QMGR_SRAM_SPACE;
++	int i,q;
++
++	for (i=0; i<words; i+=len) {
++		for (q=0; q<MAX_QUEUES; q++) {
++			struct qm_queue *qu = qmgr->queues[q];
++			if (!qu)
++				continue;
++			if ((qu->addr + qu->len > i) && (qu->addr < i + len))
++				break;
++		}
++		if (q == MAX_QUEUES) {
++			/* we have a free address */
++			return i;
++		}
++	}
++	return -1;
++}
++
++static inline int _log2(int x)
++{
++	int r=0;
++	while(x>>=1)
++		r++;
++	return r;
++}
++
++/*
++ * 32bit Config registers at IX_QMGR_QUECONFIG_BASE_OFFSET[Qid]
++ *    0 - 6 WRPTR Word offset to baseaddr (index 0 .. BSIZE-1)
++ *    7 -13 RDPTR        ''
++ *   14 -21 BADDR baseaddr = (offset to IX_QMGR_QUEBUFFER_SPACE_OFFSET) >> 6
++ *   22 -23 ESIZE entrySizeInWords (always 00 because entrySizeInWords==1)
++ *   24 -25 BSIZE qSizeInWords 00=16,01=32,10=64,11=128
++ *   26 -28 NE nearly empty
++ *   29 -31 NF nearly full
++ */
++static int conf_q_regs(struct qm_queue *queue)
++{
++	int bsize = _log2(queue->len/16);
++	int baddr = queue->addr + IX_QMGR_QCFG_SIZE;
++
++	/* +2, because baddr is in words and not in bytes */
++	queue_write_cfg_reg(queue,  (bsize << 24) | (baddr<<(14-6+2)) );
++
++	return 0;
++}
++
++static void pmu_timer_restart(void)
++{
++    unsigned long flags;
++
++    local_irq_save(flags);
++
++     __asm__(" mcr p14,0,%0,c1,c1,0\n"  /* write current counter */
++            : : "r" (timer_countup_ticks));
++
++    __asm__(" mrc p14,0,r1,c4,c1,0; "  /* get int enable register */
++            " orr r1,r1,#1; "
++            " mcr p14,0,r1,c5,c1,0; "  /* clear overflow */
++            " mcr p14,0,r1,c4,c1,0\n"  /* enable interrupts */
++            : : : "r1");
++
++    local_irq_restore(flags);
++}
++
++static void pmu_timer_init(void)
++{
++	u32 controlRegisterMask =
++		BIT(0) | /* enable counters */
++		BIT(2);  /* reset clock counter; */
++
++	/*
++	 *   Compute the number of xscale cycles needed between each
++	 *   PMU IRQ. This is done from the result of an OS calibration loop.
++	 *
++	 *   For 533MHz CPU, 533000000 tick/s / 4000 times/sec = 138250
++	 *   4000 times/sec = 37 mbufs/interrupt at line rate
++	 *   The pmu timer is reset to -138250 = 0xfffde3f6, to trigger an IRQ
++	 *   when this up counter overflows.
++	 *
++	 *   The multiplication gives a number of instructions per second.
++	 *   which is close to the processor frequency, and then close to the
++	 *   PMU clock rate.
++	 *
++	 *   2 is the number of instructions per loop
++	 *
++	 */
++
++	timer_countup_ticks = - ((loops_per_jiffy * HZ * 2) / poll_freq);
++
++	/* enable the CCNT (clock count) timer from the PMU */
++	__asm__(" mcr p14,0,%0,c0,c1,0\n"
++	        : : "r" (controlRegisterMask));
++}
++
++static void pmu_timer_disable(void)
++{
++	unsigned long flags;
++
++	local_irq_save(flags);
++
++	__asm__(" mrc p14,0,r1,c4,c1,0; "  /* get int enable register */
++	        " and r1,r1,#0x1e; "
++	        " mcr p14,0,r1,c4,c1,0\n"  /* disable interrupts */
++	        : : : "r1");
++	local_irq_restore(flags);
++}
++
++void queue_set_watermarks(struct qm_queue *queue, unsigned ne, unsigned nf)
++{
++	u32 val;
++	/* calculate the register values
++	 * 0->0, 1->1, 2->2, 4->3, 8->4 16->5...*/
++	ne = _log2(ne<<1) & 0x7;
++	nf = _log2(nf<<1) & 0x7;
++
++	/* Mask out old watermarks */
++	val = queue_read_cfg_reg(queue) & ~0xfc000000;
++	queue_write_cfg_reg(queue, val | (ne << 26) | (nf << 29));
++}
++
++int queue_set_irq_src(struct qm_queue *queue, int flag)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	u32 reg;
++	int offs, bitoffs;
++
++	/* Q 0-7 are in REG0, 8-15 are in REG1, etc. They occupy 4 bits/Q */
++	offs = queue->id/8 + INT0_SRC_SELREG0;
++	bitoffs = (queue->id % 8)*4;
++
++	reg = *(qmgr->addr + offs) & ~(0xf << bitoffs);
++	*(qmgr->addr + offs) = reg | (flag << bitoffs);
++
++	return 0;
++}
++
++static irqreturn_t irq_qm1(int irq, void *dev_id)
++{
++	struct qm_qmgr *qmgr = dev_id;
++	int offs, reg;
++	struct qm_queue *queue;
++
++	if (poll_enable)
++		pmu_timer_restart();
++
++	reg = *(qmgr->addr + QUE_INT_REG0);
++	while(reg) {
++		/*
++		 * count leading zeros. "offs" gets
++		 * the amount of leading 0 in "reg"
++		 */
++		asm ("clz %0, %1;" : "=r"(offs) : "r"(reg));
++		offs = 31 - offs;
++		reg &= ~(1 << offs);
++		queue = qmgr->queues[offs];
++		if (likely(queue)) {
++			if (likely(queue->irq_cb)) {
++				queue->irq_cb(queue);
++			} else {
++				printk(KERN_ERR "Missing callback for Q %d\n",
++						offs);
++			}
++		} else {
++			printk(KERN_ERR "IRQ for unregistered Q %d\n", offs);
++		}
++	}
++	return IRQ_HANDLED;
++}
++
++struct qm_queue *request_queue(int qid, int len)
++{
++	int ram;
++	struct qm_qmgr *qmgr;
++	struct qm_queue *queue;
++
++	if (!qmgr_dev)
++		return ERR_PTR(-ENODEV);
++
++	if ((qid < 0) || (qid > MAX_QUEUES))
++		return ERR_PTR(-ERANGE);
++
++	switch (len) {
++		case 16:
++		case 32:
++		case 64:
++		case 128: break;
++		default : return ERR_PTR(-EINVAL);
++	}
++
++	qmgr = dev_get_drvdata(qmgr_dev);
++
++	if (qmgr->queues[qid]) {
++		/* not an error, just in use already */
++		return NULL;
++	}
++	if ((ram = get_free_qspace(qmgr, len)) < 0) {
++		printk(KERN_ERR "No free SRAM space for this queue\n");
++		return ERR_PTR(-ENOMEM);
++	}
++	if (!(queue = kzalloc(sizeof(struct qm_queue), GFP_KERNEL)))
++		return ERR_PTR(-ENOMEM);
++
++	if (!try_module_get(THIS_MODULE)) {
++		kfree(queue);
++		return ERR_PTR(-ENODEV);
++	}
++
++	queue->addr = ram;
++	queue->len = len;
++	queue->id = qid;
++	queue->dev = get_device(qmgr_dev);
++	queue->acc_reg = qmgr->addr + (4 * qid);
++	qmgr->queues[qid] = queue;
++	if (request_pool(qmgr_dev, len)) {
++		printk(KERN_ERR "Failed to request DMA pool of Q %d\n", qid);
++	}
++
++	conf_q_regs(queue);
++	return queue;
++}
++
++void release_queue(struct qm_queue *queue)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++
++	BUG_ON(qmgr->queues[queue->id] != queue);
++	qmgr->queues[queue->id] = NULL;
++
++	if (free_pool(queue->dev, queue->len)) {
++		printk(KERN_ERR "Failed to release DMA pool of Q %d\n",
++				queue->id);
++	}
++	queue_disable_irq(queue);
++	queue_write_cfg_reg(queue, 0);
++
++	module_put(THIS_MODULE);
++	put_device(queue->dev);
++	kfree(queue);
++}
++
++
++
++
++static int qmgr_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct qm_qmgr *qmgr;
++	int size, ret=0, i;
++
++	if (!(res = platform_get_resource(pdev, IORESOURCE_MEM, 0)))
++		return -EIO;
++
++	if ((i = platform_get_irq(pdev, 0)) < 0)
++		return -EIO;
++
++	if (!(qmgr = kzalloc(sizeof(struct qm_qmgr), GFP_KERNEL)))
++		return -ENOMEM;
++
++	qmgr->irq = i;
++	size = res->end - res->start +1;
++	qmgr->res = request_mem_region(res->start, size, "ixp_qmgr");
++	if (!qmgr->res) {
++		ret = -EBUSY;
++		goto out_free;
++	}
++
++	qmgr->addr = ioremap(res->start, size);
++	if (!qmgr->addr) {
++		ret = -ENOMEM;
++		goto out_rel;
++	}
++
++	/* Reset Q registers */
++	for (i=0; i<4; i++)
++		*(qmgr->addr + QUE_LOW_STAT0 +i) = 0x33333333;
++	for (i=0; i<10; i++)
++		*(qmgr->addr + QUE_UO_STAT0 +i) = 0x0;
++	for (i=0; i<4; i++)
++		*(qmgr->addr + INT0_SRC_SELREG0 +i) = 0x0;
++	for (i=0; i<2; i++) {
++		*(qmgr->addr + QUE_IE_REG0 +i) = 0x00;
++		*(qmgr->addr + QUE_INT_REG0 +i) = 0xffffffff;
++	}
++	for (i=0; i<64; i++) {
++		*(qmgr->addr + IX_QMGR_QCFG_BASE + i) = 0x0;
++	}
++
++	if (poll_enable) {
++		pmu_timer_init();
++		qmgr->irq = IRQ_IXP4XX_XSCALE_PMU;
++	}
++	ret = request_irq(qmgr->irq, irq_qm1, SA_SHIRQ | SA_INTERRUPT,
++			"qmgr", qmgr);
++	if (ret) {
++		printk(KERN_ERR "Failed to request IRQ(%d)\n", qmgr->irq);
++		ret = -EIO;
++		goto out_rel;
++	}
++	if (poll_enable)
++		pmu_timer_restart();
++
++	rwlock_init(&qmgr->lock);
++	qmgr->dmapool = dma_pool_create("qmgr", &pdev->dev,
++			sizeof(struct npe_cont), 32, 0);
++	platform_set_drvdata(pdev, qmgr);
++
++	qmgr_dev = &pdev->dev;
++
++	printk(KERN_INFO IXQMGR_VERSION " initialized.\n");
++
++	return 0;
++
++out_rel:
++	release_resource(qmgr->res);
++out_free:
++	kfree(qmgr);
++	return ret;
++}
++
++static int qmgr_remove(struct platform_device *pdev)
++{
++	struct qm_qmgr *qmgr = platform_get_drvdata(pdev);
++	int i;
++
++	for (i=0; i<MAX_QUEUES; i++) {
++		if (qmgr->queues[i]) {
++			printk(KERN_ERR "WARNING Unreleased Q: %d\n", i);
++			release_queue(qmgr->queues[i]);
++		}
++	}
++
++	if (poll_enable)
++		pmu_timer_disable();
++
++	synchronize_irq (qmgr->irq);
++	free_irq(qmgr->irq, qmgr);
++
++	dma_pool_destroy(qmgr->dmapool);
++	iounmap(qmgr->addr);
++	release_resource(qmgr->res);
++	platform_set_drvdata(pdev, NULL);
++	qmgr_dev = NULL;
++	kfree(qmgr);
++	return 0;
++}
++
++static struct platform_driver ixp4xx_qmgr = {
++	.driver.name    = "ixp4xx_qmgr",
++	.probe          = qmgr_probe,
++	.remove         = qmgr_remove,
++};
++
++
++static int __init init_qmgr(void)
++{
++	return platform_driver_register(&ixp4xx_qmgr);
++}
++
++static void __exit finish_qmgr(void)
++{
++	platform_driver_unregister(&ixp4xx_qmgr);
++}
++
++module_init(init_qmgr);
++module_exit(finish_qmgr);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
++
++EXPORT_SYMBOL(request_queue);
++EXPORT_SYMBOL(release_queue);
++EXPORT_SYMBOL(queue_set_irq_src);
++EXPORT_SYMBOL(queue_set_watermarks);
++EXPORT_SYMBOL(queue_len);
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/mac.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/mac.h	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,275 @@
++/*
++ * Copyright (C) 2002-2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#include <linux/resource.h>
++#include <linux/netdevice.h>
++#include <linux/io.h>
++#include <linux/mii.h>
++#include <linux/workqueue.h>
++#include <asm/hardware.h>
++#include <linux/ixp_qmgr.h>
++
++/* 32 bit offsets to be added to u32 *pointers */
++#define MAC_TX_CNTRL1       0x00  // 0x000
++#define MAC_TX_CNTRL2       0x01  // 0x004
++#define MAC_RX_CNTRL1       0x04  // 0x010
++#define MAC_RX_CNTRL2       0x05  // 0x014
++#define MAC_RANDOM_SEED     0x08  // 0x020
++#define MAC_THRESH_P_EMPTY  0x0c  // 0x030
++#define MAC_THRESH_P_FULL   0x0e  // 0x038
++#define MAC_BUF_SIZE_TX     0x10  // 0x040
++#define MAC_TX_DEFER        0x14  // 0x050
++#define MAC_RX_DEFER        0x15  // 0x054
++#define MAC_TX_TWO_DEFER_1  0x18  // 0x060
++#define MAC_TX_TWO_DEFER_2  0x19  // 0x064
++#define MAC_SLOT_TIME       0x1c  // 0x070
++#define MAC_MDIO_CMD        0x20  // 0x080 4 registers 0x20 - 0x23
++#define MAC_MDIO_STS        0x24  // 0x090 4 registers 0x24 - 0x27
++#define MAC_ADDR_MASK       0x28  // 0x0A0 6 registers 0x28 - 0x2d
++#define MAC_ADDR            0x30  // 0x0C0 6 registers 0x30 - 0x35
++#define MAC_INT_CLK_THRESH  0x38  // 0x0E0 1 register
++#define MAC_UNI_ADDR        0x3c  // 0x0F0 6 registers 0x3c - 0x41
++#define MAC_CORE_CNTRL      0x7f  // 0x1fC
++
++/* TX Control Register 1*/
++
++#define TX_CNTRL1_TX_EN         BIT(0)
++#define TX_CNTRL1_DUPLEX        BIT(1)
++#define TX_CNTRL1_RETRY         BIT(2)
++#define TX_CNTRL1_PAD_EN        BIT(3)
++#define TX_CNTRL1_FCS_EN        BIT(4)
++#define TX_CNTRL1_2DEFER        BIT(5)
++#define TX_CNTRL1_RMII          BIT(6)
++
++/* TX Control Register 2 */
++#define TX_CNTRL2_RETRIES_MASK  0xf
++
++/* RX Control Register 1 */
++#define RX_CNTRL1_RX_EN         BIT(0)
++#define RX_CNTRL1_PADSTRIP_EN   BIT(1)
++#define RX_CNTRL1_CRC_EN        BIT(2)
++#define RX_CNTRL1_PAUSE_EN      BIT(3)
++#define RX_CNTRL1_LOOP_EN       BIT(4)
++#define RX_CNTRL1_ADDR_FLTR_EN  BIT(5)
++#define RX_CNTRL1_RX_RUNT_EN    BIT(6)
++#define RX_CNTRL1_BCAST_DIS     BIT(7)
++
++/* RX Control Register 2 */
++#define RX_CNTRL2_DEFER_EN      BIT(0)
++
++/* Core Control Register */
++#define CORE_RESET              BIT(0)
++#define CORE_RX_FIFO_FLUSH      BIT(1)
++#define CORE_TX_FIFO_FLUSH      BIT(2)
++#define CORE_SEND_JAM           BIT(3)
++#define CORE_MDC_EN             BIT(4)
++
++/* Definitions for MII access routines*/
++
++#define MII_REG_SHL    16
++#define MII_ADDR_SHL   21
++
++#define MII_GO                  BIT(31)
++#define MII_WRITE               BIT(26)
++#define MII_READ_FAIL           BIT(31)
++
++#define MII_TIMEOUT_10TH_SECS        5
++#define MII_10TH_SEC_IN_MILLIS     100
++
++/*
++ *
++ * Default values
++ *
++ */
++
++#define MAC_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
++
++#define MAC_TX_CNTRL1_DEFAULT  (\
++		TX_CNTRL1_TX_EN | \
++		TX_CNTRL1_RETRY  | \
++		TX_CNTRL1_FCS_EN | \
++		TX_CNTRL1_2DEFER | \
++		TX_CNTRL1_PAD_EN )
++
++#define MAC_TX_MAX_RETRIES_DEFAULT 0x0f
++
++#define MAC_RX_CNTRL1_DEFAULT ( \
++		RX_CNTRL1_PADSTRIP_EN | \
++		RX_CNTRL1_CRC_EN | \
++		RX_CNTRL1_RX_EN )
++
++#define MAC_RX_CNTRL2_DEFAULT       0x0
++#define MAC_TX_CNTRL2_DEFAULT       TX_CNTRL2_RETRIES_MASK
++
++/* Thresholds determined by NPE firmware FS */
++#define MAC_THRESH_P_EMPTY_DEFAULT  0x12
++#define MAC_THRESH_P_FULL_DEFAULT   0x30
++
++/* Number of bytes that must be in the tx fifo before
++ * transmission commences */
++#define MAC_BUF_SIZE_TX_DEFAULT     0x8
++
++/* One-part deferral values */
++#define MAC_TX_DEFER_DEFAULT        0x15
++#define MAC_RX_DEFER_DEFAULT        0x16
++
++/* Two-part deferral values... */
++#define MAC_TX_TWO_DEFER_1_DEFAULT  0x08
++#define MAC_TX_TWO_DEFER_2_DEFAULT  0x07
++
++/* This value applies to MII */
++#define MAC_SLOT_TIME_DEFAULT       0x80
++
++/* This value applies to RMII */
++#define MAC_SLOT_TIME_RMII_DEFAULT  0xFF
++
++#define MAC_ADDR_MASK_DEFAULT       0xFF
++
++#define MAC_INT_CLK_THRESH_DEFAULT  0x1
++/* The following is a value chosen at random */
++#define MAC_RANDOM_SEED_DEFAULT     0x8
++
++/* By default we must configure the MAC to generate the MDC clock*/
++#define CORE_DEFAULT                (CORE_MDC_EN)
++
++/* End of Intel provided register information */
++
++extern int
++mdio_read_register(struct net_device *dev, int phy_addr, int phy_reg);
++extern void
++mdio_write_register(struct net_device *dev, int phy_addr, int phy_reg, int val);
++extern void init_mdio(struct net_device *dev, int phy_id);
++
++struct mac_info {
++	u32 __iomem *addr;
++	struct resource *res;
++	struct device *npe_dev;
++	struct net_device *netdev;
++	struct qm_qmgr *qmgr;
++	struct qm_queue *rxq;
++	struct qm_queue *txq;
++	struct qm_queue *rxdoneq;
++	u32 irqflags;
++	struct net_device_stats stat;
++	struct mii_if_info mii;
++	struct delayed_work mdio_thread;
++	int rxq_pkt;
++	int txq_pkt;
++	int unloading;
++	struct mac_plat_info *plat;
++	int npe_stat_num;
++	spinlock_t rx_lock;
++	u32 msg_enable;
++};
++
++static inline void mac_write_reg(struct mac_info *mac, int offset, u32 val)
++{
++	*(mac->addr + offset) = val;
++}
++static inline u32 mac_read_reg(struct mac_info *mac, int offset)
++{
++	return *(mac->addr + offset);
++}
++static inline void mac_set_regbit(struct mac_info *mac, int offset, u32 bit)
++{
++	mac_write_reg(mac, offset, mac_read_reg(mac, offset) | bit);
++}
++static inline void mac_reset_regbit(struct mac_info *mac, int offset, u32 bit)
++{
++	mac_write_reg(mac, offset, mac_read_reg(mac, offset) & ~bit);
++}
++
++static inline void mac_mdio_cmd_write(struct mac_info *mac, u32 cmd)
++{
++	int i;
++	for(i=0; i<4; i++) {
++		mac_write_reg(mac, MAC_MDIO_CMD + i, cmd & 0xff);
++		cmd >>=8;
++	}
++}
++
++#define mac_mdio_cmd_read(mac) mac_mdio_read((mac), MAC_MDIO_CMD)
++#define mac_mdio_status_read(mac) mac_mdio_read((mac), MAC_MDIO_STS)
++static inline u32 mac_mdio_read(struct mac_info *mac, int offset)
++{
++	int i;
++	u32 data = 0;
++	for(i=0; i<4; i++) {
++		data |= (mac_read_reg(mac, offset + i) & 0xff) << (i*8);
++	}
++	return data;
++}
++
++static inline u32 mdio_cmd(int phy_addr, int phy_reg)
++{
++	return phy_addr << MII_ADDR_SHL |
++		phy_reg << MII_REG_SHL |
++	        MII_GO;
++}
++
++#define MAC_REG_LIST { \
++	MAC_TX_CNTRL1, MAC_TX_CNTRL2, \
++	MAC_RX_CNTRL1, MAC_RX_CNTRL2, \
++	MAC_RANDOM_SEED, MAC_THRESH_P_EMPTY, MAC_THRESH_P_FULL, \
++	MAC_BUF_SIZE_TX, MAC_TX_DEFER, MAC_RX_DEFER, \
++	MAC_TX_TWO_DEFER_1, MAC_TX_TWO_DEFER_2, MAC_SLOT_TIME, \
++	MAC_ADDR_MASK +0, MAC_ADDR_MASK +1, MAC_ADDR_MASK +2, \
++	MAC_ADDR_MASK +3, MAC_ADDR_MASK +4, MAC_ADDR_MASK +5, \
++	MAC_ADDR +0, MAC_ADDR +1, MAC_ADDR +2, \
++	MAC_ADDR +3, MAC_ADDR +4, MAC_ADDR +5, \
++	MAC_INT_CLK_THRESH, \
++	MAC_UNI_ADDR +0, MAC_UNI_ADDR +1, MAC_UNI_ADDR +2, \
++	MAC_UNI_ADDR +3, MAC_UNI_ADDR +4, MAC_UNI_ADDR +5, \
++	MAC_CORE_CNTRL \
++}
++
++#define NPE_STAT_NUM            34
++#define NPE_STAT_NUM_BASE       22
++#define NPE_Q_STAT_NUM           4
++
++#define NPE_Q_STAT_STRINGS \
++	{"RX ready to use queue len     "}, \
++	{"RX received queue len         "}, \
++	{"TX to be send queue len       "}, \
++	{"TX done queue len             "},
++
++#define NPE_STAT_STRINGS \
++	{"StatsAlignmentErrors          "}, \
++	{"StatsFCSErrors                "}, \
++	{"StatsInternalMacReceiveErrors "}, \
++	{"RxOverrunDiscards             "}, \
++	{"RxLearnedEntryDiscards        "}, \
++	{"RxLargeFramesDiscards         "}, \
++	{"RxSTPBlockedDiscards          "}, \
++	{"RxVLANTypeFilterDiscards      "}, \
++	{"RxVLANIdFilterDiscards        "}, \
++	{"RxInvalidSourceDiscards       "}, \
++	{"RxBlackListDiscards           "}, \
++	{"RxWhiteListDiscards           "}, \
++	{"RxUnderflowEntryDiscards      "}, \
++	{"StatsSingleCollisionFrames    "}, \
++	{"StatsMultipleCollisionFrames  "}, \
++	{"StatsDeferredTransmissions    "}, \
++	{"StatsLateCollisions           "}, \
++	{"StatsExcessiveCollsions       "}, \
++	{"StatsInternalMacTransmitErrors"}, \
++	{"StatsCarrierSenseErrors       "}, \
++	{"TxLargeFrameDiscards          "}, \
++	{"TxVLANIdFilterDiscards        "}, \
++\
++	{"RxValidFramesTotalOctets      "}, \
++	{"RxUcastPkts                   "}, \
++	{"RxBcastPkts                   "}, \
++	{"RxMcastPkts                   "}, \
++	{"RxPkts64Octets                "}, \
++	{"RxPkts65to127Octets           "}, \
++	{"RxPkts128to255Octets          "}, \
++	{"RxPkts256to511Octets          "}, \
++	{"RxPkts512to1023Octets         "}, \
++	{"RxPkts1024to1518Octets        "}, \
++	{"RxInternalNPEReceiveErrors    "}, \
++	{"TxInternalNPETransmitErrors   "}
++
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/mac_driver.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/mac_driver.c	2007-02-21 02:24:46.000000000 -0800
+@@ -0,0 +1,850 @@
++/*
++ * mac_driver.c - provide a network interface for each MAC
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/dma-mapping.h>
++#include <linux/workqueue.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++
++#include <linux/ixp_qmgr.h>
++#include <linux/ixp_npe.h>
++#include "mac.h"
++
++#define MDIO_INTERVAL (3*HZ)
++#define RX_QUEUE_PREFILL 64
++#define TX_QUEUE_PREFILL 16
++
++#define IXMAC_NAME "ixp4xx_mac"
++#define IXMAC_VERSION "0.3.1"
++
++#define MAC_DEFAULT_REG(mac, name) \
++	mac_write_reg(mac, MAC_ ## name, MAC_ ## name ## _DEFAULT)
++
++#define TX_DONE_QID 31
++
++#define DMA_ALLOC_SIZE 2048
++#define DMA_HDR_SIZE   (sizeof(struct npe_cont))
++#define DMA_BUF_SIZE (DMA_ALLOC_SIZE - DMA_HDR_SIZE)
++
++/* Since the NPEs use 1 Return Q for sent frames, we need a device
++ * independent return Q. We call it tx_doneq.
++ * It will be initialized during module load and uninitialized
++ * during module unload. Evil hack, but there is no choice :-(
++ */
++
++static struct qm_queue *tx_doneq = NULL;
++static int debug = -1;
++module_param(debug, int, 0);
++
++static int init_buffer(struct qm_queue *queue, int count)
++{
++	int i;
++	struct npe_cont *cont;
++
++	for (i=0; i<count; i++) {
++		cont = kmalloc(DMA_ALLOC_SIZE, GFP_KERNEL | GFP_DMA);
++		if (!cont)
++			goto err;
++
++		cont->phys = dma_map_single(queue->dev, cont, DMA_ALLOC_SIZE,
++				DMA_BIDIRECTIONAL);
++		if (dma_mapping_error(cont->phys))
++			goto err;
++
++		cont->data = cont+1;
++		/* now the buffer is on a 32 bit boundary.
++		 * we add 2 bytes for good alignment to SKB */
++		cont->data+=2;
++		cont->eth.next = 0;
++		cont->eth.buf_len = cpu_to_npe16(DMA_BUF_SIZE);
++		cont->eth.pkt_len = 0;
++		/* also add 2 alignment bytes from cont->data*/
++		cont->eth.phys_addr = cpu_to_npe32(cont->phys+ DMA_HDR_SIZE+ 2);
++
++		dma_sync_single(queue->dev, cont->phys, DMA_HDR_SIZE,
++				DMA_TO_DEVICE);
++
++		queue_put_entry(queue, cont->phys);
++		if (queue_stat(queue) == 2) { /* overflow */
++			dma_unmap_single(queue->dev, cont->phys, DMA_ALLOC_SIZE,
++				DMA_BIDIRECTIONAL);
++			goto err;
++		}
++	}
++	return i;
++err:
++	if (cont)
++		kfree(cont);
++	return i;
++}
++
++static int destroy_buffer(struct qm_queue *queue, int count)
++{
++	u32 phys;
++	int i;
++	struct npe_cont *cont;
++
++	for (i=0; i<count; i++) {
++		phys = queue_get_entry(queue) & ~0xf;
++		if (!phys)
++			break;
++		dma_unmap_single(queue->dev, phys, DMA_ALLOC_SIZE,
++				DMA_BIDIRECTIONAL);
++		cont = dma_to_virt(queue->dev, phys);
++		kfree(cont);
++	}
++	return i;
++}
++
++static void mac_init(struct mac_info *mac)
++{
++	MAC_DEFAULT_REG(mac, TX_CNTRL2);
++	MAC_DEFAULT_REG(mac, RANDOM_SEED);
++	MAC_DEFAULT_REG(mac, THRESH_P_EMPTY);
++	MAC_DEFAULT_REG(mac, THRESH_P_FULL);
++	MAC_DEFAULT_REG(mac, TX_DEFER);
++	MAC_DEFAULT_REG(mac, TX_TWO_DEFER_1);
++	MAC_DEFAULT_REG(mac, TX_TWO_DEFER_2);
++	MAC_DEFAULT_REG(mac, SLOT_TIME);
++	MAC_DEFAULT_REG(mac, INT_CLK_THRESH);
++	MAC_DEFAULT_REG(mac, BUF_SIZE_TX);
++	MAC_DEFAULT_REG(mac, TX_CNTRL1);
++	MAC_DEFAULT_REG(mac, RX_CNTRL1);
++}
++
++static void mac_set_uniaddr(struct net_device *dev)
++{
++	int i;
++	struct mac_info *mac = netdev_priv(dev);
++	struct npe_info *npe = dev_get_drvdata(mac->npe_dev);
++
++	/* check for multicast */
++	if (dev->dev_addr[0] & 1)
++		return;
++
++	npe_mh_setportaddr(npe, mac->plat, dev->dev_addr);
++	npe_mh_disable_firewall(npe, mac->plat);
++	for (i=0; i<dev->addr_len; i++)
++		mac_write_reg(mac, MAC_UNI_ADDR + i, dev->dev_addr[i]);
++}
++
++static void update_duplex_mode(struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	if (netif_msg_link(mac)) {
++		printk(KERN_DEBUG "Link of %s is %s-duplex\n", dev->name,
++				mac->mii.full_duplex ? "full" : "half");
++	}
++	if (mac->mii.full_duplex) {
++		mac_reset_regbit(mac, MAC_TX_CNTRL1, TX_CNTRL1_DUPLEX);
++	} else {
++		mac_set_regbit(mac, MAC_TX_CNTRL1, TX_CNTRL1_DUPLEX);
++	}
++}
++
++static int media_check(struct net_device *dev, int init)
++{
++	struct mac_info *mac = netdev_priv(dev);
++
++	if (mii_check_media(&mac->mii, netif_msg_link(mac), init)) {
++		update_duplex_mode(dev);
++		return 1;
++	}
++	return 0;
++}
++
++static void get_npe_stats(struct mac_info *mac, u32 *buf, int len, int reset)
++{
++	struct npe_info *npe = dev_get_drvdata(mac->npe_dev);
++	u32 phys;
++
++	memset(buf, len, 0);
++	phys = dma_map_single(mac->npe_dev, buf, len, DMA_BIDIRECTIONAL);
++	npe_mh_get_stats(npe, mac->plat, phys, reset);
++	dma_unmap_single(mac->npe_dev, phys, len, DMA_BIDIRECTIONAL);
++}
++
++static void irqcb_recv(struct qm_queue *queue)
++{
++	struct net_device *dev = queue->cb_data;
++
++	queue_ack_irq(queue);
++	queue_disable_irq(queue);
++	if (netif_running(dev))
++		netif_rx_schedule(dev);
++}
++
++int ix_recv(struct net_device *dev, int *budget, struct qm_queue *queue)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	struct sk_buff *skb;
++	u32 phys;
++	struct npe_cont *cont;
++
++	while (*budget > 0 && netif_running(dev) ) {
++		int len;
++		phys = queue_get_entry(queue) & ~0xf;
++		if (!phys)
++			break;
++		dma_sync_single(queue->dev, phys, DMA_HDR_SIZE,
++				DMA_FROM_DEVICE);
++		cont = dma_to_virt(queue->dev, phys);
++		len = npe_to_cpu16(cont->eth.pkt_len) -4; /* strip FCS */
++
++		if (unlikely(netif_msg_rx_status(mac))) {
++			printk(KERN_DEBUG "%s: RX packet size: %u\n",
++				dev->name, len);
++			queue_state(mac->rxq);
++			queue_state(mac->rxdoneq);
++		}
++		skb = dev_alloc_skb(len + 2);
++		if (likely(skb)) {
++			skb->dev = dev;
++			skb_reserve(skb, 2);
++			dma_sync_single(queue->dev, cont->eth.phys_addr, len,
++					DMA_FROM_DEVICE);
++#ifdef CONFIG_NPE_ADDRESS_COHERENT
++		        /* swap the payload of the SKB */
++	        	{
++				u32 *t = (u32*)(skb->data-2);
++				u32 *s = (u32*)(cont->data-2);
++				int i, j = (len+5)/4;
++				for (i=0; i<j; i++)
++					t[i] = cpu_to_be32(s[i]);
++			}
++#else			
++			eth_copy_and_sum(skb, cont->data, len, 0);
++#endif
++			skb_put(skb, len);
++			skb->protocol = eth_type_trans(skb, dev);
++			dev->last_rx = jiffies;
++			netif_receive_skb(skb);
++			mac->stat.rx_packets++;
++			mac->stat.rx_bytes += skb->len;
++		} else {
++			mac->stat.rx_dropped++;
++		}
++		cont->eth.buf_len = cpu_to_npe16(DMA_BUF_SIZE);
++		cont->eth.pkt_len = 0;
++		dma_sync_single(queue->dev, phys, DMA_HDR_SIZE, DMA_TO_DEVICE);
++		queue_put_entry(mac->rxq, phys);
++		dev->quota--;
++		(*budget)--;
++	}
++
++	return !budget;
++}
++
++static int ix_poll(struct net_device *dev, int *budget)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	struct qm_queue *queue = mac->rxdoneq;
++
++	for (;;) {
++		if (ix_recv(dev, budget, queue))
++			return 1;
++		netif_rx_complete(dev);
++		queue_enable_irq(queue);
++		if (!queue_len(queue))
++			break;
++		queue_disable_irq(queue);
++		if (netif_rx_reschedule(dev, 0))
++			break;
++	}
++	return 0;
++}
++
++static void ixmac_set_rx_mode (struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	struct dev_mc_list *mclist;
++	u8 aset[dev->addr_len], aclear[dev->addr_len];
++	int i,j;
++
++	if (dev->flags & IFF_PROMISC) {
++		mac_reset_regbit(mac, MAC_RX_CNTRL1, RX_CNTRL1_ADDR_FLTR_EN);
++	} else {
++		mac_set_regbit(mac, MAC_RX_CNTRL1, RX_CNTRL1_ADDR_FLTR_EN);
++
++		mclist = dev->mc_list;
++		memset(aset, 0xff, dev->addr_len);
++		memset(aclear, 0x00, dev->addr_len);
++		for (i = 0; mclist && i < dev->mc_count; i++) {
++			for (j=0; j< dev->addr_len; j++) {
++				aset[j] &= mclist->dmi_addr[j];
++				aclear[j] |= mclist->dmi_addr[j];
++			}
++			mclist = mclist->next;
++		}
++		for (j=0; j< dev->addr_len; j++) {
++			aclear[j] = aset[j] | ~aclear[j];
++		}
++		for (i=0; i<dev->addr_len; i++) {
++			mac_write_reg(mac, MAC_ADDR + i, aset[i]);
++			mac_write_reg(mac, MAC_ADDR_MASK + i, aclear[i]);
++		}
++	}
++}
++
++static int ixmac_open (struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	struct npe_info *npe = dev_get_drvdata(mac->npe_dev);
++	u32 buf[NPE_STAT_NUM];
++	int i;
++	u32 phys;
++
++	/* first check if the NPE is up and running */
++	if (!( npe_status(npe) & IX_NPEDL_EXCTL_STATUS_RUN)) {
++		printk(KERN_ERR "%s: %s not running\n", dev->name,
++				npe->plat->name);
++		return -EIO;
++	}
++	if (npe_mh_status(npe)) {
++		printk(KERN_ERR "%s: %s not responding\n", dev->name,
++				npe->plat->name);
++		return -EIO;
++	}
++	mac->txq_pkt += init_buffer(mac->txq, TX_QUEUE_PREFILL - mac->txq_pkt);
++	mac->rxq_pkt += init_buffer(mac->rxq, RX_QUEUE_PREFILL - mac->rxq_pkt);
++
++	queue_enable_irq(mac->rxdoneq);
++
++	/* drain all buffers from then RX-done-q to make the IRQ happen */
++	while ((phys = queue_get_entry(mac->rxdoneq) & ~0xf)) {
++		struct npe_cont *cont;
++		cont = dma_to_virt(mac->rxdoneq->dev, phys);
++		cont->eth.buf_len = cpu_to_npe16(DMA_BUF_SIZE);
++		cont->eth.pkt_len = 0;
++		dma_sync_single(mac->rxdoneq->dev, phys, DMA_HDR_SIZE,
++				DMA_TO_DEVICE);
++		queue_put_entry(mac->rxq, phys);
++	}
++	mac_init(mac);
++	npe_mh_set_rxqid(npe, mac->plat, mac->plat->rxdoneq_id);
++	get_npe_stats(mac, buf, sizeof(buf), 1); /* reset stats */
++	get_npe_stats(mac, buf, sizeof(buf), 0);
++	/*
++	 * if the extended stats contain random values
++	 * the NPE image lacks extendet statistic counters
++	 */
++	for (i=NPE_STAT_NUM_BASE; i<NPE_STAT_NUM; i++) {
++		if (buf[i] >10000)
++			break;
++	}
++	mac->npe_stat_num = i<NPE_STAT_NUM ? NPE_STAT_NUM_BASE : NPE_STAT_NUM;
++	mac->npe_stat_num += NPE_Q_STAT_NUM;
++
++	mac_set_uniaddr(dev);
++	media_check(dev, 1);
++	ixmac_set_rx_mode(dev);
++	netif_start_queue(dev);
++	schedule_delayed_work(&mac->mdio_thread, MDIO_INTERVAL);
++	if (netif_msg_ifup(mac)) {
++		 printk(KERN_DEBUG "%s: open " IXMAC_NAME
++		 	" RX queue %d bufs, TX queue %d bufs\n",
++			 dev->name, mac->rxq_pkt, mac->txq_pkt);
++	}
++	return 0;
++}
++
++static int ixmac_start_xmit (struct sk_buff *skb, struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	struct npe_cont *cont;
++	u32 phys;
++	struct qm_queue *queue = mac->txq;
++
++	if (unlikely(skb->len > DMA_BUF_SIZE)) {
++		dev_kfree_skb(skb);
++		mac->stat.tx_errors++;
++		return NETDEV_TX_OK;
++	}
++	phys = queue_get_entry(tx_doneq) & ~0xf;
++	if (!phys)
++		goto busy;
++	cont = dma_to_virt(queue->dev, phys);
++#ifdef CONFIG_NPE_ADDRESS_COHERENT
++	/* swap the payload of the SKB */
++	{
++		u32 *s = (u32*)(skb->data-2);
++		u32 *t = (u32*)(cont->data-2);
++		int i,j = (skb->len+5) / 4;
++		for (i=0; i<j; i++)
++			t[i] = cpu_to_be32(s[i]);
++	}
++#else			
++	//skb_copy_and_csum_dev(skb, cont->data);
++	memcpy(cont->data, skb->data, skb->len);
++#endif
++	cont->eth.buf_len = cpu_to_npe16(DMA_BUF_SIZE);
++	cont->eth.pkt_len = cpu_to_npe16(skb->len);
++	/* disable VLAN functions in NPE image for now */
++	cont->eth.flags = 0;
++	dma_sync_single(queue->dev, phys, skb->len + DMA_HDR_SIZE,
++			DMA_TO_DEVICE);
++	queue_put_entry(queue, phys);
++	if (queue_stat(queue) == 2) { /* overflow */
++		queue_put_entry(tx_doneq, phys);
++		goto busy;
++	}
++        dev_kfree_skb(skb);
++
++	mac->stat.tx_packets++;
++	mac->stat.tx_bytes += skb->len;
++	dev->trans_start = jiffies;
++	if (netif_msg_tx_queued(mac)) {
++		printk(KERN_DEBUG "%s: TX packet size %u\n",
++				dev->name, skb->len);
++		queue_state(mac->txq);
++		queue_state(tx_doneq);
++	}
++	return NETDEV_TX_OK;
++busy:
++	return NETDEV_TX_BUSY;
++}
++
++static int ixmac_close (struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++
++	netif_stop_queue (dev);
++	queue_disable_irq(mac->rxdoneq);
++
++	mac->txq_pkt -= destroy_buffer(tx_doneq, mac->txq_pkt);
++	mac->rxq_pkt -= destroy_buffer(mac->rxq, mac->rxq_pkt);
++
++	cancel_rearming_delayed_work(&(mac->mdio_thread));
++
++	if (netif_msg_ifdown(mac)) {
++		printk(KERN_DEBUG "%s: close " IXMAC_NAME
++			" RX queue %d bufs, TX queue %d bufs\n",
++			dev->name, mac->rxq_pkt, mac->txq_pkt);
++	}
++	return 0;
++}
++
++static int ixmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	int rc, duplex_changed;
++
++	if (!netif_running(dev))
++		return -EINVAL;
++	if (!try_module_get(THIS_MODULE))
++		return -ENODEV;
++	rc = generic_mii_ioctl(&mac->mii, if_mii(rq), cmd, &duplex_changed);
++	module_put(THIS_MODULE);
++	if (duplex_changed)
++		update_duplex_mode(dev);
++	return rc;
++}
++
++static struct net_device_stats *ixmac_stats (struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	return &mac->stat;
++}
++
++static void ixmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	struct npe_info *npe = dev_get_drvdata(mac->npe_dev);
++
++	strcpy(info->driver, IXMAC_NAME);
++	strcpy(info->version, IXMAC_VERSION);
++	if  (npe_status(npe) & IX_NPEDL_EXCTL_STATUS_RUN) {
++		snprintf(info->fw_version, 32, "%d.%d func [%d]",
++			npe->img_info[2], npe->img_info[3], npe->img_info[1]);
++	}
++	strncpy(info->bus_info, npe->plat->name, ETHTOOL_BUSINFO_LEN);
++}
++
++static int ixmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	mii_ethtool_gset(&mac->mii, cmd);
++	return 0;
++}
++
++static int ixmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	int rc;
++	rc = mii_ethtool_sset(&mac->mii, cmd);
++	return rc;
++}
++
++static int ixmac_nway_reset(struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	return mii_nway_restart(&mac->mii);
++}
++
++static u32 ixmac_get_link(struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	return mii_link_ok(&mac->mii);
++}
++
++static const int mac_reg_list[] = MAC_REG_LIST;
++
++static int ixmac_get_regs_len(struct net_device *dev)
++{
++	return ARRAY_SIZE(mac_reg_list);
++}
++
++static void
++ixmac_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
++{
++	int i;
++	struct mac_info *mac = netdev_priv(dev);
++	u8 *buf = regbuf;
++
++	for (i=0; i<regs->len; i++) {
++		buf[i] = mac_read_reg(mac, mac_reg_list[i]);
++	}
++}
++
++static struct {
++	const char str[ETH_GSTRING_LEN];
++} ethtool_stats_keys[NPE_STAT_NUM + NPE_Q_STAT_NUM] = {
++	NPE_Q_STAT_STRINGS
++	NPE_STAT_STRINGS
++};
++
++static void ixmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	memcpy(data, ethtool_stats_keys, mac->npe_stat_num * ETH_GSTRING_LEN);
++}
++
++static int ixmac_get_stats_count(struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	return mac->npe_stat_num;
++}
++
++static u32 ixmac_get_msglevel(struct net_device *dev)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	return mac->msg_enable;
++}
++
++static void ixmac_set_msglevel(struct net_device *dev, u32 datum)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	mac->msg_enable = datum;
++}
++
++static void ixmac_get_ethtool_stats(struct net_device *dev,
++		struct ethtool_stats *stats, u64 *data)
++{
++	int i;
++	struct mac_info *mac = netdev_priv(dev);
++	u32 buf[NPE_STAT_NUM];
++
++	data[0] = queue_len(mac->rxq);
++	data[1] = queue_len(mac->rxdoneq);
++	data[2] = queue_len(mac->txq);
++	data[3] = queue_len(tx_doneq);
++
++	get_npe_stats(mac, buf, sizeof(buf), 0);
++
++	for (i=0; i<stats->n_stats-4; i++) {
++		data[i+4] = npe_to_cpu32(buf[i]);
++	}
++}
++
++static struct ethtool_ops ixmac_ethtool_ops = {
++	.get_drvinfo		= ixmac_get_drvinfo,
++	.get_settings		= ixmac_get_settings,
++	.set_settings		= ixmac_set_settings,
++	.nway_reset		= ixmac_nway_reset,
++	.get_link		= ixmac_get_link,
++	.get_msglevel           = ixmac_get_msglevel,
++	.set_msglevel           = ixmac_set_msglevel,
++	.get_regs_len		= ixmac_get_regs_len,
++	.get_regs		= ixmac_get_regs,
++	.get_perm_addr		= ethtool_op_get_perm_addr,
++	.get_strings		= ixmac_get_strings,
++	.get_stats_count	= ixmac_get_stats_count,
++	.get_ethtool_stats	= ixmac_get_ethtool_stats,
++};
++
++static void mac_mdio_thread(struct work_struct *work)
++{
++	struct mac_info *mac = container_of(work, struct mac_info,
++			mdio_thread.work);
++	struct net_device *dev = mac->netdev;
++
++	media_check(dev, 0);
++	schedule_delayed_work(&mac->mdio_thread, MDIO_INTERVAL);
++}
++
++static int mac_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct mac_info *mac;
++	struct net_device *dev;
++	struct npe_info *npe;
++	struct mac_plat_info *plat = pdev->dev.platform_data;
++	int size, ret;
++
++	if (!(res = platform_get_resource(pdev, IORESOURCE_MEM, 0))) {
++		return -EIO;
++	}
++	if (!(dev = alloc_etherdev (sizeof(struct mac_info)))) {
++		return -ENOMEM;
++	}
++	SET_MODULE_OWNER(dev);
++	SET_NETDEV_DEV(dev, &pdev->dev);
++	mac = netdev_priv(dev);
++	mac->netdev = dev;
++
++	size = res->end - res->start +1;
++	mac->res = request_mem_region(res->start, size, IXMAC_NAME);
++	if (!mac->res) {
++		ret = -EBUSY;
++		goto out_free;
++	}
++
++	mac->addr = ioremap(res->start, size);
++	if (!mac->addr) {
++		ret = -ENOMEM;
++		goto out_rel;
++	}
++
++	dev->open = ixmac_open;
++	dev->hard_start_xmit = ixmac_start_xmit;
++	dev->poll = ix_poll;
++	dev->stop = ixmac_close;
++	dev->get_stats = ixmac_stats;
++	dev->do_ioctl = ixmac_ioctl;
++	dev->set_multicast_list = ixmac_set_rx_mode;
++	dev->ethtool_ops = &ixmac_ethtool_ops;
++
++	dev->weight = 16;
++	dev->tx_queue_len = 100;
++
++	mac->npe_dev = get_npe_by_id(plat->npe_id);
++	if (!mac->npe_dev) {
++		ret = -EIO;
++		goto out_unmap;
++	}
++	npe = dev_get_drvdata(mac->npe_dev);
++
++	mac->rxq = request_queue(plat->rxq_id, 128);
++	if (IS_ERR(mac->rxq)) {
++		printk(KERN_ERR "Error requesting Q: %d\n", plat->rxq_id);
++		ret = -EBUSY;
++		goto out_putmod;
++	}
++	mac->txq = request_queue(plat->txq_id, 128);
++	if (IS_ERR(mac->txq)) {
++		printk(KERN_ERR "Error requesting Q: %d\n", plat->txq_id);
++		ret = -EBUSY;
++		goto out_putmod;
++	}
++	mac->rxdoneq = request_queue(plat->rxdoneq_id, 128);
++	if (IS_ERR(mac->rxdoneq)) {
++		printk(KERN_ERR "Error requesting Q: %d\n", plat->rxdoneq_id);
++		ret = -EBUSY;
++		goto out_putmod;
++	}
++	mac->rxdoneq->irq_cb = irqcb_recv;
++	mac->rxdoneq->cb_data = dev;
++	queue_set_watermarks(mac->rxdoneq, 0, 0);
++	queue_set_irq_src(mac->rxdoneq, Q_IRQ_ID_NOT_E);
++
++	mac->qmgr = dev_get_drvdata(mac->rxq->dev);
++	if (register_netdev (dev)) {
++		ret = -EIO;
++		goto out_putmod;
++	}
++
++	mac->plat = plat;
++	mac->npe_stat_num = NPE_STAT_NUM_BASE;
++	mac->msg_enable = netif_msg_init(debug, MAC_DEF_MSG_ENABLE);
++
++	platform_set_drvdata(pdev, dev);
++
++	mac_write_reg(mac, MAC_CORE_CNTRL, CORE_RESET);
++	udelay(500);
++	mac_write_reg(mac, MAC_CORE_CNTRL, CORE_MDC_EN);
++
++	init_mdio(dev, plat->phy_id);
++
++	INIT_DELAYED_WORK(&mac->mdio_thread, mac_mdio_thread);
++
++	/* The place of the MAC address is very system dependent.
++	 * Here we use a random one to be replaced by one of the
++	 * following commands:
++	 * "ip link set address 02:03:04:04:04:01 dev eth0"
++	 * "ifconfig eth0 hw ether 02:03:04:04:04:07"
++	*/
++
++	if (is_zero_ether_addr(plat->hwaddr)) {
++		random_ether_addr(dev->dev_addr);
++		dev->dev_addr[5] = plat->phy_id;
++	}
++	else
++		memcpy(dev->dev_addr, plat->hwaddr, 6);
++
++	printk(KERN_INFO IXMAC_NAME " driver " IXMAC_VERSION
++			": %s on %s with PHY[%d] initialized\n",
++			dev->name, npe->plat->name, plat->phy_id);
++
++	return 0;
++
++out_putmod:
++	if (mac->rxq)
++		release_queue(mac->rxq);
++	if (mac->txq)
++		release_queue(mac->txq);
++	if (mac->rxdoneq)
++		release_queue(mac->rxdoneq);
++	module_put(mac->npe_dev->driver->owner);
++out_unmap:
++	iounmap(mac->addr);
++out_rel:
++	release_resource(mac->res);
++out_free:
++	kfree(mac);
++	return ret;
++}
++
++static void drain_npe(struct mac_info *mac)
++{
++	struct npe_info *npe = dev_get_drvdata(mac->npe_dev);
++	struct npe_cont *cont;
++	u32 phys;
++	int loop = 0;
++
++	/* Now there are some skb hold by the NPE.
++	 * We switch the MAC in loopback mode and send a pseudo packet
++	 * that will be returned by the NPE in its last SKB.
++	 * We will also try to isolate the PHY to keep the packets internal.
++	 */
++
++	if (mac->txq_pkt <2)
++		mac->txq_pkt += init_buffer(tx_doneq, 5);
++
++	if (npe_status(npe) & IX_NPEDL_EXCTL_STATUS_RUN) {
++		mac_reset_regbit(mac, MAC_CORE_CNTRL, CORE_MDC_EN);
++		mac_set_regbit(mac, MAC_RX_CNTRL1, RX_CNTRL1_LOOP_EN);
++
++		npe_mh_npe_loopback_mode(npe, mac->plat, 1);
++		mdelay(200);
++
++		while (mac->rxq_pkt && loop++ < 2000 ) {
++			phys = queue_get_entry(tx_doneq) & ~0xf;
++			if (!phys)
++				break;
++			cont = dma_to_virt(queue->dev, phys);
++			/* actually the packets should never leave the system,
++			 * but if they do, they shall contain 0s instead of
++			 * intresting random data....
++			 */
++			memset(cont->data, 0, 64);
++			cont->eth.pkt_len = 64;
++			dma_sync_single(mac->txq->dev, phys, 64 + DMA_HDR_SIZE,
++					DMA_TO_DEVICE);
++			queue_put_entry(mac->txq, phys);
++			if (queue_stat(mac->txq) == 2) { /* overflow */
++				queue_put_entry(tx_doneq, phys);
++				break;
++			}
++			mdelay(1);
++			mac->rxq_pkt -= destroy_buffer(mac->rxdoneq,
++					mac->rxq_pkt);
++		}
++		npe_mh_npe_loopback_mode(npe, mac->plat, 0);
++	}
++	/* Flush MAC TX fifo to drain the bogus packages */
++	mac_set_regbit(mac, MAC_CORE_CNTRL, CORE_TX_FIFO_FLUSH);
++	mac_reset_regbit(mac, MAC_RX_CNTRL1, RX_CNTRL1_RX_EN);
++	mac_reset_regbit(mac, MAC_TX_CNTRL1, TX_CNTRL1_TX_EN);
++	mac_reset_regbit(mac, MAC_RX_CNTRL1, RX_CNTRL1_LOOP_EN);
++	mac_reset_regbit(mac, MAC_CORE_CNTRL, CORE_TX_FIFO_FLUSH);
++	mac_reset_regbit(mac, MAC_CORE_CNTRL, CORE_TX_FIFO_FLUSH);
++}
++
++static int mac_remove(struct platform_device *pdev)
++{
++	struct net_device* dev = platform_get_drvdata(pdev);
++	struct mac_info *mac = netdev_priv(dev);
++
++	unregister_netdev(dev);
++
++	mac->rxq_pkt -= destroy_buffer(mac->rxq, mac->rxq_pkt);
++	if (mac->rxq_pkt)
++		drain_npe(mac);
++
++	mac->txq_pkt -= destroy_buffer(mac->txq, mac->txq_pkt);
++	mac->txq_pkt -= destroy_buffer(tx_doneq, mac->txq_pkt);
++
++	if (mac->rxq_pkt || mac->txq_pkt)
++		printk("Buffers lost in NPE: RX:%d, TX:%d\n",
++				mac->rxq_pkt,  mac->txq_pkt);
++
++	release_queue(mac->txq);
++	release_queue(mac->rxq);
++	release_queue(mac->rxdoneq);
++
++	flush_scheduled_work();
++	return_npe_dev(mac->npe_dev);
++
++	iounmap(mac->addr);
++	release_resource(mac->res);
++	platform_set_drvdata(pdev, NULL);
++	free_netdev(dev);
++	return 0;
++}
++
++static struct platform_driver ixp4xx_mac = {
++	.driver.name    = IXMAC_NAME,
++	.probe          = mac_probe,
++	.remove         = mac_remove,
++};
++
++static int __init init_mac(void)
++{
++	/* The TX done Queue handles skbs sent out by the NPE */
++	tx_doneq = request_queue(TX_DONE_QID, 128);
++	if (IS_ERR(tx_doneq)) {
++		printk(KERN_ERR "Error requesting Q: %d\n", TX_DONE_QID);
++		return -EBUSY;
++	}
++	return platform_driver_register(&ixp4xx_mac);
++}
++
++static void __exit finish_mac(void)
++{
++	platform_driver_unregister(&ixp4xx_mac);
++	if (tx_doneq) {
++		release_queue(tx_doneq);
++	}
++}
++
++module_init(init_mac);
++module_exit(finish_mac);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
++
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/npe.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/npe.c	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,291 @@
++
++#include <linux/ixp_npe.h>
++#include <asm/hardware.h>
++
++#define RESET_NPE_PARITY                0x0800
++#define PARITY_BIT_MASK             0x3F00FFFF
++#define CONFIG_CTRL_REG_MASK        0x3F3FFFFF
++#define MAX_RETRIES                    1000000
++#define NPE_PHYS_REG                        32
++#define RESET_MBST_VAL              0x0000F0F0
++#define NPE_REGMAP	            0x0000001E
++#define INSTR_WR_REG_SHORT          0x0000C000
++#define INSTR_WR_REG_BYTE           0x00004000
++#define MASK_ECS_REG_0_NEXTPC       0x1FFF0000
++
++#define INSTR_RD_FIFO               0x0F888220
++#define INSTR_RESET_MBOX            0x0FAC8210
++
++#define ECS_REG_0_LDUR                 8
++#define ECS_REG_1_CCTXT               16
++#define ECS_REG_1_SELCTXT              0
++
++#define ECS_BG_CTXT_REG_0           0x00
++#define ECS_BG_CTXT_REG_1           0x01
++#define ECS_BG_CTXT_REG_2           0x02
++#define ECS_PRI_1_CTXT_REG_0        0x04
++#define ECS_PRI_1_CTXT_REG_1        0x05
++#define ECS_PRI_1_CTXT_REG_2        0x06
++#define ECS_PRI_2_CTXT_REG_0        0x08
++#define ECS_PRI_2_CTXT_REG_1        0x09
++#define ECS_PRI_2_CTXT_REG_2        0x0A
++#define ECS_DBG_CTXT_REG_0          0x0C
++#define ECS_DBG_CTXT_REG_1          0x0D
++#define ECS_DBG_CTXT_REG_2          0x0E
++#define ECS_INSTRUCT_REG            0x11
++
++#define ECS_BG_CTXT_REG_0_RESET     0xA0000000
++#define ECS_BG_CTXT_REG_1_RESET     0x01000000
++#define ECS_BG_CTXT_REG_2_RESET     0x00008000
++#define ECS_PRI_1_CTXT_REG_0_RESET  0x20000080
++#define ECS_PRI_1_CTXT_REG_1_RESET  0x01000000
++#define ECS_PRI_1_CTXT_REG_2_RESET  0x00008000
++#define ECS_PRI_2_CTXT_REG_0_RESET  0x20000080
++#define ECS_PRI_2_CTXT_REG_1_RESET  0x01000000
++#define ECS_PRI_2_CTXT_REG_2_RESET  0x00008000
++#define ECS_DBG_CTXT_REG_0_RESET    0x20000000
++#define ECS_DBG_CTXT_REG_1_RESET    0x00000000
++#define ECS_DBG_CTXT_REG_2_RESET    0x001E0000
++#define ECS_INSTRUCT_REG_RESET      0x1003C00F
++
++static struct { u32 reg; u32 val; } ecs_reset[] =
++{
++    { ECS_BG_CTXT_REG_0,    ECS_BG_CTXT_REG_0_RESET },
++    { ECS_BG_CTXT_REG_1,    ECS_BG_CTXT_REG_1_RESET },
++    { ECS_BG_CTXT_REG_2,    ECS_BG_CTXT_REG_2_RESET },
++    { ECS_PRI_1_CTXT_REG_0, ECS_PRI_1_CTXT_REG_0_RESET },
++    { ECS_PRI_1_CTXT_REG_1, ECS_PRI_1_CTXT_REG_1_RESET },
++    { ECS_PRI_1_CTXT_REG_2, ECS_PRI_1_CTXT_REG_2_RESET },
++    { ECS_PRI_2_CTXT_REG_0, ECS_PRI_2_CTXT_REG_0_RESET },
++    { ECS_PRI_2_CTXT_REG_1, ECS_PRI_2_CTXT_REG_1_RESET },
++    { ECS_PRI_2_CTXT_REG_2, ECS_PRI_2_CTXT_REG_2_RESET },
++    { ECS_DBG_CTXT_REG_0,   ECS_DBG_CTXT_REG_0_RESET },
++    { ECS_DBG_CTXT_REG_1,   ECS_DBG_CTXT_REG_1_RESET },
++    { ECS_DBG_CTXT_REG_2,   ECS_DBG_CTXT_REG_2_RESET },
++    { ECS_INSTRUCT_REG,     ECS_INSTRUCT_REG_RESET }
++};
++
++/* actually I have no idea what I'm doing here !!
++ * I only rewrite the "reset" sequence the way Intel does it.
++ */
++
++static void npe_debg_preexec(struct npe_info *npe)
++{
++	u32 r = IX_NPEDL_MASK_ECS_DBG_REG_2_IF | IX_NPEDL_MASK_ECS_DBG_REG_2_IE;
++
++	npe->exec_count = npe_reg_read(npe, IX_NPEDL_REG_OFFSET_EXCT);
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCT, 0);
++	npe->ctx_reg2 = npe_read_ecs_reg(npe, ECS_DBG_CTXT_REG_2);
++	npe_write_ecs_reg(npe, ECS_DBG_CTXT_REG_2, npe->ctx_reg2 | r);
++}
++
++static void npe_debg_postexec(struct npe_info *npe)
++{
++	npe_write_ecs_reg(npe, ECS_DBG_CTXT_REG_0, 0);
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCT, npe->exec_count);
++	npe_write_ecs_reg(npe, ECS_DBG_CTXT_REG_2, npe->ctx_reg2);
++}
++
++static int
++npe_debg_inst_exec(struct npe_info *npe, u32 instr, u32 ctx, u32 ldur)
++{
++	u32 regval, wc;
++	int c = 0;
++
++	regval = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
++		(ldur << ECS_REG_0_LDUR);
++	npe_write_ecs_reg(npe, ECS_DBG_CTXT_REG_0 , regval);
++	/* set CCTXT at ECS DEBUG L3 to specify in which context
++	 * to execute the instruction
++	 */
++	regval = (ctx << ECS_REG_1_CCTXT) |
++		 (ctx << ECS_REG_1_SELCTXT);
++	npe_write_ecs_reg(npe, ECS_DBG_CTXT_REG_1, regval);
++
++	/* clear the pipeline */
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
++
++	/* load NPE instruction into the instruction register */
++	npe_write_ecs_reg(npe, ECS_INSTRUCT_REG, instr);
++	/* we need this value later to wait for
++	 * completion of NPE execution step
++	 */
++	wc = npe_reg_read(npe, IX_NPEDL_REG_OFFSET_WC);
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_STEP);
++
++	/* Watch Count register increments when NPE completes an instruction */
++	while (wc == npe_reg_read(npe, IX_NPEDL_REG_OFFSET_WC) &&
++			++c < MAX_RETRIES);
++
++	if (c >= MAX_RETRIES) {
++		printk(KERN_ERR "%s reset:npe_debg_inst_exec(): Timeout\n",
++				npe->plat->name);
++		return 1;
++	}
++	return 0;
++}
++
++static int npe_logical_reg_write8(struct npe_info *npe, u32 addr, u32 val)
++{
++	u32 instr;
++	val &= 0xff;
++	/* here we build the NPE assembler instruction:
++	 * mov8 d0, #0 */
++	instr = INSTR_WR_REG_BYTE |	/* OpCode */
++		addr << 9 |		/* base Operand */
++		(val & 0x1f) << 4 |	/* lower 5 bits to immediate data */
++		(val & ~0x1f) << (18-5);/* higher 3 bits to CoProc instr. */
++	/* and execute it */
++	return npe_debg_inst_exec(npe, instr, 0, 1);
++}
++
++static int npe_logical_reg_write16(struct npe_info *npe, u32 addr, u32 val)
++{
++	u32 instr;
++	/* here we build the NPE assembler instruction:
++	 * mov16 d0, #0 */
++	val &= 0xffff;
++	instr = INSTR_WR_REG_SHORT |	/* OpCode */
++		addr << 9 |		/* base Operand */
++		(val & 0x1f) << 4 |	/* lower 5 bits to immediate data */
++		(val & ~0x1f) << (18-5);/* higher 11 bits to CoProc instr. */
++	/* and execute it */
++	return npe_debg_inst_exec(npe, instr, 0, 1);
++}
++
++static int npe_logical_reg_write32(struct npe_info *npe, u32 addr, u32 val)
++{
++	/* write in 16 bit steps first the high and then the low value */
++	npe_logical_reg_write16(npe, addr, val >> 16);
++	return npe_logical_reg_write16(npe, addr+2, val & 0xffff);
++}
++
++void npe_reset(struct npe_info *npe)
++{
++	u32 reg, cfg_ctrl;
++	int i;
++	struct { u32 reset; int addr; int size; } ctx_reg[] = {
++		{ 0x80,  0x1b, 8  },
++		{ 0,     0x1c, 16 },
++		{ 0x820, 0x1e, 16 },
++		{ 0,     0x1f, 8  }
++	}, *cr;
++
++	cfg_ctrl = npe_reg_read(npe, IX_NPEDL_REG_OFFSET_CTL);
++	cfg_ctrl |= 0x3F000000;
++	/* disable the parity interrupt */
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_CTL, cfg_ctrl & PARITY_BIT_MASK);
++
++	npe_debg_preexec(npe);
++
++	/* clear the FIFOs */
++	while (npe_reg_read(npe, IX_NPEDL_REG_OFFSET_WFIFO) ==
++					IX_NPEDL_MASK_WFIFO_VALID);
++	while (npe_reg_read(npe, IX_NPEDL_REG_OFFSET_STAT) ==
++					IX_NPEDL_MASK_STAT_OFNE)
++	{
++		u32 reg;
++		reg = npe_reg_read(npe, IX_NPEDL_REG_OFFSET_FIFO);
++		printk("%s reset: Read FIFO:=%x\n", npe->plat->name, reg);
++	}
++	while (npe_reg_read(npe, IX_NPEDL_REG_OFFSET_STAT) ==
++					IX_NPEDL_MASK_STAT_IFNE) {
++		npe_debg_inst_exec(npe, INSTR_RD_FIFO, 0, 0);
++	}
++
++	/*  Reset the mailbox reg */
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_MBST, RESET_MBST_VAL);
++	npe_debg_inst_exec(npe, INSTR_RESET_MBOX, 0, 0);
++
++	/* Reset the physical registers in the NPE register file */
++	for (i=0; i<NPE_PHYS_REG; i++) {
++		npe_logical_reg_write16(npe, NPE_REGMAP, i >> 1);
++		npe_logical_reg_write32(npe, (i&1) *4, 0);
++	}
++
++	/* Reset the context store. Iterate over the 16 ctx s */
++	for(i=0; i<16; i++) {
++		for (reg=0; reg<4; reg++) {
++			/* There is no (STEVT) register for Context 0.
++			 * ignore if register=0 and ctx=0 */
++			if (!(reg || i))
++				continue;
++			 /* Context 0 has no STARTPC. Instead, this value is
++			  * used to set NextPC for Background ECS,
++			  * to set where NPE starts executing code
++			  */
++			if (!i && reg==1) {
++				u32 r;
++				r = npe_read_ecs_reg(npe, ECS_BG_CTXT_REG_0);
++				r &= ~MASK_ECS_REG_0_NEXTPC;
++				r |= (cr->reset << 16) & MASK_ECS_REG_0_NEXTPC;
++				continue;
++			}
++			cr = ctx_reg + reg;
++			switch (cr->size) {
++				case 8:
++					npe_logical_reg_write8(npe, cr->addr,
++						cr->reset);
++					break;
++				case 16:
++					npe_logical_reg_write16(npe, cr->addr,
++						cr->reset);
++			}
++		}
++	}
++	npe_debg_postexec(npe);
++
++	for (i=0; i< ARRAY_SIZE(ecs_reset); i++) {
++		npe_write_ecs_reg(npe, ecs_reset[i].reg, ecs_reset[i].val);
++	}
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
++
++	for (i=IX_NPEDL_REG_OFFSET_EXCT; i<=IX_NPEDL_REG_OFFSET_AP3; i+=4) {
++		npe_reg_write(npe, i, 0);
++	}
++
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_WC, 0);
++
++	reg = *IXP4XX_EXP_CFG2;
++	reg |= 0x800 << npe->plat->id;  /* IX_FUSE_NPE[ABC] */
++	*IXP4XX_EXP_CFG2 = reg;
++	reg &= ~(0x800 << npe->plat->id);  /* IX_FUSE_NPE[ABC] */
++	*IXP4XX_EXP_CFG2 = reg;
++
++	npe_stop(npe);
++
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_CTL,
++			cfg_ctrl & CONFIG_CTRL_REG_MASK);
++	npe->loaded = 0;
++}
++
++
++void npe_stop(struct npe_info *npe)
++{
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_STOP);
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
++}
++
++static void npe_reset_active(struct npe_info *npe, u32 reg)
++{
++	u32 regval;
++
++	regval = npe_read_ecs_reg(npe, reg);
++	regval &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
++	npe_write_ecs_reg(npe, reg, regval);
++}
++
++void npe_start(struct npe_info *npe)
++{
++	npe_reset_active(npe, IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
++	npe_reset_active(npe, IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
++	npe_reset_active(npe, IX_NPEDL_ECS_DBG_CTXT_REG_0);
++
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
++	npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_START);
++}
++
++EXPORT_SYMBOL(npe_stop);
++EXPORT_SYMBOL(npe_start);
++EXPORT_SYMBOL(npe_reset);
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/npe_mh.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/npe_mh.c	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,170 @@
++/*
++ * npe_mh.c - NPE message handler.
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#include <linux/ixp_npe.h>
++#include <linux/slab.h>
++
++#define MAX_RETRY 200
++
++struct npe_mh_msg {
++	union {
++		u8 byte[8]; /* Very desciptive name, I know ... */
++		u32 data[2];
++	} u;
++};
++
++/*
++ * The whole code in this function must be reworked.
++ * It is in a state that works but is not rock solid
++ */
++static int send_message(struct npe_info *npe, struct npe_mh_msg *msg)
++{
++	int i,j;
++	u32 send[2], recv[2];
++
++	for (i=0; i<2; i++)
++		send[i] = be32_to_cpu(msg->u.data[i]);
++
++	if ((npe_reg_read(npe, IX_NPEDL_REG_OFFSET_STAT) &
++				IX_NPEMH_NPE_STAT_IFNE))
++		return -1;
++
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_FIFO, send[0]);
++	for(i=0; i<MAX_RETRY; i++) {
++		/* if the IFNF status bit is unset then the inFIFO is full */
++		if (npe_reg_read(npe, IX_NPEDL_REG_OFFSET_STAT) &
++				IX_NPEMH_NPE_STAT_IFNF)
++			break;
++	}
++	if (i>=MAX_RETRY)
++		return -1;
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_FIFO, send[1]);
++	i=0;
++	while (!(npe_reg_read(npe, IX_NPEDL_REG_OFFSET_STAT) &
++					IX_NPEMH_NPE_STAT_OFNE)) {
++		if (i++>MAX_RETRY) {
++			printk("Waiting for Output FIFO NotEmpty failed\n");
++			return -1;
++		}
++	}
++	//printk("Output FIFO Not Empty. Loops: %d\n", i);
++	j=0;
++	while (npe_reg_read(npe, IX_NPEDL_REG_OFFSET_STAT) &
++					IX_NPEMH_NPE_STAT_OFNE) {
++		recv[j&1] = npe_reg_read(npe,IX_NPEDL_REG_OFFSET_FIFO);
++		j++;
++	}
++	if ((recv[0] != send[0]) || (recv[1] != send[1])) {
++		if (send[0] || send[1]) {
++			/* all CMDs return the complete message as answer,
++			 * only GETSTATUS returns the ImageID of the NPE
++			 */
++			printk("Unexpected answer: "
++				"Send %08x:%08x Ret %08x:%08x\n",
++				send[0], send[1], recv[0], recv[1]);
++		}
++	}
++	return 0;
++}
++
++#define CMD  0
++#define PORT 1
++#define MAC  2
++
++#define IX_ETHNPE_NPE_GETSTATUS			0x00
++#define IX_ETHNPE_EDB_SETPORTADDRESS            0x01
++#define IX_ETHNPE_GETSTATS			0x04
++#define IX_ETHNPE_RESETSTATS			0x05
++#define IX_ETHNPE_FW_SETFIREWALLMODE            0x0E
++#define IX_ETHNPE_VLAN_SETRXQOSENTRY            0x0B
++#define IX_ETHNPE_SETLOOPBACK_MODE		0x12
++
++#define logical_id(mp) (((mp)->npe_id << 4) | ((mp)->port_id & 0xf))
++
++int npe_mh_status(struct npe_info *npe)
++{
++	struct npe_mh_msg msg;
++
++	memset(&msg, 0, sizeof(msg));
++	msg.u.byte[CMD] = IX_ETHNPE_NPE_GETSTATUS;
++	return send_message(npe, &msg);
++}
++
++int npe_mh_setportaddr(struct npe_info *npe, struct mac_plat_info *mp,
++		u8 *macaddr)
++{
++	struct npe_mh_msg msg;
++
++	msg.u.byte[CMD] = IX_ETHNPE_EDB_SETPORTADDRESS;
++	msg.u.byte[PORT] = mp->eth_id;
++	memcpy(msg.u.byte + MAC, macaddr, 6);
++
++	return send_message(npe, &msg);
++}
++
++int npe_mh_disable_firewall(struct npe_info *npe, struct mac_plat_info *mp)
++{
++	struct npe_mh_msg msg;
++
++	memset(&msg, 0, sizeof(msg));
++	msg.u.byte[CMD] = IX_ETHNPE_FW_SETFIREWALLMODE;
++	msg.u.byte[PORT] = logical_id(mp);
++
++	return send_message(npe, &msg);
++}
++
++int npe_mh_npe_loopback_mode(struct npe_info *npe, struct mac_plat_info *mp,
++		int enable)
++{
++	struct npe_mh_msg msg;
++
++	memset(&msg, 0, sizeof(msg));
++	msg.u.byte[CMD] = IX_ETHNPE_SETLOOPBACK_MODE;
++	msg.u.byte[PORT] = logical_id(mp);
++	msg.u.byte[3] = enable ? 1 : 0;
++
++	return send_message(npe, &msg);
++}
++
++int npe_mh_set_rxqid(struct npe_info *npe, struct mac_plat_info *mp, int qid)
++{
++	struct npe_mh_msg msg;
++	int i, ret;
++
++	memset(&msg, 0, sizeof(msg));
++	msg.u.byte[CMD] = IX_ETHNPE_VLAN_SETRXQOSENTRY;
++	msg.u.byte[PORT] = logical_id(mp);
++	msg.u.byte[5] = qid | 0x80;
++	msg.u.byte[7] = qid<<4;
++	for(i=0; i<8; i++) {
++		msg.u.byte[3] = i;
++		if ((ret = send_message(npe, &msg)))
++			return ret;
++	}
++	return 0;
++}
++
++int npe_mh_get_stats(struct npe_info *npe, struct mac_plat_info *mp, u32 phys,
++		int reset)
++{
++	struct npe_mh_msg msg;
++	memset(&msg, 0, sizeof(msg));
++	msg.u.byte[CMD] = reset ? IX_ETHNPE_RESETSTATS : IX_ETHNPE_GETSTATS;
++	msg.u.byte[PORT] = logical_id(mp);
++	msg.u.data[1] = cpu_to_npe32(cpu_to_be32(phys));
++
++	return send_message(npe, &msg);
++}
++
++
++EXPORT_SYMBOL(npe_mh_status);
++EXPORT_SYMBOL(npe_mh_setportaddr);
++EXPORT_SYMBOL(npe_mh_disable_firewall);
++EXPORT_SYMBOL(npe_mh_set_rxqid);
++EXPORT_SYMBOL(npe_mh_npe_loopback_mode);
++EXPORT_SYMBOL(npe_mh_get_stats);
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/phy.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/phy.c	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,113 @@
++/*
++ * phy.c - MDIO functions and mii initialisation
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++
++#include <linux/mutex.h>
++#include "mac.h"
++
++#define MAX_PHYS (1<<5)
++
++/*
++ * We must always use the same MAC for acessing the MDIO
++ * We may not use each MAC for its PHY :-(
++ */
++
++static struct net_device *phy_dev = NULL;
++static struct mutex mtx;
++
++/* here we remember if the PHY is alive, to avoid log dumping */
++static int phy_works[MAX_PHYS];
++
++int mdio_read_register(struct net_device *dev, int phy_addr, int phy_reg)
++{
++	struct mac_info *mac;
++	u32 cmd, reg;
++	int cnt = 0;
++
++	if (!phy_dev)
++		return 0;
++
++	mac = netdev_priv(phy_dev);
++	cmd = mdio_cmd(phy_addr, phy_reg);
++	mutex_lock_interruptible(&mtx);
++	mac_mdio_cmd_write(mac, cmd);
++	while((cmd = mac_mdio_cmd_read(mac)) & MII_GO) {
++		if (++cnt >= 100) {
++			printk("%s: PHY[%d] access failed\n",
++				dev->name, phy_addr);
++			break;
++		}
++		schedule();
++	}
++	reg = mac_mdio_status_read(mac);
++	mutex_unlock(&mtx);
++	if (reg & MII_READ_FAIL) {
++		if (phy_works[phy_addr]) {
++			printk("%s: PHY[%d] unresponsive\n",
++					dev->name, phy_addr);
++		}
++		reg = 0;
++		phy_works[phy_addr] = 0;
++	} else {
++		if ( !phy_works[phy_addr]) {
++			printk("%s: PHY[%d] responsive again\n",
++				dev->name, phy_addr);
++		}
++		phy_works[phy_addr] = 1;
++	}
++	return reg & 0xffff;
++}
++
++void
++mdio_write_register(struct net_device *dev, int phy_addr, int phy_reg, int val)
++{
++	struct mac_info *mac;
++	u32 cmd;
++	int cnt=0;
++
++	if (!phy_dev)
++		return;
++
++	mac = netdev_priv(phy_dev);
++	cmd = mdio_cmd(phy_addr, phy_reg) | MII_WRITE | val;
++
++	mutex_lock_interruptible(&mtx);
++	mac_mdio_cmd_write(mac, cmd);
++	while((cmd = mac_mdio_cmd_read(mac)) & MII_GO) {
++		if (++cnt >= 100) {
++			printk("%s: PHY[%d] access failed\n",
++					dev->name, phy_addr);
++			break;
++		}
++		schedule();
++	}
++	mutex_unlock(&mtx);
++}
++
++void init_mdio(struct net_device *dev, int phy_id)
++{
++	struct mac_info *mac = netdev_priv(dev);
++	int i;
++
++	/* All phy operations should use the same MAC
++	 * (my experience)
++	 */
++	if (mac->plat->eth_id == 0) {
++		mutex_init(&mtx);
++		phy_dev = dev;
++		for (i=0; i<MAX_PHYS; i++)
++			phy_works[i] = 1;
++	}
++	mac->mii.dev = dev;
++	mac->mii.phy_id = phy_id;
++	mac->mii.phy_id_mask = MAX_PHYS - 1;
++	mac->mii.reg_num_mask = 0x1f;
++	mac->mii.mdio_read = mdio_read_register;
++	mac->mii.mdio_write = mdio_write_register;
++}
++
+Index: linux-2.6.21-rc1-arm/drivers/net/ixp4xx/ucode_dl.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/drivers/net/ixp4xx/ucode_dl.c	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,479 @@
++/*
++ * ucode_dl.c - provide an NPE device and a char-dev for microcode download
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/miscdevice.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/firmware.h>
++#include <linux/dma-mapping.h>
++#include <linux/byteorder/swab.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++
++#include <linux/ixp_npe.h>
++
++#define IXNPE_VERSION "IXP4XX NPE driver Version 0.3.0"
++
++#define DL_MAGIC 0xfeedf00d
++#define DL_MAGIC_SWAP 0x0df0edfe
++
++#define EOF_BLOCK 0xf
++#define IMG_SIZE(image) (((image)->size * sizeof(u32)) + \
++		sizeof(struct dl_image))
++
++#define BT_INSTR 0
++#define BT_DATA 1
++
++enum blk_type {
++	instruction,
++	data,
++};
++
++struct dl_block {
++	u32 type;
++	u32 offset;
++};
++
++struct dl_image {
++	u32 magic;
++	u32 id;
++	u32 size;
++	union {
++		u32 data[0];
++		struct dl_block block[0];
++	} u;
++};
++
++struct dl_codeblock {
++	u32 npe_addr;
++	u32 size;
++	u32 data[0];
++};
++
++static struct platform_driver ixp4xx_npe_driver;
++
++static int match_by_npeid(struct device *dev, void *id)
++{
++	struct npe_info *npe = dev_get_drvdata(dev);
++	if (!npe->plat)
++		return 0;
++	return (npe->plat->id == *(int*)id);
++}
++
++struct device *get_npe_by_id(int id)
++{
++	struct device *dev = driver_find_device(&ixp4xx_npe_driver.driver,
++			NULL, &id, match_by_npeid);
++	if (dev) {
++		struct npe_info *npe = dev_get_drvdata(dev);
++		if (!try_module_get(THIS_MODULE)) {
++			 put_device(dev);
++			 return NULL;
++		}
++		npe->usage++;
++	}
++	return dev;
++}
++
++void return_npe_dev(struct device *dev)
++{
++	struct npe_info *npe = dev_get_drvdata(dev);
++	put_device(dev);
++	module_put(THIS_MODULE);
++	npe->usage--;
++}
++
++static int
++download_block(struct npe_info *npe, struct dl_codeblock *cb, unsigned type)
++{
++	int i;
++	int cmd;
++
++	switch (type) {
++	case BT_DATA:
++		cmd = IX_NPEDL_EXCTL_CMD_WR_DATA_MEM;
++		if (cb->npe_addr + cb->size > npe->plat->data_size) {
++			printk(KERN_INFO "Data size too large: %d+%d > %d\n",
++				cb->npe_addr, cb->size, npe->plat->data_size);
++			return -EIO;
++		}
++		break;
++	case BT_INSTR:
++		cmd = IX_NPEDL_EXCTL_CMD_WR_INS_MEM;
++		if (cb->npe_addr + cb->size > npe->plat->inst_size) {
++			printk(KERN_INFO "Instr size too large: %d+%d > %d\n",
++				cb->npe_addr, cb->size, npe->plat->inst_size);
++			return -EIO;
++		}
++		break;
++	default:
++		printk(KERN_INFO "Unknown CMD: %d\n", type);
++		return -EIO;
++	}
++
++	for (i=0; i < cb->size; i++) {
++		npe_write_cmd(npe, cb->npe_addr + i, cb->data[i], cmd);
++	}
++
++	return 0;
++}
++
++static int store_npe_image(struct dl_image *image, struct device *dev)
++{
++	struct dl_block *blk;
++	struct dl_codeblock *cb;
++	struct npe_info *npe;
++	int ret=0;
++
++	if (!dev) {
++		dev = get_npe_by_id( (image->id >> 24) & 0xf);
++		return_npe_dev(dev);
++	}
++	if (!dev)
++		return -ENODEV;
++
++	npe = dev_get_drvdata(dev);
++	if (npe->loaded && (npe->usage > 0)) {
++		printk(KERN_INFO "Cowardly refusing to reload an Image "
++			"into the used and running %s\n", npe->plat->name);
++		return 0; /* indicate success anyway... */
++	}
++	if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xf)) {
++		printk(KERN_INFO "IXP46x NPE image ignored on IXP42x\n");
++		return -EIO;
++	}
++
++	npe_stop(npe);
++	npe_reset(npe);
++
++	for (blk = image->u.block; blk->type != EOF_BLOCK; blk++) {
++		if (blk->offset > image->size) {
++			printk(KERN_INFO "Block offset out of range\n");
++			return -EIO;
++		}
++		cb = (struct dl_codeblock*)&image->u.data[blk->offset];
++		if (blk->offset + cb->size + 2 > image->size) {
++			printk(KERN_INFO "Codeblock size out of range\n");
++			return -EIO;
++		}
++		if ((ret = download_block(npe, cb, blk->type)))
++			return ret;
++	}
++	*(u32*)npe->img_info = cpu_to_be32(image->id);
++	npe_start(npe);
++
++	printk(KERN_INFO "Image loaded to %s Func:%x, Rel: %x:%x, Status: %x\n",
++			npe->plat->name, npe->img_info[1], npe->img_info[2],
++			npe->img_info[3], npe_status(npe));
++	if (npe_mh_status(npe)) {
++		printk(KERN_ERR "%s not responding\n", npe->plat->name);
++	}
++	npe->loaded = 1;
++	return 0;
++}
++
++static int ucode_open(struct inode *inode, struct file *file)
++{
++	file->private_data = kmalloc(sizeof(struct dl_image), GFP_KERNEL);
++	if (!file->private_data)
++		return -ENOMEM;
++	return 0;
++}
++
++static int ucode_close(struct inode *inode, struct file *file)
++{
++	kfree(file->private_data);
++	return 0;
++}
++
++static ssize_t ucode_write(struct file *file, const char __user *buf,
++		size_t count, loff_t *ppos)
++{
++	union {
++		char *data;
++		struct dl_image *image;
++	} u;
++	const char __user *cbuf = buf;
++
++	u.data = file->private_data;
++
++	while (count) {
++		int len;
++		if (*ppos < sizeof(struct dl_image)) {
++			len = sizeof(struct dl_image) - *ppos;
++			len = len > count ? count : len;
++			if (copy_from_user(u.data + *ppos, cbuf, len))
++				return -EFAULT;
++			count -= len;
++			*ppos += len;
++			cbuf += len;
++			continue;
++		} else if (*ppos == sizeof(struct dl_image)) {
++			void *data;
++			if (u.image->magic == DL_MAGIC_SWAP) {
++				printk(KERN_INFO "swapped image found\n");
++				u.image->id = swab32(u.image->id);
++				u.image->size = swab32(u.image->size);
++			} else if (u.image->magic != DL_MAGIC) {
++				printk(KERN_INFO "Bad magic:%x\n",
++						u.image->magic);
++				return -EFAULT;
++			}
++			len = IMG_SIZE(u.image);
++			data = kmalloc(len, GFP_KERNEL);
++			if (!data)
++				return -ENOMEM;
++			memcpy(data, u.data, *ppos);
++			kfree(u.data);
++			u.data = (char*)data;
++			file->private_data = data;
++		}
++		len = IMG_SIZE(u.image) - *ppos;
++		len = len > count ? count : len;
++		if (copy_from_user(u.data + *ppos, cbuf, len))
++			return -EFAULT;
++		count -= len;
++		*ppos += len;
++		cbuf += len;
++		if (*ppos == IMG_SIZE(u.image)) {
++			int ret, i;
++			*ppos = 0;
++			if (u.image->magic == DL_MAGIC_SWAP) {
++				for (i=0; i<u.image->size; i++) {
++					u.image->u.data[i] =
++						swab32(u.image->u.data[i]);
++				}
++				u.image->magic = swab32(u.image->magic);
++			}
++			ret = store_npe_image(u.image, NULL);
++			if (ret) {
++				printk(KERN_INFO "Error in NPE image: %x\n",
++					u.image->id);
++				return ret;
++			}
++		}
++	}
++	return (cbuf-buf);
++}
++
++static void npe_firmware_probe(struct device *dev)
++{
++#if (defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)) \
++	&& defined(MODULE)
++	const struct firmware *fw_entry;
++	struct npe_info *npe = dev_get_drvdata(dev);
++	struct dl_image *image;
++	int ret = -1, i;
++
++	if (request_firmware(&fw_entry, npe->plat->name, dev) != 0) {
++		return;
++	}
++	image = (struct dl_image*)fw_entry->data;
++	/* Sanity checks */
++	if (fw_entry->size < sizeof(struct dl_image)) {
++		printk(KERN_ERR "Firmware error: too small\n");
++		goto out;
++	}
++	if (image->magic == DL_MAGIC_SWAP) {
++		printk(KERN_INFO "swapped image found\n");
++		image->id = swab32(image->id);
++		image->size = swab32(image->size);
++	} else if (image->magic != DL_MAGIC) {
++		printk(KERN_ERR "Bad magic:%x\n", image->magic);
++		goto out;
++	}
++	if (IMG_SIZE(image) != fw_entry->size) {
++		printk(KERN_ERR "Firmware error: bad size\n");
++		goto out;
++	}
++	if (((image->id >> 24) & 0xf) != npe->plat->id) {
++		printk(KERN_ERR "NPE id missmatch\n");
++		goto out;
++	}
++	if (image->magic == DL_MAGIC_SWAP) {
++		for (i=0; i<image->size; i++) {
++			image->u.data[i] = swab32(image->u.data[i]);
++		}
++		image->magic = swab32(image->magic);
++	}
++
++	ret = store_npe_image(image, dev);
++out:
++	if (ret) {
++		printk(KERN_ERR "Error downloading Firmware for %s\n",
++				npe->plat->name);
++	}
++	release_firmware(fw_entry);
++#endif
++}
++
++static void disable_npe_irq(struct npe_info *npe)
++{
++	u32 reg;
++	reg = npe_reg_read(npe, IX_NPEDL_REG_OFFSET_CTL);
++	reg &= ~(IX_NPEMH_NPE_CTL_OFE | IX_NPEMH_NPE_CTL_IFE);
++	reg |= IX_NPEMH_NPE_CTL_OFEWE | IX_NPEMH_NPE_CTL_IFEWE;
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_CTL, reg);
++}
++
++static ssize_t show_npe_state(struct device *dev, struct device_attribute *attr,
++		char *buf)
++{
++	struct npe_info *npe = dev_get_drvdata(dev);
++
++	strcpy(buf, npe_status(npe) & IX_NPEDL_EXCTL_STATUS_RUN ?
++			"start\n" : "stop\n");
++	return strlen(buf);
++}
++
++static ssize_t set_npe_state(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t count)
++{
++	struct npe_info *npe = dev_get_drvdata(dev);
++
++	if (npe->usage) {
++		printk("%s in use: read-only\n", npe->plat->name);
++		return count;
++	}
++	if (!strncmp(buf, "start", 5)) {
++		npe_start(npe);
++	}
++	if (!strncmp(buf, "stop", 4)) {
++		npe_stop(npe);
++	}
++	if (!strncmp(buf, "reset", 5)) {
++		npe_stop(npe);
++		npe_reset(npe);
++	}
++	return count;
++}
++
++static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, show_npe_state, set_npe_state);
++
++static int npe_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct npe_info *npe;
++	struct npe_plat_data *plat = pdev->dev.platform_data;
++	int err, size, ret=0;
++
++	if (!(res = platform_get_resource(pdev, IORESOURCE_MEM, 0)))
++		return -EIO;
++
++	if (!(npe = kzalloc(sizeof(struct npe_info), GFP_KERNEL)))
++		return -ENOMEM;
++
++	size = res->end - res->start +1;
++	npe->res = request_mem_region(res->start, size, plat->name);
++	if (!npe->res) {
++		ret = -EBUSY;
++		printk(KERN_ERR "Failed to get memregion(%x, %x)\n",
++				res->start, size);
++		goto out_free;
++	}
++
++	npe->addr = ioremap(res->start, size);
++	if (!npe->addr) {
++		ret = -ENOMEM;
++		printk(KERN_ERR "Failed to ioremap(%x, %x)\n",
++				res->start, size);
++		goto out_rel;
++	}
++
++	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
++
++	platform_set_drvdata(pdev, npe);
++
++	err = device_create_file(&pdev->dev, &dev_attr_state);
++	if (err)
++		goto out_rel;
++
++	npe->plat = plat;
++	disable_npe_irq(npe);
++	npe->usage = 0;
++	npe_reset(npe);
++	npe_firmware_probe(&pdev->dev);
++
++	return 0;
++
++out_rel:
++	release_resource(npe->res);
++out_free:
++	kfree(npe);
++	return ret;
++}
++
++static struct file_operations ucode_dl_fops = {
++	.owner		= THIS_MODULE,
++	.write		= ucode_write,
++	.open		= ucode_open,
++	.release	= ucode_close,
++};
++
++static struct miscdevice ucode_dl_dev = {
++	.minor	= MICROCODE_MINOR,
++	.name	= "ixp4xx_ucode",
++	.fops	= &ucode_dl_fops,
++};
++
++static int npe_remove(struct platform_device *pdev)
++{
++	struct npe_info *npe = platform_get_drvdata(pdev);
++
++	device_remove_file(&pdev->dev, &dev_attr_state);
++
++	iounmap(npe->addr);
++	release_resource(npe->res);
++	kfree(npe);
++	return 0;
++}
++
++static struct platform_driver ixp4xx_npe_driver = {
++	.driver = {
++		.name	= "ixp4xx_npe",
++		.owner	= THIS_MODULE,
++	},
++	.probe	= npe_probe,
++	.remove	= npe_remove,
++};
++
++static int __init init_npedriver(void)
++{
++	int ret;
++	if ((ret = misc_register(&ucode_dl_dev))){
++		printk(KERN_ERR "Failed to register misc device %d\n",
++				MICROCODE_MINOR);
++		return ret;
++	}
++	if ((ret = platform_driver_register(&ixp4xx_npe_driver)))
++		misc_deregister(&ucode_dl_dev);
++	else
++		printk(KERN_INFO IXNPE_VERSION " initialized\n");
++
++	return ret;
++
++}
++
++static void __exit finish_npedriver(void)
++{
++	misc_deregister(&ucode_dl_dev);
++	platform_driver_unregister(&ixp4xx_npe_driver);
++}
++
++module_init(init_npedriver);
++module_exit(finish_npedriver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
++
++EXPORT_SYMBOL(get_npe_by_id);
++EXPORT_SYMBOL(return_npe_dev);
+Index: linux-2.6.21-rc1-arm/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h	2007-02-21 02:24:18.000000000 -0800
++++ linux-2.6.21-rc1-arm/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h	2007-02-21 02:24:35.000000000 -0800
+@@ -22,6 +22,8 @@
+ #ifndef _ASM_ARM_IXP4XX_H_
+ #define _ASM_ARM_IXP4XX_H_
+ 
++#include "npe_regs.h"
++
+ /*
+  * IXP4xx Linux Memory Map:
+  *
+@@ -44,6 +46,12 @@
+  */
+ 
+ /*
++ * PCI Memory Space
++ */
++#define IXP4XX_PCIMEM_BASE_PHYS		(0x48000000)
++#define IXP4XX_PCIMEM_REGION_SIZE	(0x04000000)
++#define IXP4XX_PCIMEM_BAR_SIZE		(0x01000000)
++/*
+  * Queue Manager
+  */
+ #define IXP4XX_QMGR_BASE_PHYS		(0x60000000)
+@@ -322,7 +330,13 @@
+ #define PCI_ATPDMA0_LENADDR_OFFSET  0x48
+ #define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
+ #define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
+-#define PCI_ATPDMA1_LENADDR_OFFSET	0x54
++#define PCI_ATPDMA1_LENADDR_OFFSET  0x54
++#define PCI_PTADMA0_AHBADDR_OFFSET  0x58
++#define PCI_PTADMA0_PCIADDR_OFFSET  0x5c
++#define PCI_PTADMA0_LENADDR_OFFSET  0x60
++#define PCI_PTADMA1_AHBADDR_OFFSET  0x64
++#define PCI_PTADMA1_PCIADDR_OFFSET  0x68
++#define PCI_PTADMA1_LENADDR_OFFSET  0x6c
+ 
+ /*
+  * PCI Control/Status Registers
+@@ -351,6 +365,12 @@
+ #define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
+ #define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
+ #define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
++#define PCI_PTADMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_PTADMA0_AHBADDR_OFFSET)
++#define PCI_PTADMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_PTADMA0_PCIADDR_OFFSET)
++#define PCI_PTADMA0_LENADDR     IXP4XX_PCI_CSR(PCI_PTADMA0_LENADDR_OFFSET)
++#define PCI_PTADMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_PTADMA1_AHBADDR_OFFSET)
++#define PCI_PTADMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_PTADMA1_PCIADDR_OFFSET)
++#define PCI_PTADMA1_LENADDR     IXP4XX_PCI_CSR(PCI_PTADMA1_LENADDR_OFFSET)
+ 
+ /*
+  * PCI register values and bit definitions 
+@@ -607,6 +627,34 @@
+ 
+ #define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
+ 
++
++/* Fuse Bits of IXP_EXP_CFG2 */
++#define IX_FUSE_RCOMP   (1 << 0)
++#define IX_FUSE_USB     (1 << 1)
++#define IX_FUSE_HASH    (1 << 2)
++#define IX_FUSE_AES     (1 << 3)
++#define IX_FUSE_DES     (1 << 4)
++#define IX_FUSE_HDLC    (1 << 5)
++#define IX_FUSE_AAL     (1 << 6)
++#define IX_FUSE_HSS     (1 << 7)
++#define IX_FUSE_UTOPIA  (1 << 8)
++#define IX_FUSE_ETH0    (1 << 9)
++#define IX_FUSE_ETH1    (1 << 10)
++#define IX_FUSE_NPEA    (1 << 11)
++#define IX_FUSE_NPEB    (1 << 12)
++#define IX_FUSE_NPEC    (1 << 13)
++#define IX_FUSE_PCI     (1 << 14)
++#define IX_FUSE_ECC     (1 << 15)
++#define IX_FUSE_UTOPIA_PHY_LIMIT  (3 << 16)
++#define IX_FUSE_USB_HOST          (1 << 18)
++#define IX_FUSE_NPEA_ETH          (1 << 19)
++#define IX_FUSE_NPEB_ETH          (1 << 20)
++#define IX_FUSE_RSA               (1 << 21)
++#define IX_FUSE_XSCALE_MAX_FREQ   (3 << 22)
++
++#define IX_FUSE_IXP46X_ONLY IX_FUSE_XSCALE_MAX_FREQ | IX_FUSE_RSA | \
++	IX_FUSE_NPEB_ETH | IX_FUSE_NPEA_ETH | IX_FUSE_USB_HOST | IX_FUSE_ECC
++
+ #ifndef __ASSEMBLY__
+ static inline int cpu_is_ixp46x(void)
+ {
+@@ -620,6 +668,15 @@
+ #endif
+ 	return 0;
+ }
++
++static inline u32 ix_fuse(void)
++{
++	unsigned int fuses = ~(*IXP4XX_EXP_CFG2);
++	if (!cpu_is_ixp46x())
++		fuses &= ~IX_FUSE_IXP46X_ONLY;
++
++	return fuses;
++}
+ #endif
+ 
+ #endif
+Index: linux-2.6.21-rc1-arm/include/asm-arm/arch-ixp4xx/npe_regs.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/include/asm-arm/arch-ixp4xx/npe_regs.h	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,82 @@
++#ifndef NPE_REGS_H
++#define NPE_REGS_H
++
++/* Execution Address  */
++#define IX_NPEDL_REG_OFFSET_EXAD             0x00
++/* Execution Data */
++#define IX_NPEDL_REG_OFFSET_EXDATA           0x04
++/* Execution Control */
++#define IX_NPEDL_REG_OFFSET_EXCTL            0x08
++/* Execution Count */
++#define IX_NPEDL_REG_OFFSET_EXCT             0x0C
++/* Action Point 0 */
++#define IX_NPEDL_REG_OFFSET_AP0              0x10
++/* Action Point 1 */
++#define IX_NPEDL_REG_OFFSET_AP1              0x14
++/* Action Point 2 */
++#define IX_NPEDL_REG_OFFSET_AP2              0x18
++/* Action Point 3 */
++#define IX_NPEDL_REG_OFFSET_AP3              0x1C
++/* Watchpoint FIFO */
++#define IX_NPEDL_REG_OFFSET_WFIFO            0x20
++/* Watch Count */
++#define IX_NPEDL_REG_OFFSET_WC               0x24
++/* Profile Count */
++#define IX_NPEDL_REG_OFFSET_PROFCT           0x28
++
++/* Messaging Status */
++#define IX_NPEDL_REG_OFFSET_STAT	     0x2C
++/* Messaging Control */
++#define IX_NPEDL_REG_OFFSET_CTL	             0x30
++/* Mailbox Status */
++#define IX_NPEDL_REG_OFFSET_MBST	     0x34
++/* messaging in/out FIFO */
++#define IX_NPEDL_REG_OFFSET_FIFO	     0x38
++
++
++#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF       0x00100000
++#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE       0x00080000
++#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE       0x80000000
++
++#define IX_NPEDL_EXCTL_CMD_NPE_STEP          0x01
++#define IX_NPEDL_EXCTL_CMD_NPE_START         0x02
++#define IX_NPEDL_EXCTL_CMD_NPE_STOP          0x03
++#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE      0x04
++#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT   0x0C
++#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM        0x10
++#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM        0x11
++#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM       0x12
++#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM       0x13
++#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG        0x14
++#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG        0x15
++
++#define IX_NPEDL_EXCTL_STATUS_RUN            0x80000000
++#define IX_NPEDL_EXCTL_STATUS_STOP           0x40000000
++#define IX_NPEDL_EXCTL_STATUS_CLEAR          0x20000000
++
++#define IX_NPEDL_MASK_WFIFO_VALID            0x80000000
++#define IX_NPEDL_MASK_STAT_OFNE              0x00010000
++#define IX_NPEDL_MASK_STAT_IFNE              0x00080000
++
++#define IX_NPEDL_ECS_DBG_CTXT_REG_0          0x0C
++#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0        0x04
++#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0        0x08
++
++/* NPE control register bit definitions */
++#define IX_NPEMH_NPE_CTL_OFE   (1 << 16) /**< OutFifoEnable */
++#define IX_NPEMH_NPE_CTL_IFE   (1 << 17) /**< InFifoEnable */
++#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */
++#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */
++
++/* NPE status register bit definitions */
++#define IX_NPEMH_NPE_STAT_OFNE  (1 << 16) /**< OutFifoNotEmpty */
++#define IX_NPEMH_NPE_STAT_IFNF  (1 << 17) /**< InFifoNotFull */
++#define IX_NPEMH_NPE_STAT_OFNF  (1 << 18) /**< OutFifoNotFull */
++#define IX_NPEMH_NPE_STAT_IFNE  (1 << 19) /**< InFifoNotEmpty */
++#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */
++#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */
++#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */
++#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */
++
++#endif
++
+Index: linux-2.6.21-rc1-arm/include/asm-arm/arch-ixp4xx/platform.h
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/include/asm-arm/arch-ixp4xx/platform.h	2007-02-21 02:24:18.000000000 -0800
++++ linux-2.6.21-rc1-arm/include/asm-arm/arch-ixp4xx/platform.h	2007-02-21 02:24:35.000000000 -0800
+@@ -86,6 +86,25 @@
+ 	unsigned long scl_pin;
+ };
+ 
++struct npe_plat_data {
++	const char *name;
++	int data_size;
++	int inst_size;
++	int id;		/* Node ID */
++};
++
++struct mac_plat_info {
++	int npe_id;	/* Node ID of the NPE for this port */
++	int port_id;	/* Port ID for NPE-B @ ixp465 */
++	int eth_id;	/* Physical ID */
++	int phy_id;	/* ID of the connected PHY (PCB/platform dependent) */
++	int rxq_id;	/* Queue ID of the RX-free q */
++	int rxdoneq_id; /* where incoming packets are returned */
++	int txq_id;	/* Where to push the outgoing packets */
++	unsigned char hwaddr[6]; /* Desired hardware address */
++
++};
++
+ /*
+  * This structure provide a means for the board setup code
+  * to give information to th pata_ixp4xx driver. It is
+Index: linux-2.6.21-rc1-arm/include/linux/ixp_crypto.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/include/linux/ixp_crypto.h	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,192 @@
++
++#ifndef IX_CRYPTO_H
++#define IX_CRYPTO_H
++
++#define MAX_KEYLEN 64
++#define NPE_CTX_LEN 80
++#define AES_BLOCK128 16
++
++#define NPE_OP_HASH_GEN_ICV   0x50
++#define NPE_OP_ENC_GEN_KEY    0xc9
++
++
++#define NPE_OP_HASH_VERIFY   0x01
++#define NPE_OP_CCM_ENABLE    0x04
++#define NPE_OP_CRYPT_ENABLE  0x08
++#define NPE_OP_HASH_ENABLE   0x10
++#define NPE_OP_NOT_IN_PLACE  0x20
++#define NPE_OP_HMAC_DISABLE  0x40
++#define NPE_OP_CRYPT_ENCRYPT 0x80
++
++#define MOD_ECB     0x0000
++#define MOD_CTR     0x1000
++#define MOD_CBC_ENC 0x2000
++#define MOD_CBC_DEC 0x3000
++#define MOD_CCM_ENC 0x4000
++#define MOD_CCM_DEC 0x5000
++
++#define ALGO_AES    0x0800
++#define CIPH_DECR   0x0000
++#define CIPH_ENCR   0x0400
++
++#define MOD_DES     0x0000
++#define MOD_TDEA2   0x0100
++#define MOD_TDEA3   0x0200
++#define MOD_AES128  0x0000
++#define MOD_AES192  0x0100
++#define MOD_AES256  0x0200
++
++#define KEYLEN_128  4
++#define KEYLEN_192  6
++#define KEYLEN_256  8
++
++#define CIPHER_TYPE_NULL   0
++#define CIPHER_TYPE_DES    1
++#define CIPHER_TYPE_3DES   2
++#define CIPHER_TYPE_AES    3
++
++#define CIPHER_MODE_ECB    1
++#define CIPHER_MODE_CTR    2
++#define CIPHER_MODE_CBC    3
++#define CIPHER_MODE_CCM    4
++
++#define HASH_TYPE_NULL     0
++#define HASH_TYPE_MD5      1
++#define HASH_TYPE_SHA1     2
++#define HASH_TYPE_CBCMAC   3
++
++#define OP_REG_DONE  1
++#define OP_REGISTER  2
++#define OP_PERFORM   3
++
++#define STATE_UNREGISTERED 0
++#define STATE_REGISTERED   1
++#define STATE_UNLOADING    2
++
++struct crypt_ctl {
++#ifndef CONFIG_NPE_ADDRESS_COHERENT
++	u8 mode;    /* NPE operation */
++	u8 init_len;
++	u16 reserved;
++#else
++	u16 reserved;
++	u8 init_len;
++	u8 mode;    /* NPE operation */
++#endif
++	u8 iv[16];  /* IV for CBC mode or CTR IV for CTR mode */
++	union {
++		u32 icv;
++		u32 rev_aes;
++	} addr;
++	u32 src_buf;
++	u32 dest_buf;
++#ifndef CONFIG_NPE_ADDRESS_COHERENT
++	u16 auth_offs;  /* Authentication start offset */
++	u16 auth_len;   /* Authentication data length */
++	u16 crypt_offs; /* Cryption start offset */
++	u16 crypt_len;  /* Cryption data length */
++#else
++	u16 auth_len;   /* Authentication data length */
++	u16 auth_offs;  /* Authentication start offset */
++	u16 crypt_len;  /* Cryption data length */
++	u16 crypt_offs; /* Cryption start offset */
++#endif
++	u32 aadAddr;    /* Additional Auth Data Addr for CCM mode */
++	u32 crypto_ctx; /* NPE Crypto Param structure address */
++
++	/* Used by Host */
++	struct ix_sa_ctx *sa_ctx;
++	int oper_type;
++};
++
++struct npe_crypt_cont {
++	union {
++		struct crypt_ctl crypt;
++		u8 rev_aes_key[NPE_CTX_LEN];
++	} ctl;
++	struct npe_crypt_cont *next;
++	struct npe_crypt_cont *virt;
++	dma_addr_t phys;
++};
++
++struct ix_hash_algo {
++	char *name;
++	u32 cfgword;
++	int digest_len;
++	int aad_len;
++	unsigned char *icv;
++	int type;
++};
++
++struct ix_cipher_algo {
++	char *name;
++	u32 cfgword_enc;
++	u32 cfgword_dec;
++	int block_len;
++	int iv_len;
++	int type;
++	int mode;
++};
++
++struct ix_key {
++	u8 key[MAX_KEYLEN];
++	int len;
++};
++
++struct ix_sa_master {
++	struct device *npe_dev;
++	struct qm_queue *sendq;
++	struct qm_queue *recvq;
++	struct dma_pool *dmapool;
++	struct npe_crypt_cont *pool;
++	int pool_size;
++	rwlock_t lock;
++};
++
++struct ix_sa_dir {
++	unsigned char *npe_ctx;
++	dma_addr_t npe_ctx_phys;
++	int npe_ctx_idx;
++	u8 npe_mode;
++};
++
++struct ix_sa_ctx {
++	struct list_head list;
++	struct ix_sa_master *master;
++
++	const struct ix_hash_algo *h_algo;
++	const struct ix_cipher_algo *c_algo;
++	struct ix_key c_key;
++	struct ix_key h_key;
++
++	int digest_len;
++
++	struct ix_sa_dir encrypt;
++	struct ix_sa_dir decrypt;
++
++	struct npe_crypt_cont *rev_aes;
++	gfp_t gfp_flags;
++
++	int state;
++	void *priv;
++
++	void(*reg_cb)(struct ix_sa_ctx*, int);
++	void(*perf_cb)(struct ix_sa_ctx*, void*, int);
++	atomic_t use_cnt;
++};
++
++const struct ix_hash_algo *ix_hash_by_id(int type);
++const struct ix_cipher_algo *ix_cipher_by_id(int type, int mode);
++
++struct ix_sa_ctx *ix_sa_ctx_new(int priv_len, gfp_t flags);
++void ix_sa_ctx_free(struct ix_sa_ctx *sa_ctx);
++
++int ix_sa_crypto_perform(struct ix_sa_ctx *sa_ctx, u8 *data, void *ptr,
++		int datalen, int c_offs, int c_len, int a_offs, int a_len,
++		int hmac, char *iv, int encrypt);
++
++int ix_sa_ctx_setup_cipher_auth(struct ix_sa_ctx *sa_ctx,
++		const struct ix_cipher_algo *cipher,
++		const struct ix_hash_algo *auth, int len);
++
++#endif
+Index: linux-2.6.21-rc1-arm/include/linux/ixp_npe.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/include/linux/ixp_npe.h	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,117 @@
++/*
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#ifndef NPE_DEVICE_H
++#define NPE_DEVICE_H
++
++#include <linux/miscdevice.h>
++#include <asm/hardware.h>
++
++#ifdef __ARMEB__
++#undef CONFIG_NPE_ADDRESS_COHERENT
++#else
++#define CONFIG_NPE_ADDRESS_COHERENT
++#endif
++
++#if defined(__ARMEB__) || defined (CONFIG_NPE_ADDRESS_COHERENT)
++#define npe_to_cpu32(x) (x)
++#define npe_to_cpu16(x) (x)
++#define cpu_to_npe32(x) (x)
++#define cpu_to_npe16(x) (x)
++#else
++#error NPE_DATA_COHERENT
++#define NPE_DATA_COHERENT
++#define npe_to_cpu32(x) be32_to_cpu(x)
++#define npe_to_cpu16(x) be16_to_cpu(x)
++#define cpu_to_npe32(x) cpu_to_be32(x)
++#define cpu_to_npe16(x) cpu_to_be16(x)
++#endif
++
++
++struct npe_info {
++	struct resource *res;
++	void __iomem *addr;
++	struct npe_plat_data *plat;
++	u8 img_info[4];
++	int usage;
++	int loaded;
++	u32 exec_count;
++	u32 ctx_reg2;
++};
++
++
++static inline void npe_reg_write(struct npe_info *npe, u32 reg, u32 val)
++{
++	*(volatile u32*)((u8*)(npe->addr) + reg) = val;
++}
++
++static inline u32 npe_reg_read(struct npe_info *npe, u32 reg)
++{
++	return *(volatile u32*)((u8*)(npe->addr) + reg);
++}
++
++static inline u32 npe_status(struct npe_info *npe)
++{
++	return npe_reg_read(npe, IX_NPEDL_REG_OFFSET_EXCTL);
++}
++
++/* ixNpeDlNpeMgrCommandIssue */
++static inline void npe_write_exctl(struct npe_info *npe, u32 cmd)
++{
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
++}
++/* ixNpeDlNpeMgrWriteCommandIssue */
++static inline void
++npe_write_cmd(struct npe_info *npe, u32 addr, u32 data, int cmd)
++{
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXDATA, data);
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXAD, addr);
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
++}
++/* ixNpeDlNpeMgrReadCommandIssue */
++static inline u32
++npe_read_cmd(struct npe_info *npe, u32 addr, int cmd)
++{
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXAD, addr);
++	npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
++	/* Intel reads the data twice - so do we... */
++	npe_reg_read(npe, IX_NPEDL_REG_OFFSET_EXDATA);
++	return npe_reg_read(npe, IX_NPEDL_REG_OFFSET_EXDATA);
++}
++
++/* ixNpeDlNpeMgrExecAccRegWrite */
++static inline void npe_write_ecs_reg(struct npe_info *npe, u32 addr, u32 data)
++{
++	npe_write_cmd(npe, addr, data, IX_NPEDL_EXCTL_CMD_WR_ECS_REG);
++}
++/* ixNpeDlNpeMgrExecAccRegRead */
++static inline u32 npe_read_ecs_reg(struct npe_info *npe, u32 addr)
++{
++	return npe_read_cmd(npe, addr, IX_NPEDL_EXCTL_CMD_RD_ECS_REG);
++}
++
++extern void npe_stop(struct npe_info *npe);
++extern void npe_start(struct npe_info *npe);
++extern void npe_reset(struct npe_info *npe);
++
++extern struct device *get_npe_by_id(int id);
++extern void return_npe_dev(struct device *dev);
++
++/* NPE Messages */
++extern int
++npe_mh_status(struct npe_info *npe);
++extern int
++npe_mh_setportaddr(struct npe_info *npe, struct mac_plat_info *mp, u8 *macaddr);
++extern int
++npe_mh_disable_firewall(struct npe_info *npe, struct mac_plat_info *mp);
++extern int
++npe_mh_set_rxqid(struct npe_info *npe, struct mac_plat_info *mp, int qid);
++extern int
++npe_mh_npe_loopback_mode(struct npe_info *npe, struct mac_plat_info *mp, int enable);
++extern int
++npe_mh_get_stats(struct npe_info *npe, struct mac_plat_info *mp, u32 phys, int reset);
++
++#endif
+Index: linux-2.6.21-rc1-arm/include/linux/ixp_qmgr.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/include/linux/ixp_qmgr.h	2007-02-21 02:24:35.000000000 -0800
+@@ -0,0 +1,202 @@
++/*
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#ifndef IX_QMGR_H
++#define IX_QMGR_H
++
++#include <linux/skbuff.h>
++#include <linux/list.h>
++#include <linux/if_ether.h>
++#include <linux/spinlock.h>
++#include <linux/platform_device.h>
++#include <linux/ixp_npe.h>
++#include <asm/atomic.h>
++
++/* All offsets are in 32bit words */
++#define QUE_LOW_STAT0    0x100 /* 4x Status of the 32 lower queues 0-31 */
++#define QUE_UO_STAT0     0x104 /* 2x Underflow/Overflow status bits*/
++#define QUE_UPP_STAT0    0x106 /* 2x Status of thew 32 upper queues 32-63 */
++#define INT0_SRC_SELREG0 0x108 /* 4x */
++#define QUE_IE_REG0      0x10c /* 2x */
++#define QUE_INT_REG0     0x10e /* 2x IRQ reg, write 1 to reset IRQ */
++
++#define IX_QMGR_QCFG_BASE	0x800
++#define IX_QMGR_QCFG_SIZE	0x40
++#define IX_QMGR_SRAM_SPACE	(IX_QMGR_QCFG_BASE + IX_QMGR_QCFG_SIZE)
++
++#define MAX_QUEUES 32 /* first, we only support the lower 32 queues */
++#define MAX_NPES    3
++
++enum {
++	Q_IRQ_ID_E = 0,  /* Queue Empty due to last read  */
++	Q_IRQ_ID_NE,     /* Queue Nearly Empty due to last read */
++	Q_IRQ_ID_NF,     /* Queue Nearly Full due to last write */
++	Q_IRQ_ID_F,      /* Queue Full due to last write  */
++	Q_IRQ_ID_NOT_E,  /* Queue Not Empty due to last write */
++	Q_IRQ_ID_NOT_NE, /* Queue Not Nearly Empty due to last write */
++	Q_IRQ_ID_NOT_NF, /* Queue Not Nearly Full due to last read */
++	Q_IRQ_ID_NOT_F   /* Queue Not Full due to last read */
++};
++
++extern struct qm_queue *request_queue(int qid, int len);
++extern void release_queue(struct qm_queue *queue);
++extern int queue_set_irq_src(struct qm_queue *queue, int flag);
++extern void queue_set_watermarks(struct qm_queue *, unsigned ne, unsigned nf);
++extern int queue_len(struct qm_queue *queue);
++
++struct qm_qmgr;
++struct qm_queue;
++
++typedef void(*queue_cb)(struct qm_queue *);
++
++struct qm_queue {
++	int addr;	/* word offset from IX_QMGR_SRAM_SPACE */
++	int len;	/* size in words */
++	int id;		/* Q Id */
++	u32 __iomem *acc_reg;
++	struct device *dev;
++	atomic_t use;
++	queue_cb irq_cb;
++	void *cb_data;
++};
++
++#ifndef CONFIG_NPE_ADDRESS_COHERENT
++struct eth_ctl {
++	u32 next;
++	u16 buf_len;
++	u16 pkt_len;
++	u32 phys_addr;
++	u8 dest_id;
++	u8 src_id;
++	u16 flags;
++	u8 qos;
++	u8 padlen;
++	u16 vlan_tci;
++	u8 dest_mac[ETH_ALEN];
++	u8 src_mac[ETH_ALEN];
++};
++
++#else
++struct eth_ctl {
++	u32 next;
++	u16 pkt_len;
++	u16 buf_len;
++	u32 phys_addr;
++	u16 flags;
++	u8 src_id;
++	u8 dest_id;
++	u16 vlan_tci;
++	u8 padlen;
++	u8 qos;
++	u8 dest_mac[ETH_ALEN];
++	u8 src_mac[ETH_ALEN];
++};
++#endif
++
++struct npe_cont {
++	struct eth_ctl eth;
++	void *data;
++	struct npe_cont *next;
++	struct npe_cont *virt;
++	dma_addr_t phys;
++};
++
++struct qm_qmgr {
++	u32 __iomem *addr;
++	struct resource *res;
++	struct qm_queue *queues[MAX_QUEUES];
++	rwlock_t lock;
++	struct npe_cont *pool;
++	struct dma_pool *dmapool;
++	int irq;
++};
++
++static inline void queue_write_cfg_reg(struct qm_queue *queue, u32 val)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	*(qmgr->addr + IX_QMGR_QCFG_BASE + queue->id) = val;
++}
++static inline u32 queue_read_cfg_reg(struct qm_queue *queue)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	return *(qmgr->addr + IX_QMGR_QCFG_BASE + queue->id);
++}
++
++static inline void queue_ack_irq(struct qm_queue *queue)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	*(qmgr->addr + QUE_INT_REG0) = 1 << queue->id;
++}
++
++static inline void queue_enable_irq(struct qm_queue *queue)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	*(qmgr->addr + QUE_IE_REG0) |= 1 << queue->id;
++}
++
++static inline void queue_disable_irq(struct qm_queue *queue)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	*(qmgr->addr + QUE_IE_REG0) &= ~(1 << queue->id);
++}
++
++static inline void queue_put_entry(struct qm_queue *queue, u32 entry)
++{
++	*(queue->acc_reg) = npe_to_cpu32(entry);
++}
++
++static inline u32 queue_get_entry(struct qm_queue *queue)
++{
++	return cpu_to_npe32(*queue->acc_reg);
++}
++
++static inline struct npe_cont *qmgr_get_cont(struct qm_qmgr *qmgr)
++{
++	unsigned long flags;
++	struct npe_cont *cont;
++
++	if (!qmgr->pool)
++		return NULL;
++	write_lock_irqsave(&qmgr->lock, flags);
++	cont = qmgr->pool;
++	qmgr->pool = cont->next;
++	write_unlock_irqrestore(&qmgr->lock, flags);
++	return cont;
++}
++
++static inline void qmgr_return_cont(struct qm_qmgr *qmgr,struct npe_cont *cont)
++{
++	unsigned long flags;
++
++	write_lock_irqsave(&qmgr->lock, flags);
++	cont->next = qmgr->pool;
++	qmgr->pool = cont;
++	write_unlock_irqrestore(&qmgr->lock, flags);
++}
++
++static inline int queue_stat(struct qm_queue *queue)
++{
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++	u32 reg = *(qmgr->addr + QUE_UO_STAT0 + (queue->id >> 4));
++	return (reg >> (queue->id & 0xf) << 1) & 3;
++}
++
++/* Prints the queue state, which is very, very helpfull for debugging */
++static inline void queue_state(struct qm_queue *queue)
++{
++	u32 val=0, lstat=0;
++	int offs;
++	struct qm_qmgr *qmgr = dev_get_drvdata(queue->dev);
++
++	offs = queue->id/8 + QUE_LOW_STAT0;
++	val = *(qmgr->addr + IX_QMGR_QCFG_BASE + queue->id);
++	lstat = (*(qmgr->addr + offs) >>  ((queue->id % 8)*4)) & 0x0f;
++
++	printk("Qid[%02d]: Wptr=%4x, Rptr=%4x, diff=%4x, Stat:%x\n", queue->id,
++		val&0x7f, (val>>7) &0x7f, (val - (val >> 7)) & 0x7f, lstat);
++}
++
++#endif
diff --git a/target/linux/ixp4xx/patches/110-ixp4xx_net_driver_fix_mac_handling.patch b/target/linux/ixp4xx/patches/110-ixp4xx_net_driver_fix_mac_handling.patch
new file mode 100644
index 0000000000..1050702d88
--- /dev/null
+++ b/target/linux/ixp4xx/patches/110-ixp4xx_net_driver_fix_mac_handling.patch
@@ -0,0 +1,17 @@
+---
+ drivers/net/ixp4xx/mac_driver.c |   24 ++++++++++--------------
+ 1 file changed, 10 insertions(+), 14 deletions(-)
+
+Index: linux-2.6.21-rc4-git6-arm/drivers/net/ixp4xx/mac_driver.c
+===================================================================
+--- linux-2.6.21-rc4-git6-arm.orig/drivers/net/ixp4xx/mac_driver.c	2007-03-22 10:32:20.735684085 +0000
++++ linux-2.6.21-rc4-git6-arm/drivers/net/ixp4xx/mac_driver.c	2007-03-22 10:33:29.355972584 +0000
+@@ -842,7 +842,7 @@
+ 	}
+ }
+ 
+-module_init(init_mac);
++late_initcall(init_mac);
+ module_exit(finish_mac);
+ 
+ MODULE_LICENSE("GPL");
diff --git a/target/linux/ixp4xx/patches/139-ixp4xx_net_driver_mtd_load_fw.patch b/target/linux/ixp4xx/patches/139-ixp4xx_net_driver_mtd_load_fw.patch
new file mode 100644
index 0000000000..ef53155c03
--- /dev/null
+++ b/target/linux/ixp4xx/patches/139-ixp4xx_net_driver_mtd_load_fw.patch
@@ -0,0 +1,392 @@
+---
+ drivers/net/ixp4xx/Kconfig             |   10 +
+ drivers/net/ixp4xx/Makefile            |    1 
+ drivers/net/ixp4xx/npe_ucode.c         |  185 +++++++++++++++++++++++++++++++++
+ drivers/net/ixp4xx/ucode_dl.c          |   43 ++++---
+ include/asm-arm/arch-ixp4xx/platform.h |   19 +++
+ include/linux/ixp_npe.h                |    1 
+ 6 files changed, 239 insertions(+), 20 deletions(-)
+
+Index: linux-2.6.20-rc3/drivers/net/ixp4xx/Kconfig
+===================================================================
+--- linux-2.6.20-rc3.orig/drivers/net/ixp4xx/Kconfig
++++ linux-2.6.20-rc3/drivers/net/ixp4xx/Kconfig
+@@ -11,6 +11,7 @@
+ 	tristate "IXP4xx NPE support"
+ 	depends on ARCH_IXP4XX
+ 	depends on NET_ETHERNET
++	select CRC16
+ 	help
+ 	  The IXP4XX NPE driver supports the 3 CPU co-processors called
+ 	  "Network Processing Engines" (NPE). It adds support fo downloading
+@@ -18,7 +19,7 @@
+ 	  More about this at: Documentation/networking/ixp4xx/README.
+ 	  You can either use this OR the Intel Access Library (IAL)
+ 
+-config IXP4XX_FW_LOAD
++config IXP4XX_NPE_FW_LOAD
+ 	bool "Use Firmware hotplug for Microcode download"
+ 	depends on IXP4XX_NPE
+ 	select HOTPLUG
+@@ -28,6 +29,13 @@
+ 	  /usr/lib/hotplug/firmware/NPE-[ABC]
+ 	  see Documentation/firmware_class/hotplug-script
+ 
++config IXP4XX_NPE_FW_MTD
++	bool "Load firmware from an mtd partition"
++	depends on IXP4XX_NPE && MTD_IXP4XX
++	help
++	  With this option, the driver will search for
++	  the firmware into an MTD partition.
++
+ config IXP4XX_MAC
+ 	tristate "IXP4xx MAC support"
+ 	depends on IXP4XX_NPE
+Index: linux-2.6.20-rc3/drivers/net/ixp4xx/Makefile
+===================================================================
+--- linux-2.6.20-rc3.orig/drivers/net/ixp4xx/Makefile
++++ linux-2.6.20-rc3/drivers/net/ixp4xx/Makefile
+@@ -1,5 +1,6 @@
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+ obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
++obj-$(CONFIG_IXP4XX_NPE_FW_MTD) += npe_ucode.o
+ obj-$(CONFIG_IXP4XX_MAC) += ixp4xx_mac.o
+ obj-$(CONFIG_IXP4XX_CRYPTO) += ixp4xx_crypto.o
+ 
+Index: linux-2.6.20-rc3/drivers/net/ixp4xx/npe_ucode.c
+===================================================================
+--- /dev/null
++++ linux-2.6.20-rc3/drivers/net/ixp4xx/npe_ucode.c
+@@ -0,0 +1,185 @@
++/*
++ * Provide an NPE platform device for microcode handling
++ *
++ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
++ *
++ * This file is released under the GPLv2
++ */
++
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/firmware.h>
++#include <linux/mtd/mtd.h>
++
++#include <linux/ixp_npe.h>
++
++#define DL_MAGIC 0xfeedf00d
++#define DL_MAGIC_SWAP 0x0df0edfe
++
++#define IMG_SIZE(image) (((image)->size * sizeof(u32)) + \
++		sizeof(struct dl_image))
++
++#define IMG_REV_MAJOR(id) (((id) >> 8) & 0x0f)
++#define IMG_REV_MINOR(id) ((id) & 0x0f)
++#define IMG_FUNC(id) (((id) >> 16) & 0xff)
++#define IMG_NPE(id) (((id) >> 24) & 0x0f)
++#define IMG_IXP(id) (((id) >> 28) & 0x0f)
++
++static struct platform_driver ixp4xx_npe_ucode_driver;
++static unsigned char *partition_name = NULL;
++
++static void print_image_info(u32 id, u32 offset, u32 size)
++{
++	unsigned char idx;
++	const char *names[] = { "IXP425", "IXP465", "unknown" };
++
++	idx = IMG_IXP(id) < 2 ? IMG_IXP(id) : 2;
++
++	printk(KERN_INFO "npe: found at 0x%x, %s/NPE-%c func: %02x, rev: %x.%x, "
++		"size: %5d, id: %08x\n", offset, names[idx], IMG_NPE(id) + 'A',
++		IMG_FUNC(id), IMG_REV_MAJOR(id), IMG_REV_MINOR(id), size, id);
++}
++
++void npe_swap_image(struct dl_image *image)
++{
++	unsigned int i;
++
++	image->magic = swab32(image->magic);
++	image->id = swab32(image->id);
++	image->size = swab32(image->size);
++
++	for (i = 0; i < image->size; i++)
++		image->u.data[i] = swab32(image->u.data[i]);
++}
++
++static void npe_find_microcode(struct mtd_info *mtd)
++{
++	u32 buf;
++	u32 magic = htonl(DL_MAGIC);
++	u32 id, size;
++	size_t retlen;
++	int err;
++	unsigned int offset = 0;
++
++	printk("npe: searching for firmware...\n");
++
++	while (offset < mtd->size) {
++
++		err = mtd->read(mtd, offset, 4, &retlen, (u_char *) &buf);
++		offset += retlen;
++
++		if (buf != magic)
++			continue;
++
++		err = mtd->read(mtd, offset, 4, &retlen, (u_char *) &id);
++		offset += retlen;
++
++		if (id == magic)
++			break;
++
++		id = ntohl(id);
++
++		err = mtd->read(mtd, offset, 4, &retlen, (u_char *) &size);
++		offset += retlen;
++
++		size = (ntohl(size) * 4) + 12;
++
++		print_image_info(id, offset - 12, size);
++
++		if (size < 24000 && ( IMG_FUNC(id) == 0x01 || IMG_FUNC(id) == 0x00) || IMG_FUNC(id) == 0x05 ) { // XXX fix size/detection
++
++			struct dl_image *image = kmalloc(size, GFP_KERNEL);
++
++			/* we are going to load it, rewind offset */
++			offset -= 12;
++
++			if (image) {
++				err = mtd->read(mtd, offset, size, &retlen, (u_char *) image);
++
++				if (err == 0 && retlen == size) {
++					if (image->magic == DL_MAGIC_SWAP)
++						npe_swap_image(image);
++
++					store_npe_image(image, NULL);
++				} else {
++					printk(KERN_ERR "unable to read firmware\n");
++				}
++
++				kfree(image);
++			}
++
++			offset += size;
++		}
++	}
++}
++
++static void npe_flash_add(struct mtd_info *mtd)
++{
++	if (partition_name == NULL)
++		return;
++
++	if (strcmp(mtd->name, partition_name) == 0) {
++		npe_find_microcode(mtd);
++	}
++}
++
++static void npe_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier npe_flash_notifier = {
++	.add = npe_flash_add,
++	.remove = npe_flash_remove,
++};
++
++static int npe_ucode_probe(struct platform_device *pdev)
++{
++	struct npe_ucode_platform_data *data = pdev->dev.platform_data;
++
++	if (partition_name)
++		return -EEXIST;
++
++	if (data && data->mtd_partition) {
++		partition_name = data->mtd_partition;
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static int npe_ucode_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static struct platform_driver ixp4xx_npe_ucode_driver = {
++	.driver = {
++		.name	= "ixp4xx_npe_ucode",
++		.owner	= THIS_MODULE,
++	},
++	.probe	= npe_ucode_probe,
++	.remove	= npe_ucode_remove,
++};
++
++static int __init npe_ucode_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&ixp4xx_npe_ucode_driver);
++	register_mtd_user(&npe_flash_notifier);
++
++	return ret;
++}
++
++static void __exit npe_ucode_exit(void)
++{
++	unregister_mtd_user(&npe_flash_notifier);
++	platform_driver_unregister(&ixp4xx_npe_ucode_driver);
++}
++
++module_init(npe_ucode_init);
++module_exit(npe_ucode_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
+Index: linux-2.6.20-rc3/drivers/net/ixp4xx/ucode_dl.c
+===================================================================
+--- linux-2.6.20-rc3.orig/drivers/net/ixp4xx/ucode_dl.c
++++ linux-2.6.20-rc3/drivers/net/ixp4xx/ucode_dl.c
+@@ -16,6 +16,7 @@
+ #include <linux/firmware.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/byteorder/swab.h>
++#include <linux/crc16.h>
+ #include <asm/uaccess.h>
+ #include <asm/io.h>
+ 
+@@ -26,6 +27,12 @@
+ #define DL_MAGIC 0xfeedf00d
+ #define DL_MAGIC_SWAP 0x0df0edfe
+ 
++#define IMG_REV_MAJOR(id) (((id) >> 8) & 0x0f)
++#define IMG_REV_MINOR(id) ((id) & 0x0f)
++#define IMG_FUNC(id) (((id) >> 16) & 0xff)
++#define IMG_NPE(id) (((id) >> 24) & 0x0f)
++#define IMG_IXP(id) (((id) >> 28) & 0x0f)
++
+ #define EOF_BLOCK 0xf
+ #define IMG_SIZE(image) (((image)->size * sizeof(u32)) + \
+ 		sizeof(struct dl_image))
+@@ -38,21 +45,6 @@
+ 	data,
+ };
+ 
+-struct dl_block {
+-	u32 type;
+-	u32 offset;
+-};
+-
+-struct dl_image {
+-	u32 magic;
+-	u32 id;
+-	u32 size;
+-	union {
+-		u32 data[0];
+-		struct dl_block block[0];
+-	} u;
+-};
+-
+ struct dl_codeblock {
+ 	u32 npe_addr;
+ 	u32 size;
+@@ -127,20 +119,33 @@
+ 	return 0;
+ }
+ 
+-static int store_npe_image(struct dl_image *image, struct device *dev)
++int store_npe_image(struct dl_image *image, struct device *dev)
+ {
+ 	struct dl_block *blk;
+ 	struct dl_codeblock *cb;
+ 	struct npe_info *npe;
+ 	int ret=0;
++	u16 crc;
+ 
+ 	if (!dev) {
+-		dev = get_npe_by_id( (image->id >> 24) & 0xf);
++		dev = get_npe_by_id(IMG_NPE(image->id));
+ 		return_npe_dev(dev);
+ 	}
+ 	if (!dev)
+ 		return -ENODEV;
+ 
++	if (image->size > 24000) { // XXX fix max size
++		printk(KERN_ERR "npe: firmware too large\n");
++		return -EFBIG;
++	}
++
++	if (IMG_REV_MAJOR(image->id) != 2) {
++		printk(KERN_ERR "npe: only revision 2 is supported at this time\n");
++		return -EINVAL;
++	}
++
++	crc = crc16(0, (u8 *) image, IMG_SIZE(image));
++
+ 	npe = dev_get_drvdata(dev);
+ 	if (npe->loaded && (npe->usage > 0)) {
+ 		printk(KERN_INFO "Cowardly refusing to reload an Image "
+@@ -267,8 +272,7 @@
+ 
+ static void npe_firmware_probe(struct device *dev)
+ {
+-#if (defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)) \
+-	&& defined(MODULE)
++#ifdef CONFIG_IXP4XX_NPE_FW_LOADER
+ 	const struct firmware *fw_entry;
+ 	struct npe_info *npe = dev_get_drvdata(dev);
+ 	struct dl_image *image;
+@@ -477,3 +481,4 @@
+ 
+ EXPORT_SYMBOL(get_npe_by_id);
+ EXPORT_SYMBOL(return_npe_dev);
++EXPORT_SYMBOL(store_npe_image);
+Index: linux-2.6.20-rc3/include/asm-arm/arch-ixp4xx/platform.h
+===================================================================
+--- linux-2.6.20-rc3.orig/include/asm-arm/arch-ixp4xx/platform.h
++++ linux-2.6.20-rc3/include/asm-arm/arch-ixp4xx/platform.h
+@@ -86,6 +86,21 @@
+ 	unsigned long scl_pin;
+ };
+ 
++struct dl_block {
++	u32 type;
++        u32 offset;
++};
++
++struct dl_image {
++	u32 magic;
++	u32 id;
++	u32 size;
++	union {
++		u32 data[0];
++		struct dl_block block[0];
++	} u;
++};
++
+ struct npe_plat_data {
+ 	const char *name;
+ 	int data_size;
+@@ -105,6 +120,10 @@
+ 
+ };
+ 
++struct npe_ucode_platform_data {
++	unsigned char *mtd_partition;
++};
++ 
+ /*
+  * This structure provide a means for the board setup code
+  * to give information to th pata_ixp4xx driver. It is
+Index: linux-2.6.20-rc3/include/linux/ixp_npe.h
+===================================================================
+--- linux-2.6.20-rc3.orig/include/linux/ixp_npe.h
++++ linux-2.6.20-rc3/include/linux/ixp_npe.h
+@@ -99,6 +99,7 @@
+ 
+ extern struct device *get_npe_by_id(int id);
+ extern void return_npe_dev(struct device *dev);
++extern int store_npe_image(struct dl_image *image, struct device *dev);
+ 
+ /* NPE Messages */
+ extern int
diff --git a/target/linux/ixp4xx/patches/140-ixp4xx_net_driver_no_phy.patch b/target/linux/ixp4xx/patches/140-ixp4xx_net_driver_no_phy.patch
new file mode 100644
index 0000000000..4bd6875e9d
--- /dev/null
+++ b/target/linux/ixp4xx/patches/140-ixp4xx_net_driver_no_phy.patch
@@ -0,0 +1,73 @@
+diff -Nur linux-2.6.19.2/drivers/net/ixp4xx/mac_driver.c linux-2.6.19.2-owrt/drivers/net/ixp4xx/mac_driver.c
+--- linux-2.6.19.2/drivers/net/ixp4xx/mac_driver.c	2007-04-15 14:26:54.000000000 +0200
++++ linux-2.6.19.2-owrt/drivers/net/ixp4xx/mac_driver.c	2007-04-15 14:33:44.000000000 +0200
+@@ -161,6 +161,16 @@
+ {
+ 	struct mac_info *mac = netdev_priv(dev);
+ 
++	if ( mac->mii.phy_id < 0 ) {
++		if ( init ) {
++			netif_carrier_on(mac->mii.dev);
++			mac->mii.full_duplex = 1;
++			update_duplex_mode(dev);
++			return 1;
++		}
++		return 0;
++	}
++
+ 	if (mii_check_media(&mac->mii, netif_msg_link(mac), init)) {
+ 		update_duplex_mode(dev);
+ 		return 1;
+@@ -458,7 +468,12 @@
+ 		return -EINVAL;
+ 	if (!try_module_get(THIS_MODULE))
+ 		return -ENODEV;
+-	rc = generic_mii_ioctl(&mac->mii, if_mii(rq), cmd, &duplex_changed);
++	if ( mac->mii.phy_id < 0 ) {
++		duplex_changed = 0;
++		rc = -EOPNOTSUPP;
++	} else {
++		rc = generic_mii_ioctl(&mac->mii, if_mii(rq), cmd, &duplex_changed);
++	}
+ 	module_put(THIS_MODULE);
+ 	if (duplex_changed)
+ 		update_duplex_mode(dev);
+@@ -488,6 +503,9 @@
+ static int ixmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+ {
+ 	struct mac_info *mac = netdev_priv(dev);
++	if ( mac->mii.phy_id < 0 ) {
++		return 0;
++	}
+ 	mii_ethtool_gset(&mac->mii, cmd);
+ 	return 0;
+ }
+@@ -496,6 +514,9 @@
+ {
+ 	struct mac_info *mac = netdev_priv(dev);
+ 	int rc;
++	if ( mac->mii.phy_id < 0 ) {
++		return -EOPNOTSUPP;
++	}
+ 	rc = mii_ethtool_sset(&mac->mii, cmd);
+ 	return rc;
+ }
+@@ -503,12 +524,18 @@
+ static int ixmac_nway_reset(struct net_device *dev)
+ {
+ 	struct mac_info *mac = netdev_priv(dev);
++	if ( mac->mii.phy_id < 0 ) {
++		return -EOPNOTSUPP;
++	}
+ 	return mii_nway_restart(&mac->mii);
+ }
+ 
+ static u32 ixmac_get_link(struct net_device *dev)
+ {
+ 	struct mac_info *mac = netdev_priv(dev);
++	if ( mac->mii.phy_id < 0 ) {
++		return 1;
++	}
+ 	return mii_link_ok(&mac->mii);
+ }
+ 
diff --git a/target/linux/ixp4xx/patches/141-nslu2_setup_mac.patch b/target/linux/ixp4xx/patches/141-nslu2_setup_mac.patch
new file mode 100644
index 0000000000..cada1bd544
--- /dev/null
+++ b/target/linux/ixp4xx/patches/141-nslu2_setup_mac.patch
@@ -0,0 +1,42 @@
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -137,6 +137,29 @@ static struct platform_device nslu2_uart
+ 	.resource		= nslu2_uart_resources,
+ };
+ 
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= 1,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct platform_device mac0 = {
++	.name           = "ixp4xx_mac",
++	.id             = 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources  = 1,
++	.resource       = &res_mac0,
++};
++
+ static struct platform_device *nslu2_devices[] __initdata = {
+ 	&nslu2_i2c_controller,
+ 	&nslu2_flash,
+@@ -144,6 +166,7 @@ static struct platform_device *nslu2_dev
+ #ifdef CONFIG_LEDS_IXP4XX
+ 	&nslu2_leds,
+ #endif
++	&mac0
+ };
+ 
+ static void nslu2_power_off(void)
diff --git a/target/linux/ixp4xx/patches/142-nas100d_setup_mac.patch b/target/linux/ixp4xx/patches/142-nas100d_setup_mac.patch
new file mode 100644
index 0000000000..9256324b10
--- /dev/null
+++ b/target/linux/ixp4xx/patches/142-nas100d_setup_mac.patch
@@ -0,0 +1,41 @@
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -123,12 +123,36 @@ static struct platform_device nas100d_ua
+ 	.resource		= nas100d_uart_resources,
+ };
+ 
++static struct resource res_mac0 = {
++       .start          = IXP4XX_EthB_BASE_PHYS,
++       .end            = IXP4XX_EthB_BASE_PHYS + 0x1ff,
++       .flags          = IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++       .npe_id         = 1,
++       .phy_id         = 0,
++       .eth_id         = 0,
++       .rxq_id         = 27,
++       .txq_id         = 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct platform_device mac0 = {
++       .name           = "ixp4xx_mac",
++       .id             = 0,
++       .dev.platform_data = &plat_mac0,
++       .num_resources  = 1,
++       .resource       = &res_mac0,
++};
++
+ static struct platform_device *nas100d_devices[] __initdata = {
+ 	&nas100d_i2c_controller,
+ 	&nas100d_flash,
+ #ifdef CONFIG_LEDS_IXP4XX
+ 	&nas100d_leds,
+ #endif
++	&mac0
+ };
+ 
+ static void nas100d_power_off(void)
diff --git a/target/linux/ixp4xx/patches/143-nslu2_mtd_microcode.patch b/target/linux/ixp4xx/patches/143-nslu2_mtd_microcode.patch
new file mode 100644
index 0000000000..adf91891f8
--- /dev/null
+++ b/target/linux/ixp4xx/patches/143-nslu2_mtd_microcode.patch
@@ -0,0 +1,35 @@
+---
+ arch/arm/mach-ixp4xx/nslu2-setup.c |   13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -159,6 +159,16 @@ static struct platform_device mac0 = {
+ 	.resource       = &res_mac0,
+ };
+ 
++struct npe_ucode_platform_data nslu2_npe_ucode_data = {
++	.mtd_partition	= "FIS directory",
++};
++
++static struct platform_device nslu2_npe_ucode = {
++	.name			= "ixp4xx_npe_ucode",
++	.id			= 0,
++	.dev.platform_data	= &nslu2_npe_ucode_data,
++};
++
+ static struct platform_device *nslu2_devices[] __initdata = {
+ 	&nslu2_i2c_controller,
+ 	&nslu2_flash,
+@@ -166,7 +176,8 @@ static struct platform_device *nslu2_dev
+ #ifdef CONFIG_LEDS_IXP4XX
+ 	&nslu2_leds,
+ #endif
+-	&mac0
++	&mac0,
++	&nslu2_npe_ucode,
+ };
+ 
+ static void nslu2_power_off(void)
diff --git a/target/linux/ixp4xx/patches/144-nas100d_mtd_microcode.patch b/target/linux/ixp4xx/patches/144-nas100d_mtd_microcode.patch
new file mode 100644
index 0000000000..0794e6fd72
--- /dev/null
+++ b/target/linux/ixp4xx/patches/144-nas100d_mtd_microcode.patch
@@ -0,0 +1,34 @@
+---
+ arch/arm/mach-ixp4xx/nas100d-setup.c |   13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -145,13 +145,24 @@ static struct platform_device mac0 = {
+        .resource       = &res_mac0,
+ };
+ 
++struct npe_ucode_platform_data nas100d_npe_ucode_data = {
++	.mtd_partition	= "microcode",
++};
++
++static struct platform_device nas100d_npe_ucode = {
++	.name			= "ixp4xx_npe_ucode",
++	.id			= 0,
++	.dev.platform_data	= &nas100d_npe_ucode_data,
++};
++
+ static struct platform_device *nas100d_devices[] __initdata = {
+ 	&nas100d_i2c_controller,
+ 	&nas100d_flash,
+ #ifdef CONFIG_LEDS_IXP4XX
+ 	&nas100d_leds,
+ #endif
+-	&mac0
++	&mac0,
++	&nas100d_npe_ucode,
+ };
+ 
+ static void nas100d_power_off(void)
diff --git a/target/linux/ixp4xx/patches/152-nas100d_mtd_load_mac.patch b/target/linux/ixp4xx/patches/152-nas100d_mtd_load_mac.patch
new file mode 100644
index 0000000000..37368861bd
--- /dev/null
+++ b/target/linux/ixp4xx/patches/152-nas100d_mtd_load_mac.patch
@@ -0,0 +1,56 @@
+---
+ arch/arm/mach-ixp4xx/nas100d-setup.c |   27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -16,6 +16,7 @@
+ #include <linux/serial.h>
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
++#include <linux/mtd/mtd.h>
+ 
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -165,6 +166,30 @@ static struct platform_device *nas100d_d
+ 	&nas100d_npe_ucode,
+ };
+ 
++static void nas100d_flash_add(struct mtd_info *mtd)
++{
++	if (strcmp(mtd->name, "RedBoot config") == 0) {
++		size_t retlen;
++		u_char mac[6];
++
++		if (mtd->read(mtd, 0x0FD8, 6, &retlen, mac) == 0 && retlen == 6) {
++			printk(KERN_INFO "nas100d mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++				mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++			memcpy(plat_mac0.hwaddr, mac, 6);
++		} else {
++			printk(KERN_ERR "nas100d mac: read failed\n");
++		}
++	}
++}
++
++static void nas100d_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier nas100d_flash_notifier = {
++	.add = nas100d_flash_add,
++	.remove = nas100d_flash_remove,
++};
++
+ static void nas100d_power_off(void)
+ {
+ 	/* This causes the box to drop the power and go dead. */
+@@ -196,6 +221,8 @@ static void __init nas100d_init(void)
+ 	(void)platform_device_register(&nas100d_uart);
+ 
+ 	platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices));
++
++	register_mtd_user(&nas100d_flash_notifier);
+ }
+ 
+ MACHINE_START(NAS100D, "Iomega NAS 100d")
diff --git a/target/linux/ixp4xx/patches/153-nslu2_mtd_load_mac.patch b/target/linux/ixp4xx/patches/153-nslu2_mtd_load_mac.patch
new file mode 100644
index 0000000000..21fe29a88d
--- /dev/null
+++ b/target/linux/ixp4xx/patches/153-nslu2_mtd_load_mac.patch
@@ -0,0 +1,56 @@
+---
+ arch/arm/mach-ixp4xx/nslu2-setup.c |   27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -18,6 +18,7 @@
+ #include <linux/serial.h>
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
++#include <linux/mtd/mtd.h>
+ 
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -180,6 +181,30 @@ static struct platform_device *nslu2_dev
+ 	&nslu2_npe_ucode,
+ };
+ 
++static void nslu2_flash_add(struct mtd_info *mtd)
++{
++	if (strcmp(mtd->name, "RedBoot") == 0) {
++		size_t retlen;
++		u_char mac[6];
++
++		if (mtd->read(mtd, 0x3FFB0, 6, &retlen, mac) == 0 && retlen == 6) {
++			printk(KERN_INFO "nslu2 mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++				mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++			memcpy(plat_mac0.hwaddr, mac, 6);
++		} else {
++			printk(KERN_ERR "nslu2 mac: read failed\n");
++		}
++	}
++}
++
++static void nslu2_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier nslu2_flash_notifier = {
++	.add = nslu2_flash_add,
++	.remove = nslu2_flash_remove,
++};
++
+ static void nslu2_power_off(void)
+ {
+ 	/* This causes the box to drop the power and go dead. */
+@@ -210,6 +235,8 @@ static void __init nslu2_init(void)
+ 	(void)platform_device_register(&nslu2_uart);
+ 
+ 	platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices));
++
++	register_mtd_user(&nslu2_flash_notifier);
+ }
+ 
+ MACHINE_START(NSLU2, "Linksys NSLU2")
diff --git a/target/linux/ixp4xx/patches/160-nas100d_artop_temp_fix.patch b/target/linux/ixp4xx/patches/160-nas100d_artop_temp_fix.patch
new file mode 100644
index 0000000000..b7ac4d94c6
--- /dev/null
+++ b/target/linux/ixp4xx/patches/160-nas100d_artop_temp_fix.patch
@@ -0,0 +1,49 @@
+From: Alan Cox <alan@redhat.com>
+To: Alessandro Zummo <alessandro.zummo@towertech.it>
+Cc: Jeff Garzik <jgarzik@redhat.com>, Alan Cox <alan@redhat.com>
+Subject: Re: drivers/ata/pata_artop.c
+Date: Sun, 15 Oct 2006 14:25:16 -0400
+User-Agent: Mutt/1.4.1i
+
+On Sun, Oct 15, 2006 at 07:18:31PM +0200, Alessandro Zummo wrote:
+>  In the discovery phase there's a lot of time spent in the detection
+>  of the second port.  
+
+The error recovery is a bit determined right now - Tejun's been doing some
+work on SRST behaviour and also for the worst cases polled detect so it
+should come out ok
+
+>  What's the correct way to inform the driver
+>  to avoid checking the second port?  
+
+Set the number of ports to 1 in your own tree for now. The real fix is
+not to go poking at pata ports if the ret is 0xFF
+
+---
+ drivers/ata/pata_artop.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+Index: linux-2.6.19/drivers/ata/pata_artop.c
+===================================================================
+--- linux-2.6.19.orig/drivers/ata/pata_artop.c
++++ linux-2.6.19/drivers/ata/pata_artop.c
+@@ -26,6 +26,7 @@
+ #include <scsi/scsi_host.h>
+ #include <linux/libata.h>
+ #include <linux/ata.h>
++#include <asm/mach-types.h>
+ 
+ #define DRV_NAME	"pata_artop"
+ #define DRV_VERSION	"0.4.2"
+@@ -469,6 +470,11 @@ static int artop_init_one (struct pci_de
+ 		pci_read_config_byte(pdev, 0x4a, &reg);
+ 		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
+ 
++		/* NAS100D workaround */
++#ifdef CONFIG_MACH_NAS100D
++		if (machine_is_nas100d())
++			ports = 1;
++#endif
+ 	}
+ 
+ 	BUG_ON(info == NULL);
diff --git a/target/linux/ixp4xx/patches/178-via_velocity_bigendian.patch b/target/linux/ixp4xx/patches/178-via_velocity_bigendian.patch
new file mode 100644
index 0000000000..bfff465227
--- /dev/null
+++ b/target/linux/ixp4xx/patches/178-via_velocity_bigendian.patch
@@ -0,0 +1,927 @@
+Index: linux-2.6.20-rc3/drivers/net/via-velocity.c
+===================================================================
+--- linux-2.6.20-rc3.orig/drivers/net/via-velocity.c	2007-01-02 10:30:25.892465963 +0000
++++ linux-2.6.20-rc3/drivers/net/via-velocity.c	2007-01-02 10:30:36.261113964 +0000
+@@ -96,11 +96,31 @@
+ MODULE_LICENSE("GPL");
+ MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
+ 
++/* Valid values for vdebug (additive, this is a bitmask):
++ *  0x00 => off
++ *  0x01 => always on
++ *  0x02 => additional detail on tx (rx, too, if anyone implements same)
++ *  0x04 => detail the initialization process
++ *  0x08 => spot debug detail; to be used as developers see fit
++ */
++static int vdebug = 0;
++
++/* HAIL - these macros are for the normal 0x01-type tracing... */
++#define HAIL(S) \
++	if (vdebug&1) printk(KERN_NOTICE "%s\n", (S));
++#define HAILS(S,T) \
++	if (vdebug&1) printk(KERN_NOTICE "%s -> status=0x%x\n", (S), (T));
++
+ #define VELOCITY_PARAM(N,D) \
+         static int N[MAX_UNITS]=OPTION_DEFAULT;\
+ 	module_param_array(N, int, NULL, 0); \
+         MODULE_PARM_DESC(N, D);
+ 
++#define VELO_DEBUG_MIN   0
++#define VELO_DEBUG_MAX   255
++#define VELO_DEBUG_DEF   0
++VELOCITY_PARAM(velo_debug, "Debug level");
++
+ #define RX_DESC_MIN     64
+ #define RX_DESC_MAX     255
+ #define RX_DESC_DEF     64
+@@ -385,12 +405,12 @@
+ 	if (val == -1)
+ 		*opt = def;
+ 	else if (val < min || val > max) {
+-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
+-					devname, name, min, max);
++		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "via-velocity: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
++					name, min, max);
+ 		*opt = def;
+ 	} else {
+-		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
+-					devname, name, val);
++		VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "via-velocity: set value of parameter %s to %d\n",
++					name, val);
+ 		*opt = val;
+ 	}
+ }
+@@ -415,12 +435,12 @@
+ 	if (val == -1)
+ 		*opt |= (def ? flag : 0);
+ 	else if (val < 0 || val > 1) {
+-		printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
+-			devname, name);
++		printk(KERN_NOTICE "via-velocity: the value of parameter %s is invalid, the valid range is (0-1)\n",
++			name);
+ 		*opt |= (def ? flag : 0);
+ 	} else {
+-		printk(KERN_INFO "%s: set parameter %s to %s\n",
+-			devname, name, val ? "TRUE" : "FALSE");
++		printk(KERN_INFO "via-velocity: set parameter %s to %s\n",
++			name, val ? "TRUE" : "FALSE");
+ 		*opt |= (val ? flag : 0);
+ 	}
+ }
+@@ -438,6 +458,7 @@
+ static void __devinit velocity_get_options(struct velocity_opt *opts, int index, char *devname)
+ {
+ 
++	velocity_set_int_opt(&opts->velo_debug, velo_debug[index], VELO_DEBUG_MIN, VELO_DEBUG_MAX, VELO_DEBUG_DEF, "velo_debug", devname);
+ 	velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
+ 	velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
+ 	velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
+@@ -452,6 +473,7 @@
+ 	velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
+ 	velocity_set_int_opt((int *) &opts->int_works, int_works[index], INT_WORKS_MIN, INT_WORKS_MAX, INT_WORKS_DEF, "Interrupt service works", devname);
+ 	opts->numrx = (opts->numrx & ~3);
++	vdebug = opts->velo_debug;
+ }
+ 
+ /**
+@@ -466,6 +488,8 @@
+ {
+ 	struct mac_regs __iomem * regs = vptr->mac_regs;
+ 
++	HAIL("velocity_init_cam_filter");
++
+ 	/* Turn on MCFG_PQEN, turn off MCFG_RTGOPT */
+ 	WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, &regs->MCFG);
+ 	WORD_REG_BITS_ON(MCFG_VIDFR, &regs->MCFG);
+@@ -484,14 +508,12 @@
+ 			WORD_REG_BITS_ON(MCFG_RTGOPT, &regs->MCFG);
+ 
+ 		mac_set_cam(regs, 0, (u8 *) & (vptr->options.vid), VELOCITY_VLAN_ID_CAM);
+-		vptr->vCAMmask[0] |= 1;
+-		mac_set_cam_mask(regs, vptr->vCAMmask, VELOCITY_VLAN_ID_CAM);
+ 	} else {
+ 		u16 temp = 0;
+ 		mac_set_cam(regs, 0, (u8 *) &temp, VELOCITY_VLAN_ID_CAM);
+-		temp = 1;
+-		mac_set_cam_mask(regs, (u8 *) &temp, VELOCITY_VLAN_ID_CAM);
+ 	}
++	vptr->vCAMmask[0] |= 1;
++	mac_set_cam_mask(regs, vptr->vCAMmask, VELOCITY_VLAN_ID_CAM);
+ }
+ 
+ /**
+@@ -508,13 +530,15 @@
+ 	struct mac_regs __iomem * regs = vptr->mac_regs;
+ 	int i;
+ 
++	HAIL("velocity_rx_reset");
+ 	vptr->rd_dirty = vptr->rd_filled = vptr->rd_curr = 0;
+ 
+ 	/*
+ 	 *	Init state, all RD entries belong to the NIC
+ 	 */
+ 	for (i = 0; i < vptr->options.numrx; ++i)
+-		vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC;
++		/* vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC; BE */
++		vptr->rd_ring[i].rdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
+ 
+ 	writew(vptr->options.numrx, &regs->RBRDU);
+ 	writel(vptr->rd_pool_dma, &regs->RDBaseLo);
+@@ -537,12 +561,15 @@
+ 	struct mac_regs __iomem * regs = vptr->mac_regs;
+ 	int i, mii_status;
+ 
++	if (vdebug&5) printk(KERN_NOTICE "velocity_init_registers: entering\n");
++
+ 	mac_wol_reset(regs);
+ 
+ 	switch (type) {
+ 	case VELOCITY_INIT_RESET:
+ 	case VELOCITY_INIT_WOL:
+ 
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: RESET or WOL\n");
+ 		netif_stop_queue(vptr->dev);
+ 
+ 		/*
+@@ -570,12 +597,13 @@
+ 
+ 	case VELOCITY_INIT_COLD:
+ 	default:
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: COLD or default\n");
+ 		/*
+ 		 *	Do reset
+ 		 */
+ 		velocity_soft_reset(vptr);
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: soft reset complete.\n");
+ 		mdelay(5);
+-
+ 		mac_eeprom_reload(regs);
+ 		for (i = 0; i < 6; i++) {
+ 			writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+@@ -593,11 +621,16 @@
+ 		 */
+ 		BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), &regs->CFGB);
+ 
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Initializing CAM filter\n");
+ 		/*
+ 		 *	Init CAM filter
+ 		 */
++		if (vdebug&8) printk(KERN_NOTICE "velocity: spot debug: about to init CAM filters\n");
++		mdelay(5);  /* MJW - ARM processors, kernel 2.6.19 - this fixes oopses and hangs */
+ 		velocity_init_cam_filter(vptr);
++		if (vdebug&8) printk(KERN_NOTICE "velocity: spot debug: init CAM filters complete\n");
+ 
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Setting packet filter\n");
+ 		/*
+ 		 *	Set packet filter: Receive directed and broadcast address
+ 		 */
+@@ -607,10 +640,12 @@
+ 		 *	Enable MII auto-polling
+ 		 */
+ 		enable_mii_autopoll(regs);
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: enable_mii_autopoll complete.\n");
+ 
+ 		vptr->int_mask = INT_MASK_DEF;
+ 
+-		writel(cpu_to_le32(vptr->rd_pool_dma), &regs->RDBaseLo);
++		/* writel(cpu_to_le32(vptr->rd_pool_dma), &regs->RDBaseLo); BE */
++		writel((vptr->rd_pool_dma), &regs->RDBaseLo); /* BE */
+ 		writew(vptr->options.numrx - 1, &regs->RDCSize);
+ 		mac_rx_queue_run(regs);
+ 		mac_rx_queue_wake(regs);
+@@ -618,10 +653,13 @@
+ 		writew(vptr->options.numtx - 1, &regs->TDCSize);
+ 
+ 		for (i = 0; i < vptr->num_txq; i++) {
+-			writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i]));
++			/* writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i])); BE */
++			writel((vptr->td_pool_dma[i]), &(regs->TDBaseLo[i])); /* BE */
+ 			mac_tx_queue_run(regs, i);
+ 		}
+ 
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: DMA settings complete.\n");
++
+ 		init_flow_control_register(vptr);
+ 
+ 		writel(CR0_STOP, &regs->CR0Clr);
+@@ -640,8 +678,10 @@
+ 
+ 		enable_flow_control_ability(vptr);
+ 		mac_hw_mibs_init(regs);
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Set interrupt mask\n");
+ 		mac_write_int_mask(vptr->int_mask, regs);
+ 		mac_clear_isr(regs);
++		if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: complete.\n");
+ 
+ 	}
+ }
+@@ -659,6 +699,7 @@
+ 	struct mac_regs __iomem * regs = vptr->mac_regs;
+ 	int i = 0;
+ 
++	HAIL("velocity_soft_reset");
+ 	writel(CR0_SFRST, &regs->CR0Set);
+ 
+ 	for (i = 0; i < W_MAX_TIMEOUT; i++) {
+@@ -722,6 +763,7 @@
+ 			VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
+ 		printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
+ 		printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
++		printk(KERN_INFO "BE support, misc. fixes MJW 01Jan2007 - may be unstable\n");
+ 		first = 0;
+ 	}
+ 
+@@ -935,6 +977,7 @@
+ 	dma_addr_t pool_dma;
+ 	u8 *pool;
+ 
++	HAIL("velocity_init_rings");
+ 	/*
+ 	 *	Allocate all RD/TD rings a single pool
+ 	 */
+@@ -997,6 +1040,7 @@
+ static void velocity_free_rings(struct velocity_info *vptr)
+ {
+ 	int size;
++	HAIL("velocity_free_rings");
+ 
+ 	size = vptr->options.numrx * sizeof(struct rx_desc) +
+ 	       vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
+@@ -1013,6 +1057,7 @@
+ 	struct mac_regs __iomem *regs = vptr->mac_regs;
+ 	int avail, dirty, unusable;
+ 
++	HAIL("velocity_give_many_rx_descs");
+ 	/*
+ 	 * RD number must be equal to 4X per hardware spec
+ 	 * (programming guide rev 1.20, p.13)
+@@ -1026,7 +1071,8 @@
+ 	dirty = vptr->rd_dirty - unusable;
+ 	for (avail = vptr->rd_filled & 0xfffc; avail; avail--) {
+ 		dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
+-		vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC;
++		/* vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC; BE */
++		vptr->rd_ring[dirty].rdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
+ 	}
+ 
+ 	writew(vptr->rd_filled & 0xfffc, &regs->RBRDU);
+@@ -1036,12 +1082,14 @@
+ static int velocity_rx_refill(struct velocity_info *vptr)
+ {
+ 	int dirty = vptr->rd_dirty, done = 0, ret = 0;
++	HAIL("velocity_rx_refill");
+ 
+ 	do {
+ 		struct rx_desc *rd = vptr->rd_ring + dirty;
+ 
+ 		/* Fine for an all zero Rx desc at init time as well */
+-		if (rd->rdesc0.owner == OWNED_BY_NIC)
++		/* if (rd->rdesc0.owner == OWNED_BY_NIC) BE */
++		if (rd->rdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
+ 			break;
+ 
+ 		if (!vptr->rd_info[dirty].skb) {
+@@ -1076,6 +1124,7 @@
+ 	unsigned int rsize = sizeof(struct velocity_rd_info) *
+ 					vptr->options.numrx;
+ 
++	HAIL("velocity_init_rd_ring");
+ 	vptr->rd_info = kmalloc(rsize, GFP_KERNEL);
+ 	if(vptr->rd_info == NULL)
+ 		goto out;
+@@ -1105,6 +1154,7 @@
+ {
+ 	int i;
+ 
++	HAIL("velocity_free_rd_ring");
+ 	if (vptr->rd_info == NULL)
+ 		return;
+ 
+@@ -1146,6 +1196,7 @@
+ 	unsigned int tsize = sizeof(struct velocity_td_info) *
+ 					vptr->options.numtx;
+ 
++	HAIL("velocity_init_td_ring");
+ 	/* Init the TD ring entries */
+ 	for (j = 0; j < vptr->num_txq; j++) {
+ 		curr = vptr->td_pool_dma[j];
+@@ -1182,6 +1233,7 @@
+ 	struct velocity_td_info * td_info = &(vptr->td_infos[q][n]);
+ 	int i;
+ 
++	HAIL("velocity_free_td_ring_entry");
+ 	if (td_info == NULL)
+ 		return;
+ 
+@@ -1211,6 +1263,7 @@
+ {
+ 	int i, j;
+ 
++	HAIL("velocity_free_td_ring");
+ 	for (j = 0; j < vptr->num_txq; j++) {
+ 		if (vptr->td_infos[j] == NULL)
+ 			continue;
+@@ -1238,34 +1291,42 @@
+ 	struct net_device_stats *stats = &vptr->stats;
+ 	int rd_curr = vptr->rd_curr;
+ 	int works = 0;
++	u16 wRSR; /* BE */
+ 
++	HAILS("velocity_rx_srv", status);
+ 	do {
+ 		struct rx_desc *rd = vptr->rd_ring + rd_curr;
+ 
+ 		if (!vptr->rd_info[rd_curr].skb)
+ 			break;
+ 
+-		if (rd->rdesc0.owner == OWNED_BY_NIC)
++		/* if (rd->rdesc0.owner == OWNED_BY_NIC) BE */
++		if (rd->rdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
+ 			break;
+ 
+ 		rmb();
+ 
++		wRSR = (u16)(cpu_to_le32(rd->rdesc0)); /* BE */
+ 		/*
+ 		 *	Don't drop CE or RL error frame although RXOK is off
+ 		 */
+-		if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) {
++		/* if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) { BE */
++		if ((wRSR & RSR_RXOK) || (!(wRSR & RSR_RXOK) && (wRSR & (RSR_CE | RSR_RL)))) { /* BE */
+ 			if (velocity_receive_frame(vptr, rd_curr) < 0)
+ 				stats->rx_dropped++;
+ 		} else {
+-			if (rd->rdesc0.RSR & RSR_CRC)
++			/* if (rd->rdesc0.RSR & RSR_CRC) BE */
++			if (wRSR & RSR_CRC) /* BE */
+ 				stats->rx_crc_errors++;
+-			if (rd->rdesc0.RSR & RSR_FAE)
++			/* if (rd->rdesc0.RSR & RSR_FAE) BE */
++			if (wRSR & RSR_FAE) /* BE */
+ 				stats->rx_frame_errors++;
+ 
+ 			stats->rx_dropped++;
+ 		}
+ 
+-		rd->inten = 1;
++		/* rd->inten = 1; BE */
++		rd->ltwo |= cpu_to_le32(BE_INT_ENABLE); /* BE */
+ 
+ 		vptr->dev->last_rx = jiffies;
+ 
+@@ -1296,13 +1357,21 @@
+ 
+ static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
+ {
++	u8 bCSM;
++	HAIL("velocity_rx_csum");
+ 	skb->ip_summed = CHECKSUM_NONE;
+ 
+-	if (rd->rdesc1.CSM & CSM_IPKT) {
+-		if (rd->rdesc1.CSM & CSM_IPOK) {
+-			if ((rd->rdesc1.CSM & CSM_TCPKT) ||
+-					(rd->rdesc1.CSM & CSM_UDPKT)) {
+-				if (!(rd->rdesc1.CSM & CSM_TUPOK)) {
++//	if (rd->rdesc1.CSM & CSM_IPKT) {
++//		if (rd->rdesc1.CSM & CSM_IPOK) {
++//			if ((rd->rdesc1.CSM & CSM_TCPKT) ||
++//					(rd->rdesc1.CSM & CSM_UDPKT)) {
++//				if (!(rd->rdesc1.CSM & CSM_TUPOK)) {
++	bCSM = (u8)(cpu_to_le32(rd->rdesc1) >> 16); /* BE */
++	if (bCSM & CSM_IPKT) {
++		if (bCSM & CSM_IPOK) {
++			if ((bCSM & CSM_TCPKT) ||
++			    (bCSM & CSM_UDPKT)) {
++				if (!(bCSM & CSM_TUPOK)) {      /* BE */
+ 					return;
+ 				}
+ 			}
+@@ -1328,9 +1397,11 @@
+ {
+ 	int ret = -1;
+ 
++	HAIL("velocity_rx_copy");
+ 	if (pkt_size < rx_copybreak) {
+ 		struct sk_buff *new_skb;
+ 
++		HAIL("velocity_rx_copy (working...)");
+ 		new_skb = dev_alloc_skb(pkt_size + 2);
+ 		if (new_skb) {
+ 			new_skb->dev = vptr->dev;
+@@ -1360,10 +1431,12 @@
+ static inline void velocity_iph_realign(struct velocity_info *vptr,
+ 					struct sk_buff *skb, int pkt_size)
+ {
++	HAIL("velocity_iph_realign");
+ 	/* FIXME - memmove ? */
+ 	if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
+ 		int i;
+ 
++		HAIL("velocity_iph_realign (working...)");
+ 		for (i = pkt_size; i >= 0; i--)
+ 			*(skb->data + i + 2) = *(skb->data + i);
+ 		skb_reserve(skb, 2);
+@@ -1382,19 +1455,27 @@
+ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
+ {
+ 	void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
++	u16 pkt_len; /* BE */
++	u16 wRSR;    /* BE */
++	struct sk_buff *skb;
+ 	struct net_device_stats *stats = &vptr->stats;
+ 	struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
+ 	struct rx_desc *rd = &(vptr->rd_ring[idx]);
+-	int pkt_len = rd->rdesc0.len;
+-	struct sk_buff *skb;
++	/* int pkt_len = rd->rdesc0.len BE */;
++
++	pkt_len = ((cpu_to_le32(rd->rdesc0) >> 16) & 0x00003FFFUL); /* BE */
++	wRSR = (u16)(cpu_to_le32(rd->rdesc0)); /* BE */
+ 
+-	if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
++	HAIL("velocity_receive_frame");
++	/* if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) { BE */
++	if (wRSR & (RSR_STP | RSR_EDP)) { /* BE */
+ 		VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+ 		stats->rx_length_errors++;
+ 		return -EINVAL;
+ 	}
+ 
+-	if (rd->rdesc0.RSR & RSR_MAR)
++	/* if (rd->rdesc0.RSR & RSR_MAR) BE */
++	if (wRSR & RSR_MAR) /* BE */
+ 		vptr->stats.multicast++;
+ 
+ 	skb = rd_info->skb;
+@@ -1408,7 +1489,8 @@
+ 	 */
+ 
+ 	if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
+-		if (rd->rdesc0.RSR & RSR_RL) {
++		/* if (rd->rdesc0.RSR & RSR_RL) { BE */
++		if (wRSR & RSR_RL) { /* BE */
+ 			stats->rx_length_errors++;
+ 			return -EINVAL;
+ 		}
+@@ -1452,6 +1534,7 @@
+ 	struct rx_desc *rd = &(vptr->rd_ring[idx]);
+ 	struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
+ 
++	HAIL("velocity_alloc_rx_buf");
+ 	rd_info->skb = dev_alloc_skb(vptr->rx_buf_sz + 64);
+ 	if (rd_info->skb == NULL)
+ 		return -ENOMEM;
+@@ -1469,10 +1552,14 @@
+  	 */
+ 
+ 	*((u32 *) & (rd->rdesc0)) = 0;
+-	rd->len = cpu_to_le32(vptr->rx_buf_sz);
+-	rd->inten = 1;
++	/* rd->len = cpu_to_le32(vptr->rx_buf_sz);		BE */
++	/* rd->inten = 1;					BE */
+ 	rd->pa_low = cpu_to_le32(rd_info->skb_dma);
+-	rd->pa_high = 0;
++	/* rd->pa_high = 0;					BE */
++	rd->ltwo &= cpu_to_le32(0xC000FFFFUL);			/* BE */
++	rd->ltwo |= cpu_to_le32((vptr->rx_buf_sz << 16));	/* BE */
++	rd->ltwo |= cpu_to_le32(BE_INT_ENABLE);			/* BE */
++	rd->ltwo &= cpu_to_le32(0xFFFF0000UL);			/* BE */
+ 	return 0;
+ }
+ 
+@@ -1493,9 +1580,11 @@
+ 	int full = 0;
+ 	int idx;
+ 	int works = 0;
++	u16 wTSR; /* BE */
+ 	struct velocity_td_info *tdinfo;
+ 	struct net_device_stats *stats = &vptr->stats;
+ 
++	HAILS("velocity_tx_srv", status);
+ 	for (qnum = 0; qnum < vptr->num_txq; qnum++) {
+ 		for (idx = vptr->td_tail[qnum]; vptr->td_used[qnum] > 0;
+ 			idx = (idx + 1) % vptr->options.numtx) {
+@@ -1506,22 +1595,29 @@
+ 			td = &(vptr->td_rings[qnum][idx]);
+ 			tdinfo = &(vptr->td_infos[qnum][idx]);
+ 
+-			if (td->tdesc0.owner == OWNED_BY_NIC)
++			/* if (td->tdesc0.owner == OWNED_BY_NIC) BE */
++			if (td->tdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
+ 				break;
+ 
+ 			if ((works++ > 15))
+ 				break;
+ 
+-			if (td->tdesc0.TSR & TSR0_TERR) {
++			wTSR = (u16)cpu_to_le32(td->tdesc0);
++			/* if (td->tdesc0.TSR & TSR0_TERR) { BE */
++			if (wTSR & TSR0_TERR) { /* BE */
+ 				stats->tx_errors++;
+ 				stats->tx_dropped++;
+-				if (td->tdesc0.TSR & TSR0_CDH)
++				/* if (td->tdesc0.TSR & TSR0_CDH) BE */
++				if (wTSR & TSR0_CDH) /* BE */
+ 					stats->tx_heartbeat_errors++;
+-				if (td->tdesc0.TSR & TSR0_CRS)
++				/* if (td->tdesc0.TSR & TSR0_CRS) BE */
++				if (wTSR & TSR0_CRS) /* BE */
+ 					stats->tx_carrier_errors++;
+-				if (td->tdesc0.TSR & TSR0_ABT)
++				/* if (td->tdesc0.TSR & TSR0_ABT) BE */
++				if (wTSR & TSR0_ABT) /* BE */
+ 					stats->tx_aborted_errors++;
+-				if (td->tdesc0.TSR & TSR0_OWC)
++				/* if (td->tdesc0.TSR & TSR0_OWC) BE */
++				if (wTSR & TSR0_OWC) /* BE */
+ 					stats->tx_window_errors++;
+ 			} else {
+ 				stats->tx_packets++;
+@@ -1610,6 +1706,7 @@
+ 
+ static void velocity_error(struct velocity_info *vptr, int status)
+ {
++	HAILS("velocity_error", status);
+ 
+ 	if (status & ISR_TXSTLI) {
+ 		struct mac_regs __iomem * regs = vptr->mac_regs;
+@@ -1699,6 +1796,7 @@
+ 	struct sk_buff *skb = tdinfo->skb;
+ 	int i;
+ 
++	HAIL("velocity_free_tx_buf");
+ 	/*
+ 	 *	Don't unmap the pre-allocated tx_bufs
+ 	 */
+@@ -1902,6 +2000,7 @@
+ 	struct velocity_td_info *tdinfo;
+ 	unsigned long flags;
+ 	int index;
++	u32 lbufsz; /* BE */
+ 
+ 	int pktlen = skb->len;
+ 
+@@ -1918,9 +2017,18 @@
+ 	td_ptr = &(vptr->td_rings[qnum][index]);
+ 	tdinfo = &(vptr->td_infos[qnum][index]);
+ 
+-	td_ptr->tdesc1.TCPLS = TCPLS_NORMAL;
+-	td_ptr->tdesc1.TCR = TCR0_TIC;
+-	td_ptr->td_buf[0].queue = 0;
++	td_ptr->tdesc0 = 0x00000000UL;				  /* BE */
++	td_ptr->tdesc1 = 0x00000000UL;				  /* BE */
++
++	/* td_ptr->tdesc1.TCPLS = TCPLS_NORMAL;		BE */
++	td_ptr->tdesc1 &= cpu_to_le32(0xfcffffffUL);		  /* BE */
++	td_ptr->tdesc1 |= cpu_to_le32(((u32)TCPLS_NORMAL) << 24); /* BE */
++
++	/* td_ptr->tdesc1.TCR = TCR0_TIC;		BE */
++	td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_TIC);		  /* BE */
++
++	/*	td_ptr->td_buf[0].queue = 0;		BE */
++	td_ptr->td_buf[0].ltwo &= cpu_to_le32(~BE_QUEUE_ENABLE);  /* BE */
+ 
+ 	/*
+ 	 *	Pad short frames.
+@@ -1932,20 +2040,35 @@
+ 		memset(tdinfo->buf + skb->len, 0, ETH_ZLEN - skb->len);
+ 		tdinfo->skb = skb;
+ 		tdinfo->skb_dma[0] = tdinfo->buf_dma;
+-		td_ptr->tdesc0.pktsize = pktlen;
++		/* td_ptr->tdesc0.pktsize = pktlen; */
++		td_ptr->tdesc0 &= cpu_to_le32(0xc000ffffUL); /* BE */
++		lbufsz = pktlen; /* Assign, and make sure it's unsigned 32 bits - BE */
++		lbufsz = lbufsz << 16; /* BE - shift over     */
++		td_ptr->tdesc0 |= cpu_to_le32(lbufsz); /* BE */
+ 		td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
+-		td_ptr->td_buf[0].pa_high = 0;
+-		td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
++		/* td_ptr->td_buf[0].pa_high = 0; */
++		/* td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; */
++		td_ptr->td_buf[0].ltwo = cpu_to_le32(lbufsz);   /* BE */
+ 		tdinfo->nskb_dma = 1;
+-		td_ptr->tdesc1.CMDZ = 2;
++		/* td_ptr->tdesc1.CMDZ = 2; */
++		td_ptr->tdesc1 &= cpu_to_le32(0x0fffffffUL); /* BE */
++		td_ptr->tdesc1 |= cpu_to_le32(((u32)0x2) << 28); /* BE */
+ 	} else
+ #ifdef VELOCITY_ZERO_COPY_SUPPORT
++	/*
++	 * BE - NOTE on the VELOCITY_ZERO_COPY_SUPPORT:
++	 * This block of code has NOT been patched up for BE support, as
++	 * it is certainly broken -- if it compiles at all.  Since the BE
++	 * fixes depend on the broken code, attempts to convert to BE support
++	 * would almost certainly confuse more than help.
++	 */
+ 	if (skb_shinfo(skb)->nr_frags > 0) {
+ 		int nfrags = skb_shinfo(skb)->nr_frags;
+ 		tdinfo->skb = skb;
+ 		if (nfrags > 6) {
+ 			memcpy(tdinfo->buf, skb->data, skb->len);
+ 			tdinfo->skb_dma[0] = tdinfo->buf_dma;
++			/* BE: Er, exactly what value are we assigning in this next line? */
+ 			td_ptr->tdesc0.pktsize =
+ 			td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
+ 			td_ptr->td_buf[0].pa_high = 0;
+@@ -1962,6 +2085,7 @@
+ 			/* FIXME: support 48bit DMA later */
+ 			td_ptr->td_buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma);
+ 			td_ptr->td_buf[i].pa_high = 0;
++			/* BE: This next line can't be right: */
+ 			td_ptr->td_buf[i].bufsize = skb->len->skb->data_len;
+ 
+ 			for (i = 0; i < nfrags; i++) {
+@@ -1979,7 +2103,7 @@
+ 		}
+ 
+ 	} else
+-#endif
++#endif /* (broken) VELOCITY_ZERO_COPY_SUPPORT */
+ 	{
+ 		/*
+ 		 *	Map the linear network buffer into PCI space and
+@@ -1987,19 +2111,30 @@
+ 		 */
+ 		tdinfo->skb = skb;
+ 		tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+-		td_ptr->tdesc0.pktsize = pktlen;
++		/* td_ptr->tdesc0.pktsize = pktlen;			BE */
++		td_ptr->tdesc0 &= cpu_to_le32(0xc000ffffUL);	/* BE */
++		lbufsz = pktlen; /* Assign, and make sure it's unsigned 32 bits - BE */
++		lbufsz = lbufsz << 16;				/* BE */
++		td_ptr->tdesc0 |= cpu_to_le32(lbufsz);		/* BE */
+ 		td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
+-		td_ptr->td_buf[0].pa_high = 0;
+-		td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
++		/* td_ptr->td_buf[0].pa_high = 0;			BE */
++		/* td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;	BE */
++		td_ptr->td_buf[0].ltwo = cpu_to_le32(lbufsz);	/* BE */
++
+ 		tdinfo->nskb_dma = 1;
+-		td_ptr->tdesc1.CMDZ = 2;
++		/* td_ptr->tdesc1.CMDZ = 2;				BE */
++		td_ptr->tdesc1 &= cpu_to_le32(0x0fffffffUL);	/* BE */
++		td_ptr->tdesc1 |= cpu_to_le32(((u32)0x2) << 28);/* BE */
+ 	}
+ 
+ 	if (vptr->flags & VELOCITY_FLAGS_TAGGING) {
+-		td_ptr->tdesc1.pqinf.VID = (vptr->options.vid & 0xfff);
+-		td_ptr->tdesc1.pqinf.priority = 0;
+-		td_ptr->tdesc1.pqinf.CFI = 0;
+-		td_ptr->tdesc1.TCR |= TCR0_VETAG;
++		/* td_ptr->tdesc1.pqinf.priority = 0;			BE */
++		/* td_ptr->tdesc1.pqinf.CFI = 0;			BE */
++		td_ptr->tdesc1 &= cpu_to_le32(0xFFFF0000UL);	/* BE */
++		/* td_ptr->tdesc1.pqinf.VID = (vptr->options.vid & 0xfff); BE */
++		td_ptr->tdesc1 |= cpu_to_le32((vptr->options.vid & 0xfff)); /* BE */
++		/* td_ptr->tdesc1.TCR |= TCR0_VETAG;			BE */
++		td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_VETAG);	/* BE */
+ 	}
+ 
+ 	/*
+@@ -2009,26 +2144,34 @@
+ 				 && (skb->ip_summed == CHECKSUM_PARTIAL)) {
+ 		struct iphdr *ip = skb->nh.iph;
+ 		if (ip->protocol == IPPROTO_TCP)
+-			td_ptr->tdesc1.TCR |= TCR0_TCPCK;
++			/* td_ptr->tdesc1.TCR |= TCR0_TCPCK;	BE */
++			td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_TCPCK);	/* BE */
+ 		else if (ip->protocol == IPPROTO_UDP)
+-			td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
+-		td_ptr->tdesc1.TCR |= TCR0_IPCK;
+-	}
++			/* td_ptr->tdesc1.TCR |= (TCR0_UDPCK);	BE */
++			td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_UDPCK);	/* BE */
++		/* td_ptr->tdesc1.TCR |= TCR0_IPCK;		BE */
++		td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_IPCK);		/* BE */
++ 	}
+ 	{
+ 
+ 		int prev = index - 1;
+ 
+ 		if (prev < 0)
+ 			prev = vptr->options.numtx - 1;
+-		td_ptr->tdesc0.owner = OWNED_BY_NIC;
++		/* td_ptr->tdesc0.owner = OWNED_BY_NIC; BE */
++		td_ptr->tdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
+ 		vptr->td_used[qnum]++;
+ 		vptr->td_curr[qnum] = (index + 1) % vptr->options.numtx;
+ 
+ 		if (AVAIL_TD(vptr, qnum) < 1)
+ 			netif_stop_queue(dev);
+ 
+-		td_ptr = &(vptr->td_rings[qnum][prev]);
+-		td_ptr->td_buf[0].queue = 1;
++ 		td_ptr = &(vptr->td_rings[qnum][prev]);
++ 		/* td_ptr->td_buf[0].queue = 1; BE */
++ 		td_ptr->td_buf[0].ltwo |= cpu_to_le32(BE_QUEUE_ENABLE); /* BE */
++		if (vdebug&2) printk(KERN_NOTICE "velocity_xmit: (%s) len=%d idx=%d tdesc0=0x%x tdesc1=0x%x ltwo=0x%x\n",
++			(pktlen<ETH_ZLEN) ? "short" : "normal", pktlen, index,
++			td_ptr->tdesc0, td_ptr->tdesc1, td_ptr->td_buf[0].ltwo);
+ 		mac_tx_queue_wake(vptr->mac_regs, qnum);
+ 	}
+ 	dev->trans_start = jiffies;
+@@ -2054,7 +2197,7 @@
+ 	u32 isr_status;
+ 	int max_count = 0;
+ 
+-
++	HAIL("velocity_intr");
+ 	spin_lock(&vptr->lock);
+ 	isr_status = mac_read_isr(vptr->mac_regs);
+ 
+@@ -2073,7 +2216,10 @@
+ 
+ 	while (isr_status != 0) {
+ 		mac_write_isr(vptr->mac_regs, isr_status);
+-		if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
++		HAILS("velocity_intr",isr_status);
++		/* MJW - velocity_error is ALWAYS called; need to mask off some other flags */
++		/* if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI))) */
++		if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI | ISR_PTX0I | ISR_ISR0)))
+ 			velocity_error(vptr, isr_status);
+ 		if (isr_status & (ISR_PRXI | ISR_PPRXI))
+ 			max_count += velocity_rx_srv(vptr, isr_status);
+@@ -2111,6 +2257,7 @@
+ 	int i;
+ 	struct dev_mc_list *mclist;
+ 
++	HAIL("velocity_set_multi");
+ 	if (dev->flags & IFF_PROMISC) {	/* Set promiscuous. */
+ 		writel(0xffffffff, &regs->MARCAM[0]);
+ 		writel(0xffffffff, &regs->MARCAM[4]);
+@@ -2154,6 +2301,7 @@
+ {
+ 	struct velocity_info *vptr = netdev_priv(dev);
+ 
++	HAIL("net_device_stats");
+ 	/* If the hardware is down, don't touch MII */
+ 	if(!netif_running(dev))
+ 		return &vptr->stats;
+@@ -2198,6 +2346,7 @@
+ 	struct velocity_info *vptr = netdev_priv(dev);
+ 	int ret;
+ 
++	HAIL("velocity_ioctl");
+ 	/* If we are asked for information and the device is power
+ 	   saving then we need to bring the device back up to talk to it */
+ 
+@@ -2416,6 +2565,7 @@
+ {
+ 	u16 ww;
+ 
++	HAIL("velocity_mii_read");
+ 	/*
+ 	 *	Disable MIICR_MAUTO, so that mii addr can be set normally
+ 	 */
+@@ -2452,6 +2602,7 @@
+ {
+ 	u16 ww;
+ 
++	HAIL("velocity_mii_write");
+ 	/*
+ 	 *	Disable MIICR_MAUTO, so that mii addr can be set normally
+ 	 */
+Index: linux-2.6.20-rc3/drivers/net/via-velocity.h
+===================================================================
+--- linux-2.6.20-rc3.orig/drivers/net/via-velocity.h	2006-11-29 21:57:37.000000000 +0000
++++ linux-2.6.20-rc3/drivers/net/via-velocity.h	2007-01-02 10:30:36.265114211 +0000
+@@ -196,64 +196,70 @@
+  *	Receive descriptor
+  */
+ 
+-struct rdesc0 {
+-	u16 RSR;		/* Receive status */
+-	u16 len:14;		/* Received packet length */
+-	u16 reserved:1;
+-	u16 owner:1;		/* Who owns this buffer ? */
+-};
+-
+-struct rdesc1 {
+-	u16 PQTAG;
+-	u8 CSM;
+-	u8 IPKT;
+-};
++//struct rdesc0 {
++//	u16 RSR;		/* Receive status */
++//	u16 len:14;		/* Received packet length */
++//	u16 reserved:1;
++//	u16 owner:1;		/* Who owns this buffer ? */
++//};
++
++//struct rdesc1 {
++//	u16 PQTAG;
++//	u8 CSM;
++//	u8 IPKT;
++//};
+ 
+ struct rx_desc {
+-	struct rdesc0 rdesc0;
+-	struct rdesc1 rdesc1;
++//	struct rdesc0 rdesc0;
++//	struct rdesc1 rdesc1;
++	u32 rdesc0;
++	u32 rdesc1;
+ 	u32 pa_low;		/* Low 32 bit PCI address */
+-	u16 pa_high;		/* Next 16 bit PCI address (48 total) */
+-	u16 len:15;		/* Frame size */
+-	u16 inten:1;		/* Enable interrupt */
++//	u16 pa_high;		/* Next 16 bit PCI address (48 total) */
++//	u16 len:15;		/* Frame size */
++//	u16 inten:1;		/* Enable interrupt */
++	u32 ltwo;
+ } __attribute__ ((__packed__));
+ 
+ /*
+  *	Transmit descriptor
+  */
+ 
+-struct tdesc0 {
+-	u16 TSR;		/* Transmit status register */
+-	u16 pktsize:14;		/* Size of frame */
+-	u16 reserved:1;
+-	u16 owner:1;		/* Who owns the buffer */
+-};
+-
+-struct pqinf {			/* Priority queue info */
+-	u16 VID:12;
+-	u16 CFI:1;
+-	u16 priority:3;
+-} __attribute__ ((__packed__));
+-
+-struct tdesc1 {
+-	struct pqinf pqinf;
+-	u8 TCR;
+-	u8 TCPLS:2;
+-	u8 reserved:2;
+-	u8 CMDZ:4;
+-} __attribute__ ((__packed__));
++//struct tdesc0 {
++//	u16 TSR;		/* Transmit status register */
++//	u16 pktsize:14;		/* Size of frame */
++//	u16 reserved:1;
++//	u16 owner:1;		/* Who owns the buffer */
++//};
++
++//struct pqinf {			/* Priority queue info */
++//	u16 VID:12;
++//	u16 CFI:1;
++//	u16 priority:3;
++//} __attribute__ ((__packed__));
++
++//struct tdesc1 {
++//	struct pqinf pqinf;
++//	u8 TCR;
++//	u8 TCPLS:2;
++//	u8 reserved:2;
++//	u8 CMDZ:4;
++//} __attribute__ ((__packed__));
+ 
+ struct td_buf {
+ 	u32 pa_low;
+-	u16 pa_high;
+-	u16 bufsize:14;
+-	u16 reserved:1;
+-	u16 queue:1;
++//	u16 pa_high;
++//	u16 bufsize:14;
++//	u16 reserved:1;
++//	u16 queue:1;
++	u32 ltwo;
+ } __attribute__ ((__packed__));
+ 
+ struct tx_desc {
+-	struct tdesc0 tdesc0;
+-	struct tdesc1 tdesc1;
++//	struct tdesc0 tdesc0;
++//	struct tdesc1 tdesc1;
++	u32 tdesc0;
++	u32 tdesc1;
+ 	struct td_buf td_buf[7];
+ };
+ 
+@@ -279,6 +285,16 @@
+ 	OWNED_BY_NIC = 1
+ };
+ 
++/* Constants added for the BE fixes */
++#define BE_OWNED_BY_NIC    0x80000000UL
++#define BE_INT_ENABLE      0x80000000UL
++#define BE_QUEUE_ENABLE    0x80000000UL
++#define BE_TCR_TIC         0x00800000UL
++#define BE_TCR_VETAG       0x00200000UL
++#define BE_TCR_TCPCK       0x00040000UL
++#define BE_TCR_UDPCK       0x00080000UL
++#define BE_TCR_IPCK        0x00100000UL
++
+ 
+ /*
+  *	MAC registers and macros.
+@@ -1698,6 +1714,7 @@
+ };
+ 
+ struct velocity_opt {
++	int velo_debug;                 /* debug flag */
+ 	int numrx;			/* Number of RX descriptors */
+ 	int numtx;			/* Number of TX descriptors */
+ 	enum speed_opt spd_dpx;		/* Media link mode */
diff --git a/target/linux/ixp4xx/patches/185-nslu2_rtc_fixup.patch b/target/linux/ixp4xx/patches/185-nslu2_rtc_fixup.patch
new file mode 100644
index 0000000000..2c379d2648
--- /dev/null
+++ b/target/linux/ixp4xx/patches/185-nslu2_rtc_fixup.patch
@@ -0,0 +1,54 @@
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -20,6 +20,7 @@
+ #include <linux/leds.h>
+ #include <linux/mtd/mtd.h>
+ 
++#include <asm/setup.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
+@@ -239,11 +240,41 @@ static void __init nslu2_init(void)
+ 	register_mtd_user(&nslu2_flash_notifier);
+ }
+ 
++static char nslu2_rtc_probe[] __initdata = "rtc-x1205.probe=0,0x6f ";
++
++static void __init nslu2_fixup(struct machine_desc *desc,
++		struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++	struct tag *t = tags;
++	char *p = *cmdline;
++
++	/* Find the end of the tags table, taking note of any cmdline tag. */
++	for (; t->hdr.size; t = tag_next(t)) {
++		if (t->hdr.tag == ATAG_CMDLINE) {
++			p = t->u.cmdline.cmdline;
++		}
++	}
++
++	/* Overwrite the end of the table with a new cmdline tag. */
++	t->hdr.tag = ATAG_CMDLINE;
++	t->hdr.size = (sizeof (struct tag_header) +
++		       strlen(nslu2_rtc_probe) + strlen(p) + 1 + 4) >> 2;
++	strlcpy(t->u.cmdline.cmdline, nslu2_rtc_probe, COMMAND_LINE_SIZE);
++	strlcpy(t->u.cmdline.cmdline + strlen(nslu2_rtc_probe), p,
++		COMMAND_LINE_SIZE - strlen(nslu2_rtc_probe));
++
++	/* Terminate the table. */
++	t = tag_next(t);
++	t->hdr.tag = ATAG_NONE;
++	t->hdr.size = 0;
++}
++
+ MACHINE_START(NSLU2, "Linksys NSLU2")
+ 	/* Maintainer: www.nslu2-linux.org */
+ 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+ 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+ 	.boot_params	= 0x00000100,
++	.fixup          = nslu2_fixup,
+ 	.map_io		= ixp4xx_map_io,
+ 	.init_irq	= ixp4xx_init_irq,
+ 	.timer          = &ixp4xx_timer,
diff --git a/target/linux/ixp4xx/patches/186-nas100d_rtc_fixup.patch b/target/linux/ixp4xx/patches/186-nas100d_rtc_fixup.patch
new file mode 100644
index 0000000000..f594802d2f
--- /dev/null
+++ b/target/linux/ixp4xx/patches/186-nas100d_rtc_fixup.patch
@@ -0,0 +1,55 @@
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -18,6 +18,7 @@
+ #include <linux/leds.h>
+ #include <linux/mtd/mtd.h>
+ 
++#include <asm/setup.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
+@@ -225,11 +226,42 @@ static void __init nas100d_init(void)
+ 	register_mtd_user(&nas100d_flash_notifier);
+ }
+ 
++static char nas100d_rtc_probe[] __initdata = "rtc-pcf8563.probe=0,0x51 ";
++
++static void __init nas100d_fixup(struct machine_desc *desc,
++		struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++	struct tag *t = tags;
++	char *p = *cmdline;
++
++	/* Find the end of the tags table, taking note of any cmdline tag. */
++	for (; t->hdr.size; t = tag_next(t)) {
++		if (t->hdr.tag == ATAG_CMDLINE) {
++			p = t->u.cmdline.cmdline;
++		}
++	}
++
++	/* Overwrite the end of the table with a new cmdline tag. */
++	t->hdr.tag = ATAG_CMDLINE;
++	t->hdr.size =
++		(sizeof (struct tag_header) +
++		 strlen(nas100d_rtc_probe) + strlen(p) + 1 + 4) >> 2;
++	strlcpy(t->u.cmdline.cmdline, nas100d_rtc_probe, COMMAND_LINE_SIZE);
++	strlcpy(t->u.cmdline.cmdline + strlen(nas100d_rtc_probe), p,
++		COMMAND_LINE_SIZE - strlen(nas100d_rtc_probe));
++
++	/* Terminate the table. */
++	t = tag_next(t);
++	t->hdr.tag = ATAG_NONE;
++	t->hdr.size = 0;
++}
++
+ MACHINE_START(NAS100D, "Iomega NAS 100d")
+ 	/* Maintainer: www.nslu2-linux.org */
+ 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+ 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+ 	.boot_params	= 0x00000100,
++	.fixup          = nas100d_fixup,
+ 	.map_io		= ixp4xx_map_io,
+ 	.init_irq	= ixp4xx_init_irq,
+ 	.timer          = &ixp4xx_timer,
diff --git a/target/linux/ixp4xx/patches/187-dsmg600_rtc_fixup.patch b/target/linux/ixp4xx/patches/187-dsmg600_rtc_fixup.patch
new file mode 100644
index 0000000000..04e51cd0c3
--- /dev/null
+++ b/target/linux/ixp4xx/patches/187-dsmg600_rtc_fixup.patch
@@ -0,0 +1,57 @@
+Index: linux-2.6.21-arm/arch/arm/mach-ixp4xx/dsmg600-setup.c
+===================================================================
+--- linux-2.6.21-arm.orig/arch/arm/mach-ixp4xx/dsmg600-setup.c	2007-05-07 11:29:44.000000000 -0700
++++ linux-2.6.21-arm/arch/arm/mach-ixp4xx/dsmg600-setup.c	2007-05-07 11:31:15.000000000 -0700
+@@ -15,6 +15,7 @@
+ #include <linux/serial.h>
+ #include <linux/serial_8250.h>
+ 
++#include <asm/setup.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
+@@ -142,6 +143,36 @@
+     .init   = dsmg600_timer_init,
+ };
+ 
++static char dsmg600_rtc_probe[] __initdata = "rtc-pcf8563.probe=0,0x51 ";
++
++static void __init dsmg600_fixup(struct machine_desc *desc,
++                struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++    struct tag *t = tags;
++    char *p = *cmdline;
++
++    /* Find the end of the tags table, taking note of any cmdline tag. */
++    for (; t->hdr.size; t = tag_next(t)) {
++        if (t->hdr.tag == ATAG_CMDLINE) {
++            p = t->u.cmdline.cmdline;
++        }
++    }   
++
++    /* Overwrite the end of the table with a new cmdline tag. */
++    t->hdr.tag = ATAG_CMDLINE;
++    t->hdr.size =
++        (sizeof (struct tag_header) +
++        strlen(dsmg600_rtc_probe) + strlen(p) + 1 + 4) >> 2;
++    strlcpy(t->u.cmdline.cmdline, dsmg600_rtc_probe, COMMAND_LINE_SIZE);
++    strlcpy(t->u.cmdline.cmdline + strlen(dsmg600_rtc_probe), p,
++        COMMAND_LINE_SIZE - strlen(dsmg600_rtc_probe));
++
++    /* Terminate the table. */
++    t = tag_next(t);
++    t->hdr.tag = ATAG_NONE;
++    t->hdr.size = 0;
++}
++
+ static void __init dsmg600_init(void)
+ {
+ 	ixp4xx_sys_init();
+@@ -174,6 +205,7 @@
+ 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+ 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+ 	.boot_params	= 0x00000100,
++	.fixup		= dsmg600_fixup,
+ 	.map_io		= ixp4xx_map_io,
+ 	.init_irq	= ixp4xx_init_irq,
+ 	.timer          = &dsmg600_timer,
diff --git a/target/linux/ixp4xx/patches/200-gateway_7001.patch b/target/linux/ixp4xx/patches/200-gateway_7001.patch
new file mode 100644
index 0000000000..80cf000796
--- /dev/null
+++ b/target/linux/ixp4xx/patches/200-gateway_7001.patch
@@ -0,0 +1,250 @@
+diff -Nur linux-2.6.19.2/arch/arm/boot/compressed/head-xscale.S linux-2.6.19.2-owrt/arch/arm/boot/compressed/head-xscale.S
+--- linux-2.6.19.2/arch/arm/boot/compressed/head-xscale.S	2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/boot/compressed/head-xscale.S	2007-04-02 15:39:28.000000000 +0200
+@@ -46,6 +46,11 @@
+                orr     r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00)
+ #endif
+ 
++#ifdef  CONFIG_MACH_GATEWAY7001
++               mov     r7, #(MACH_TYPE_GATEWAY7001 & 0xff)
++               orr     r7, r7, #(MACH_TYPE_GATEWAY7001 & 0xff00)
++#endif
++
+ #ifdef CONFIG_ARCH_IXP2000
+ 		mov	r1, #-1
+ 		mov	r0, #0xd6000000
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/gateway7001-pci.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/gateway7001-pci.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/gateway7001-pci.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/gateway7001-pci.c	2007-04-02 15:39:28.000000000 +0200
+@@ -0,0 +1,68 @@
++/*
++ * arch/arch/mach-ixp4xx/gateway7001-pci.c
++ *
++ * PCI setup routines for Gateway 7001
++ *
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ *	Copyright (C) 2002 Jungo Software Technologies.
++ *	Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init gateway7001_pci_preinit(void)
++{
++	set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
++	set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++
++	ixp4xx_pci_preinit();
++}
++
++static int __init gateway7001_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	if (slot == 1)
++		return IRQ_IXP4XX_GPIO11;
++	else if (slot == 2)
++		return IRQ_IXP4XX_GPIO10;
++	else return -1;
++}
++
++struct hw_pci gateway7001_pci __initdata = {
++	.nr_controllers = 1,
++	.preinit =        gateway7001_pci_preinit,
++	.swizzle =        pci_std_swizzle,
++	.setup =          ixp4xx_setup,
++	.scan =           ixp4xx_scan_bus,
++	.map_irq =        gateway7001_map_irq,
++};
++
++int __init gateway7001_pci_init(void)
++{
++	if (machine_is_gateway7001())
++		pci_common_init(&gateway7001_pci);
++	return 0;
++}
++
++subsys_initcall(gateway7001_pci_init);
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/gateway7001-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/gateway7001-setup.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c	2007-04-02 15:49:28.000000000 +0200
+@@ -0,0 +1,108 @@
++/*
++ * arch/arm/mach-ixp4xx/gateway7001-setup.c
++ *
++ * Board setup for the Gateway 7001 board
++ *
++ * Copyright (C) 2006 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ *      Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data gateway7001_flash_data = {
++	.map_name	= "cfi_probe",
++	.width		= 2,
++};
++
++static struct resource gateway7001_flash_resource = {
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct platform_device gateway7001_flash = {
++	.name		= "IXP4XX-Flash",
++	.id		= 0,
++	.dev		= {
++		.platform_data = &gateway7001_flash_data,
++	},
++	.num_resources	= 1,
++	.resource	= &gateway7001_flash_resource,
++};
++
++static struct resource gateway7001_uart_resource = {
++	.start	= IXP4XX_UART2_BASE_PHYS,
++	.end	= IXP4XX_UART2_BASE_PHYS + 0x0fff,
++	.flags	= IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port gateway7001_uart_data[] = {
++	{
++		.mapbase	= IXP4XX_UART2_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART2,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{ },
++};
++
++static struct platform_device gateway7001_uart = {
++	.name		= "serial8250",
++	.id		= PLAT8250_DEV_PLATFORM,
++	.dev			= {
++		.platform_data	= gateway7001_uart_data,
++	},
++	.num_resources	= 1,
++	.resource	= &gateway7001_uart_resource,
++};
++
++static struct platform_device *gateway7001_devices[] __initdata = {
++	&gateway7001_flash,
++	&gateway7001_uart
++};
++
++static void __init gateway7001_init(void)
++{
++	ixp4xx_sys_init();
++
++	gateway7001_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++	gateway7001_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++	*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++	platform_add_devices(gateway7001_devices, ARRAY_SIZE(gateway7001_devices));
++}
++
++#ifdef CONFIG_MACH_GATEWAY7001
++MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
++	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
++	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++	.map_io		= ixp4xx_map_io,
++	.init_irq	= ixp4xx_init_irq,
++	.timer		= &ixp4xx_timer,
++	.boot_params	= 0x0100,
++	.init_machine	= gateway7001_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig	2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig	2007-04-02 15:39:28.000000000 +0200
+@@ -33,6 +33,14 @@
+ 	  Engineering Coyote Gateway Reference Platform. For more
+ 	  information on this platform, see <file:Documentation/arm/IXP4xx>.
+ 
++config MACH_GATEWAY7001
++	bool "Gateway 7001"
++	select PCI
++	help
++	  Say 'Y' here if you want your kernel to support Gateway's 
++	  7001 Access Point. For more information on this platform,
++	  see http://openwrt.org
++
+ config ARCH_IXDP425
+ 	bool "IXDP425"
+ 	help
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile	2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile	2007-04-02 15:49:49.000000000 +0200
+@@ -11,6 +11,7 @@
+ obj-pci-$(CONFIG_MACH_NSLU2)		+= nslu2-pci.o
+ obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
+ obj-pci-$(CONFIG_MACH_DSMG600)		+= dsmg600-pci.o
++obj-pci-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-pci.o
+ 
+ obj-y	+= common.o
+ 
+@@ -20,5 +21,6 @@
+ obj-$(CONFIG_MACH_NSLU2)	+= nslu2-setup.o nslu2-power.o
+ obj-$(CONFIG_MACH_NAS100D)	+= nas100d-setup.o nas100d-power.o
+ obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o dsmg600-power.o
++obj-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-setup.o
+ 
+ obj-$(CONFIG_PCI)		+= $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff -Nur linux-2.6.19.2/include/asm-arm/arch-ixp4xx/uncompress.h linux-2.6.19.2-owrt/include/asm-arm/arch-ixp4xx/uncompress.h
+--- linux-2.6.19.2/include/asm-arm/arch-ixp4xx/uncompress.h	2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2-owrt/include/asm-arm/arch-ixp4xx/uncompress.h	2007-04-02 15:42:04.000000000 +0200
+@@ -38,9 +38,9 @@
+ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+ {
+ 	/*
+-	 * Coyote and gtwx5715 only have UART2 connected
++	 * Some boards are using UART2 as console
+ 	 */
+-	if (machine_is_adi_coyote() || machine_is_gtwx5715())
++	if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001())
+ 		uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ 	else
+ 		uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/target/linux/ixp4xx/patches/210-gateway_7001_setup_mac.patch b/target/linux/ixp4xx/patches/210-gateway_7001_setup_mac.patch
new file mode 100644
index 0000000000..8b3f4b92c5
--- /dev/null
+++ b/target/linux/ixp4xx/patches/210-gateway_7001_setup_mac.patch
@@ -0,0 +1,62 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/gateway7001-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/gateway7001-setup.c	2007-04-02 15:56:39.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c	2007-04-02 15:57:38.000000000 +0200
+@@ -76,9 +76,57 @@
+ 	.resource	= &gateway7001_uart_resource,
+ };
+ 
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct resource res_mac1 = {
++	.start		= IXP4XX_EthC_BASE_PHYS,
++	.end		= IXP4XX_EthC_BASE_PHYS + 0x1ff,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= 1,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct mac_plat_info plat_mac1 = {
++	.npe_id		= 2,
++	.phy_id		= 2,
++	.eth_id		= 1,
++	.rxq_id		= 28,
++	.txq_id		= 25,
++	.rxdoneq_id	= 5,
++};
++
++static struct platform_device mac0 = {
++	.name		= "ixp4xx_mac",
++	.id		= 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources	= 1,
++	.resource	= &res_mac0,
++};
++
++static struct platform_device mac1 = {
++	.name		= "ixp4xx_mac",
++	.id		= 1,
++	.dev.platform_data = &plat_mac1,
++	.num_resources	= 1,
++	.resource	= &res_mac1,
++};
++
+ static struct platform_device *gateway7001_devices[] __initdata = {
+ 	&gateway7001_flash,
+-	&gateway7001_uart
++	&gateway7001_uart,
++	&mac0,
++	&mac1,
+ };
+ 
+ static void __init gateway7001_init(void)
diff --git a/target/linux/ixp4xx/patches/212-gateway_7001_mtd_microcode.patch b/target/linux/ixp4xx/patches/212-gateway_7001_mtd_microcode.patch
new file mode 100644
index 0000000000..c15c5f66a8
--- /dev/null
+++ b/target/linux/ixp4xx/patches/212-gateway_7001_mtd_microcode.patch
@@ -0,0 +1,67 @@
+--- linux-2.6.21.5/arch/arm/mach-ixp4xx/gateway7001-setup.c.orig	2007-06-19 18:03:37.202848276 +0100
++++ linux-2.6.21.5/arch/arm/mach-ixp4xx/gateway7001-setup.c	2007-06-19 18:09:04.152969985 +0100
+@@ -16,6 +16,7 @@
+ #include <linux/device.h>
+ #include <linux/serial.h>
+ #include <linux/tty.h>
++#include <linux/mtd/mtd.h>
+ #include <linux/serial_8250.h>
+ #include <linux/slab.h>
+ 
+@@ -122,11 +123,48 @@
+ 	.resource	= &res_mac1,
+ };
+ 
++struct npe_ucode_platform_data gateway7001_npe_ucode_data = {
++	.mtd_partition  = "microcode",
++};
++
++static struct platform_device gateway7001_npe_ucode = {
++	.name                   = "ixp4xx_npe_ucode",
++	.id                     = 0,
++	.dev.platform_data      = &gateway7001_npe_ucode_data,
++};
++
+ static struct platform_device *gateway7001_devices[] __initdata = {
+ 	&gateway7001_flash,
+ 	&gateway7001_uart,
+ 	&mac0,
+ 	&mac1,
++	&gateway7001_npe_ucode,
++};
++
++static void gateway7001_flash_add(struct mtd_info *mtd) 
++{
++	if (strcmp(mtd->name, "RedBoot config") == 0) {
++		size_t retlen;
++		u_char mac0[6], mac1[6];
++			if (mtd->read(mtd, 0x0422, 6, &retlen, mac0) == 0 && retlen == 6) {
++				printk(KERN_INFO "gateway 7001 mac0: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++					mac0[0], mac0[1], mac0[2], mac0[3], mac0[4], mac0[5]);
++				memcpy(plat_mac0.hwaddr, mac0, 6);
++			}
++			if (mtd->read(mtd, 0x043B, 6, &retlen, mac1) == 0 && retlen == 6) {
++				printk(KERN_INFO "gateway 7001 mac1: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++					mac1[0], mac1[1], mac1[2], mac1[3], mac1[4], mac1[5]);
++				memcpy(plat_mac1.hwaddr, mac1, 6);
++		}
++	}
++}
++
++static void gateway7001_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier gateway7001_flash_notifier = {
++	.add = gateway7001_flash_add,
++	.remove = gateway7001_flash_remove,
+ };
+ 
+ static void __init gateway7001_init(void)
+@@ -140,6 +178,7 @@
+ 	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+ 
+ 	platform_add_devices(gateway7001_devices, ARRAY_SIZE(gateway7001_devices));
++	register_mtd_user(&gateway7001_flash_notifier);
+ }
+ 
+ #ifdef CONFIG_MACH_GATEWAY7001
diff --git a/target/linux/ixp4xx/patches/300-wg302v2.patch b/target/linux/ixp4xx/patches/300-wg302v2.patch
new file mode 100644
index 0000000000..8dc1d72d9e
--- /dev/null
+++ b/target/linux/ixp4xx/patches/300-wg302v2.patch
@@ -0,0 +1,231 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig	2007-04-02 16:09:06.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig	2007-04-02 16:01:25.000000000 +0200
+@@ -41,6 +41,14 @@
+ 	  7001 Access Point. For more information on this platform,
+ 	  see http://openwrt.org
+ 
++config MACH_WG302V2
++	bool "Netgear WG302 v2 / WAG302 v2"
++	select PCI
++	help
++	  Say 'Y' here if you want your kernel to support Netgear's 
++	  WG302 v2 or WAG302 v2 Access Points. For more information
++	  on this platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ 	bool "IXDP425"
+ 	help
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile	2007-04-02 16:09:06.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile	2007-04-02 16:09:25.000000000 +0200
+@@ -12,6 +12,7 @@
+ obj-pci-$(CONFIG_MACH_NSLU2)		+= nslu2-pci.o
+ obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
+ obj-pci-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-pci.o
++obj-pci-$(CONFIG_MACH_WG302V2)		+= wg302v2-pci.o
+ 
+ obj-y	+= common.o
+ 
+@@ -22,5 +23,6 @@
+ obj-$(CONFIG_MACH_NSLU2)	+= nslu2-setup.o nslu2-power.o
+ obj-$(CONFIG_MACH_NAS100D)	+= nas100d-setup.o nas100d-power.o
+ obj-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-setup.o
++obj-$(CONFIG_MACH_WG302V2)	+= wg302v2-setup.o
+ 
+ obj-$(CONFIG_PCI)		+= $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/wg302v2-pci.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wg302v2-pci.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/wg302v2-pci.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wg302v2-pci.c	2007-04-02 16:00:12.000000000 +0200
+@@ -0,0 +1,68 @@
++/*
++ * arch/arch/mach-ixp4xx/wg302v2-pci.c
++ *
++ * PCI setup routines for the Netgear WG302 v2 and WAG302 v2
++ *
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ *	Copyright (C) 2002 Jungo Software Technologies.
++ *	Copyright (C) 2003 MontaVista Software, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init wg302v2_pci_preinit(void)
++{
++	set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
++	set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
++
++	ixp4xx_pci_preinit();
++}
++
++static int __init wg302v2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	if (slot == 1)
++		return IRQ_IXP4XX_GPIO8;
++	else if (slot == 2)
++		return IRQ_IXP4XX_GPIO9;
++	else return -1;
++}
++
++struct hw_pci wg302v2_pci __initdata = {
++	.nr_controllers = 1,
++	.preinit =        wg302v2_pci_preinit,
++	.swizzle =        pci_std_swizzle,
++	.setup =          ixp4xx_setup,
++	.scan =           ixp4xx_scan_bus,
++	.map_irq =        wg302v2_map_irq,
++};
++
++int __init wg302v2_pci_init(void)
++{
++	if (machine_is_wg302v2())
++		pci_common_init(&wg302v2_pci);
++	return 0;
++}
++
++subsys_initcall(wg302v2_pci_init);
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/wg302v2-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/wg302v2-setup.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c	2007-04-02 16:08:57.000000000 +0200
+@@ -0,0 +1,107 @@
++/*
++ * arch/arm/mach-ixp4xx/wg302-setup.c
++ *
++ * Board setup for the Netgear WG302 v2 and WAG302 v2
++ *
++ * based on coyote-setup.c:
++ *     Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data wg302v2_flash_data = {
++	.map_name	= "cfi_probe",
++	.width		= 2,
++};
++
++static struct resource wg302v2_flash_resource = {
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct platform_device wg302v2_flash = {
++	.name		= "IXP4XX-Flash",
++	.id		= 0,
++	.dev		= {
++		.platform_data = &wg302v2_flash_data,
++	},
++	.num_resources	= 1,
++	.resource	= &wg302v2_flash_resource,
++};
++
++static struct resource wg302v2_uart_resource = {
++	.start	= IXP4XX_UART2_BASE_PHYS,
++	.end	= IXP4XX_UART2_BASE_PHYS + 0x0fff,
++	.flags	= IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port wg302v2_uart_data[] = {
++	{
++		.mapbase	= IXP4XX_UART2_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART2,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{ },
++};
++
++static struct platform_device wg302v2_uart = {
++	.name		= "serial8250",
++	.id		= PLAT8250_DEV_PLATFORM,
++	.dev			= {
++		.platform_data	= wg302v2_uart_data,
++	},
++	.num_resources	= 1,
++	.resource	= &wg302v2_uart_resource,
++};
++
++static struct platform_device *wg302v2_devices[] __initdata = {
++	&wg302v2_flash,
++	&wg302v2_uart,
++};
++
++static void __init wg302v2_init(void)
++{
++	ixp4xx_sys_init();
++
++	wg302v2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++	wg302v2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++	*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++	platform_add_devices(wg302v2_devices, ARRAY_SIZE(wg302v2_devices));
++}
++
++#ifdef CONFIG_MACH_WG302V2
++MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
++	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
++	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++	.map_io		= ixp4xx_map_io,
++	.init_irq	= ixp4xx_init_irq,
++	.timer		= &ixp4xx_timer,
++	.boot_params	= 0x0100,
++	.init_machine	= wg302v2_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.19.2/include/asm-arm/arch-ixp4xx/uncompress.h linux-2.6.19.2-owrt/include/asm-arm/arch-ixp4xx/uncompress.h
+--- linux-2.6.19.2/include/asm-arm/arch-ixp4xx/uncompress.h	2007-04-02 16:09:06.000000000 +0200
++++ linux-2.6.19.2-owrt/include/asm-arm/arch-ixp4xx/uncompress.h	2007-04-02 16:02:04.000000000 +0200
+@@ -40,7 +40,7 @@
+ 	/*
+ 	 * Some boards are using UART2 as console
+ 	 */
+-	if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001())
++	if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2())
+ 		uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ 	else
+ 		uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/target/linux/ixp4xx/patches/310-wg302v2_setup_mac.patch b/target/linux/ixp4xx/patches/310-wg302v2_setup_mac.patch
new file mode 100644
index 0000000000..27616e15b3
--- /dev/null
+++ b/target/linux/ixp4xx/patches/310-wg302v2_setup_mac.patch
@@ -0,0 +1,37 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/wg302v2-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/wg302v2-setup.c	2007-04-02 16:06:02.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c	2007-03-05 11:57:24.000000000 +0100
+@@ -75,9 +75,33 @@
+ 	.resource	= &wg302v2_uart_resource,
+ };
+ 
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= 8,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct platform_device mac0 = {
++	.name		= "ixp4xx_mac",
++	.id		= 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources	= 1,
++	.resource	= &res_mac0,
++};
++
+ static struct platform_device *wg302v2_devices[] __initdata = {
+ 	&wg302v2_flash,
+ 	&wg302v2_uart,
++	&mac0,
+ };
+ 
+ static void __init wg302v2_init(void)
diff --git a/target/linux/ixp4xx/patches/400-pronghorn_metro.patch b/target/linux/ixp4xx/patches/400-pronghorn_metro.patch
new file mode 100644
index 0000000000..8b88e106e1
--- /dev/null
+++ b/target/linux/ixp4xx/patches/400-pronghorn_metro.patch
@@ -0,0 +1,251 @@
+diff -Nur linux-2.6.21.1/Documentation/arm/IXP4xx linux-2.6.21.1-owrt/Documentation/arm/IXP4xx
+--- linux-2.6.21.1/Documentation/arm/IXP4xx	2007-06-10 13:54:49.000000000 +0200
++++ linux-2.6.21.1-owrt/Documentation/arm/IXP4xx	2007-06-10 13:46:37.000000000 +0200
+@@ -111,6 +111,9 @@
+    the platform has two mini-PCI slots used for 802.11[bga] cards.
+    Finally, there is an IDE port hanging off the expansion bus.
+ 
++ADI Engineering Pronghorn Metro Platform
++http://www.adiengineering.com/php-bin/ecomm4/productDisplay.php?category_id=30&product_id=85
++
+ Gateworks Avila Network Platform
+ http://www.gateworks.com/avila_sbc.htm
+ 
+diff -Nur linux-2.6.21.1/arch/arm/mach-ixp4xx/Kconfig linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.21.1/arch/arm/mach-ixp4xx/Kconfig	2007-06-10 13:54:47.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/Kconfig	2007-06-10 13:46:37.000000000 +0200
+@@ -57,6 +57,14 @@
+ 	  WG302 v2 or WAG302 v2 Access Points. For more information
+ 	  on this platform, see http://openwrt.org
+ 
++config MACH_PRONGHORNMETRO
++	bool "Pronghorn Metro"
++	select PCI
++	help
++	  Say 'Y' here if you want your kernel to support the ADI 
++	  Engineering Pronghorn Metro Platform. For more
++	  information on this platform, see <file:Documentation/arm/IXP4xx>.
++
+ config ARCH_IXDP425
+ 	bool "IXDP425"
+ 	help
+diff -Nur linux-2.6.21.1/arch/arm/mach-ixp4xx/Makefile linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.21.1/arch/arm/mach-ixp4xx/Makefile	2007-06-10 13:54:47.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/Makefile	2007-06-10 13:46:37.000000000 +0200
+@@ -14,6 +14,7 @@
+ obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
+ obj-pci-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2)		+= wg302v2-pci.o
++obj-pci-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-pci.o
+ 
+ obj-y	+= common.o
+ 
+@@ -26,5 +27,6 @@
+ obj-$(CONFIG_MACH_NAS100D)	+= nas100d-setup.o nas100d-power.o
+ obj-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-setup.o
+ obj-$(CONFIG_MACH_WG302V2)	+= wg302v2-setup.o
++obj-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-setup.o
+ 
+ obj-$(CONFIG_PCI)		+= $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff -Nur linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-pci.c linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-pci.c
+--- linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-pci.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-pci.c	2007-06-10 13:50:08.000000000 +0200
+@@ -0,0 +1,74 @@
++/*
++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c
++ *
++ * PCI setup routines for ADI Engineering Pronghorn Metro
++ *
++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ *	Copyright (C) 2002 Jungo Software Technologies.
++ *	Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init pronghornmetro_pci_preinit(void)
++{
++	set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_LOW);
++	set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
++	set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++	set_irq_type(IRQ_IXP4XX_GPIO1, IRQT_LOW);
++
++	ixp4xx_pci_preinit();
++}
++
++static int __init pronghornmetro_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	if (slot == 13)
++		return IRQ_IXP4XX_GPIO4;
++	else if (slot == 14)
++		return IRQ_IXP4XX_GPIO6;
++	else if (slot == 15)
++		return IRQ_IXP4XX_GPIO11;
++	else if (slot == 16)
++		return IRQ_IXP4XX_GPIO1;
++	else return -1;
++}
++
++struct hw_pci pronghornmetro_pci __initdata = {
++	.nr_controllers = 1,
++	.preinit =        pronghornmetro_pci_preinit,
++	.swizzle =        pci_std_swizzle,
++	.setup =          ixp4xx_setup,
++	.scan =           ixp4xx_scan_bus,
++	.map_irq =        pronghornmetro_map_irq,
++};
++
++int __init pronghornmetro_pci_init(void)
++{
++	if (machine_is_pronghorn_metro())
++		pci_common_init(&pronghornmetro_pci);
++	return 0;
++}
++
++subsys_initcall(pronghornmetro_pci_init);
+diff -Nur linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c
+--- linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	2007-06-10 13:51:51.000000000 +0200
+@@ -0,0 +1,108 @@
++/*
++ * arch/arm/mach-ixp4xx/pronghornmetro-setup.c
++ *
++ * Board setup for the ADI Engineering Pronghorn Metro
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ *      Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data pronghornmetro_flash_data = {
++	.map_name	= "cfi_probe",
++	.width		= 2,
++};
++
++static struct resource pronghornmetro_flash_resource = {
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct platform_device pronghornmetro_flash = {
++	.name		= "IXP4XX-Flash",
++	.id		= 0,
++	.dev		= {
++		.platform_data = &pronghornmetro_flash_data,
++	},
++	.num_resources	= 1,
++	.resource	= &pronghornmetro_flash_resource,
++};
++
++static struct resource pronghornmetro_uart_resource = {
++	.start	= IXP4XX_UART2_BASE_PHYS,
++	.end	= IXP4XX_UART2_BASE_PHYS + 0x0fff,
++	.flags	= IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port pronghornmetro_uart_data[] = {
++	{
++		.mapbase	= IXP4XX_UART2_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART2,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{ },
++};
++
++static struct platform_device pronghornmetro_uart = {
++	.name		= "serial8250",
++	.id		= PLAT8250_DEV_PLATFORM,
++	.dev			= {
++		.platform_data	= pronghornmetro_uart_data,
++	},
++	.num_resources	= 1,
++	.resource	= &pronghornmetro_uart_resource,
++};
++
++static struct platform_device *pronghornmetro_devices[] __initdata = {
++	&pronghornmetro_flash,
++	&pronghornmetro_uart,
++};
++
++static void __init pronghornmetro_init(void)
++{
++	ixp4xx_sys_init();
++
++	pronghornmetro_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++	pronghornmetro_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1;
++
++	*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++	platform_add_devices(pronghornmetro_devices, ARRAY_SIZE(pronghornmetro_devices));
++}
++
++#ifdef CONFIG_MACH_PRONGHORNMETRO
++MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro")
++	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
++	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++	.map_io		= ixp4xx_map_io,
++	.init_irq	= ixp4xx_init_irq,
++	.timer		= &ixp4xx_timer,
++	.boot_params	= 0x0100,
++	.init_machine	= pronghornmetro_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.21.1/include/asm-arm/arch-ixp4xx/uncompress.h linux-2.6.21.1-owrt/include/asm-arm/arch-ixp4xx/uncompress.h
+--- linux-2.6.21.1/include/asm-arm/arch-ixp4xx/uncompress.h	2007-06-10 13:54:52.000000000 +0200
++++ linux-2.6.21.1-owrt/include/asm-arm/arch-ixp4xx/uncompress.h	2007-06-10 13:49:37.000000000 +0200
+@@ -40,7 +40,7 @@
+ 	/*
+ 	 * Some boards are using UART2 as console
+ 	 */
+-	if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2())
++	if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2() || machine_is_pronghorn_metro())
+ 		uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ 	else
+ 		uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/target/linux/ixp4xx/patches/410-pronghorn_metro_setup_mac.patch b/target/linux/ixp4xx/patches/410-pronghorn_metro_setup_mac.patch
new file mode 100644
index 0000000000..54621d6c3e
--- /dev/null
+++ b/target/linux/ixp4xx/patches/410-pronghorn_metro_setup_mac.patch
@@ -0,0 +1,61 @@
+diff -Nur linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c
+--- linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	2007-06-10 14:05:47.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	2007-06-10 14:05:38.000000000 +0200
+@@ -76,9 +76,57 @@
+ 	.resource	= &pronghornmetro_uart_resource,
+ };
+ 
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct resource res_mac1 = {
++	.start		= IXP4XX_EthC_BASE_PHYS,
++	.end		= IXP4XX_EthC_BASE_PHYS + 0x1ff,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= 0,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct mac_plat_info plat_mac1 = {
++	.npe_id		= 2,
++	.phy_id		= 1,
++	.eth_id		= 1,
++	.rxq_id		= 28,
++	.txq_id		= 25,
++	.rxdoneq_id	= 5,
++};
++
++static struct platform_device mac0 = {
++	.name		= "ixp4xx_mac",
++	.id		= 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources	= 1,
++	.resource	= &res_mac0,
++};
++
++static struct platform_device mac1 = {
++	.name		= "ixp4xx_mac",
++	.id		= 1,
++	.dev.platform_data = &plat_mac1,
++	.num_resources	= 1,
++	.resource	= &res_mac1,
++};
++
+ static struct platform_device *pronghornmetro_devices[] __initdata = {
+ 	&pronghornmetro_flash,
+ 	&pronghornmetro_uart,
++	&mac0,
++	&mac1,
+ };
+ 
+ static void __init pronghornmetro_init(void)
diff --git a/target/linux/ixp4xx/patches/420-pronghorn_metro_mtd_microcode.patch b/target/linux/ixp4xx/patches/420-pronghorn_metro_mtd_microcode.patch
new file mode 100644
index 0000000000..0c304c78ff
--- /dev/null
+++ b/target/linux/ixp4xx/patches/420-pronghorn_metro_mtd_microcode.patch
@@ -0,0 +1,55 @@
+diff -Nur linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c
+--- linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	2007-06-10 14:10:24.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	2007-06-10 14:10:15.000000000 +0200
+@@ -17,6 +17,7 @@
+ #include <linux/serial.h>
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
++#include <linux/mtd/mtd.h>
+ #include <linux/slab.h>
+ 
+ #include <asm/types.h>
+@@ -122,11 +123,34 @@
+ 	.resource	= &res_mac1,
+ };
+ 
++struct npe_ucode_platform_data pronghornmetro_npe_ucode_data = {
++	.mtd_partition	= "RedBoot",
++};
++
++static struct platform_device pronghornmetro_npe_ucode = {
++	.name			= "ixp4xx_npe_ucode",
++	.id			= 0,
++	.dev.platform_data	= &pronghornmetro_npe_ucode_data,
++};
++
+ static struct platform_device *pronghornmetro_devices[] __initdata = {
+ 	&pronghornmetro_flash,
+ 	&pronghornmetro_uart,
+ 	&mac0,
+ 	&mac1,
++	&pronghornmetro_npe_ucode,
++};
++
++static void pronghornmetro_flash_add(struct mtd_info *mtd)
++{
++}
++
++static void pronghornmetro_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier pronghornmetro_flash_notifier = {
++	.add = pronghornmetro_flash_add,
++	.remove = pronghornmetro_flash_remove,
+ };
+ 
+ static void __init pronghornmetro_init(void)
+@@ -140,6 +164,8 @@
+ 	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+ 
+ 	platform_add_devices(pronghornmetro_devices, ARRAY_SIZE(pronghornmetro_devices));
++
++	register_mtd_user(&pronghornmetro_flash_notifier);
+ }
+ 
+ #ifdef CONFIG_MACH_PRONGHORNMETRO
diff --git a/target/linux/ixp4xx/patches/430-pronghorn_metro_cf.patch b/target/linux/ixp4xx/patches/430-pronghorn_metro_cf.patch
new file mode 100644
index 0000000000..d2982bc954
--- /dev/null
+++ b/target/linux/ixp4xx/patches/430-pronghorn_metro_cf.patch
@@ -0,0 +1,57 @@
+diff -Nur linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c
+--- linux-2.6.21.1/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	2007-06-10 14:31:27.000000000 +0200
++++ linux-2.6.21.1-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c	2007-06-10 14:36:23.000000000 +0200
+@@ -77,6 +77,35 @@
+ 	.resource	= &pronghornmetro_uart_resource,
+ };
+ 
++static struct resource pronghornmetro_pata_resources[] = {
++	{
++		.flags	= IORESOURCE_MEM
++	},
++	{
++		.flags	= IORESOURCE_MEM,
++	},
++	{
++		.name	= "intrq",
++		.start	= IRQ_IXP4XX_GPIO0,
++		.end	= IRQ_IXP4XX_GPIO0,
++		.flags	= IORESOURCE_IRQ,
++	},
++};
++
++static struct ixp4xx_pata_data pronghornmetro_pata_data = {
++	.cs0_bits	= 0xbfff0043,
++	.cs1_bits	= 0xbfff0043,
++};
++
++static struct platform_device pronghornmetro_pata = {
++	.name			= "pata_ixp4xx_cf",
++	.id			= 0,
++	.dev.platform_data      = &pronghornmetro_pata_data,
++	.num_resources		= ARRAY_SIZE(pronghornmetro_pata_resources),
++	.resource		= pronghornmetro_pata_resources,
++};
++
++
+ static struct resource res_mac0 = {
+ 	.start		= IXP4XX_EthB_BASE_PHYS,
+ 	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
+@@ -165,6 +194,17 @@
+ 
+ 	platform_add_devices(pronghornmetro_devices, ARRAY_SIZE(pronghornmetro_devices));
+ 
++	pronghornmetro_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1);
++	pronghornmetro_pata_resources[0].end = IXP4XX_EXP_BUS_END(1);
++
++	pronghornmetro_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
++	pronghornmetro_pata_resources[1].end = IXP4XX_EXP_BUS_END(2);
++
++	pronghornmetro_pata_data.cs0_cfg = IXP4XX_EXP_CS1;
++	pronghornmetro_pata_data.cs1_cfg = IXP4XX_EXP_CS2;
++
++	platform_device_register(&pronghornmetro_pata);
++
+ 	register_mtd_user(&pronghornmetro_flash_notifier);
+ }
+ 
diff --git a/target/linux/ixp4xx/patches/500-compex.patch b/target/linux/ixp4xx/patches/500-compex.patch
new file mode 100644
index 0000000000..854194b35f
--- /dev/null
+++ b/target/linux/ixp4xx/patches/500-compex.patch
@@ -0,0 +1,184 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/compex-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/compex-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/compex-setup.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/compex-setup.c	2007-04-10 01:56:21.000000000 +0200
+@@ -0,0 +1,120 @@
++/*
++ * arch/arm/mach-ixp4xx/compex-setup.c
++ *
++ * Ccompex WP18 / NP18A board-setup
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on ixdp425-setup.c:
++ *	Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data compex_flash_data = {
++	.map_name	= "cfi_probe",
++	.width		= 2,
++};
++
++static struct resource compex_flash_resource = {
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct platform_device compex_flash = {
++	.name		= "IXP4XX-Flash",
++	.id		= 0,
++	.dev		= {
++		.platform_data = &compex_flash_data,
++	},
++	.num_resources	= 1,
++	.resource	= &compex_flash_resource,
++};
++
++static struct resource compex_uart_resources[] = {
++	{
++		.start		= IXP4XX_UART1_BASE_PHYS,
++		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
++		.flags		= IORESOURCE_MEM
++	},
++	{
++		.start		= IXP4XX_UART2_BASE_PHYS,
++		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
++		.flags		= IORESOURCE_MEM
++	}
++};
++
++static struct plat_serial8250_port compex_uart_data[] = {
++	{
++		.mapbase	= IXP4XX_UART1_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART1,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{
++		.mapbase	= IXP4XX_UART2_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART2,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{ },
++};
++
++static struct platform_device compex_uart = {
++	.name			= "serial8250",
++	.id			= PLAT8250_DEV_PLATFORM,
++	.dev.platform_data	= compex_uart_data,
++	.num_resources		= 2,
++	.resource		= compex_uart_resources
++};
++
++static struct platform_device *compex_devices[] __initdata = {
++	&compex_flash,
++	&compex_uart
++};
++
++static void __init compex_init(void)
++{
++	ixp4xx_sys_init();
++
++	compex_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++	compex_flash_resource.end =
++		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
++
++	platform_add_devices(compex_devices, ARRAY_SIZE(compex_devices));
++}
++
++#ifdef CONFIG_MACH_COMPEX
++MACHINE_START(COMPEX, "Compex WP18 / NP18A")
++	/* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
++	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
++	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++	.map_io		= ixp4xx_map_io,
++	.init_irq	= ixp4xx_init_irq,
++	.timer		= &ixp4xx_timer,
++	.boot_params	= 0x0100,
++	.init_machine	= compex_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/ixdp425-pci.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/ixdp425-pci.c	2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c	2007-04-10 00:22:16.000000000 +0200
+@@ -66,7 +66,7 @@
+ int __init ixdp425_pci_init(void)
+ {
+ 	if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
+-			machine_is_ixdp465())
++			machine_is_ixdp465() || machine_is_compex())
+ 		pci_common_init(&ixdp425_pci);
+ 	return 0;
+ }
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig	2007-04-10 00:33:31.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig	2007-04-10 00:48:37.000000000 +0200
+@@ -57,6 +57,14 @@
+ 	  Engineering Pronghorn Metro Platform. For more
+ 	  information on this platform, see <file:Documentation/arm/IXP4xx>.
+ 
++config MACH_COMPEX
++	bool "Compex WP18 / NP18A"
++	select PCI
++	help
++	  Say 'Y' here if you want your kernel to support Compex' 
++	  WP18 or NP18A boards. For more information on this
++	  platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ 	bool "IXDP425"
+ 	help
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile	2007-04-10 00:33:39.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile	2007-04-09 20:23:06.000000000 +0200
+@@ -14,6 +14,7 @@
+ obj-pci-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2)		+= wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-pci.o
++obj-pci-$(CONFIG_MACH_COMPEX)		+= ixdp425-pci.o
+ 
+ obj-y	+= common.o
+ 
+@@ -26,5 +27,6 @@
+ obj-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-setup.o
+ obj-$(CONFIG_MACH_WG302V2)	+= wg302v2-setup.o
+ obj-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-setup.o
++obj-$(CONFIG_MACH_COMPEX)	+= compex-setup.o
+ 
+ obj-$(CONFIG_PCI)		+= $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff -Nur linux-2.6.19.2/arch/arm/tools/mach-types linux-2.6.19.2-owrt/arch/arm/tools/mach-types
+--- linux-2.6.19.2/arch/arm/tools/mach-types	2007-04-10 01:27:55.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/tools/mach-types	2007-04-09 20:22:33.000000000 +0200
+@@ -1278,7 +1278,7 @@
+ smdk6400		MACH_SMDK6400		SMDK6400		1270
+ nokia_n800		MACH_NOKIA_N800		NOKIA_N800		1271
+ greenphone		MACH_GREENPHONE		GREENPHONE		1272
+-compex42x		MACH_COMPEXWP18		COMPEXWP18		1273
++compex			MACH_COMPEX		COMPEX			1273
+ xmate			MACH_XMATE		XMATE			1274
+ energizer		MACH_ENERGIZER		ENERGIZER		1275
+ ime1			MACH_IME1		IME1			1276
diff --git a/target/linux/ixp4xx/patches/510-compex_setup_mac.patch b/target/linux/ixp4xx/patches/510-compex_setup_mac.patch
new file mode 100644
index 0000000000..ed85df0818
--- /dev/null
+++ b/target/linux/ixp4xx/patches/510-compex_setup_mac.patch
@@ -0,0 +1,62 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/compex-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/compex-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/compex-setup.c	2007-04-09 20:30:37.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/compex-setup.c	2007-04-09 20:36:23.000000000 +0200
+@@ -90,9 +90,57 @@
+ 	.resource		= compex_uart_resources
+ };
+ 
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct resource res_mac1 = {
++	.start		= IXP4XX_EthC_BASE_PHYS,
++	.end		= IXP4XX_EthC_BASE_PHYS + 0x1ff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= -1,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct mac_plat_info plat_mac1 = {
++	.npe_id		= 2,
++	.phy_id		= 3,
++	.eth_id		= 1,
++	.rxq_id		= 28,
++	.txq_id		= 25,
++	.rxdoneq_id	= 5,
++};
++
++static struct platform_device mac0 = {
++	.name           = "ixp4xx_mac",
++	.id             = 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources  = 1,
++	.resource       = &res_mac0,
++};
++
++static struct platform_device mac1 = {
++	.name           = "ixp4xx_mac",
++	.id             = 1,
++	.dev.platform_data = &plat_mac1,
++	.num_resources  = 1,
++	.resource       = &res_mac1,
++};
++
+ static struct platform_device *compex_devices[] __initdata = {
+ 	&compex_flash,
+-	&compex_uart
++	&compex_uart,
++	&mac0,
++	&mac1,
+ };
+ 
+ static void __init compex_init(void)
diff --git a/target/linux/ixp4xx/patches/520-compex_mtd_microcode.patch b/target/linux/ixp4xx/patches/520-compex_mtd_microcode.patch
new file mode 100644
index 0000000000..90842239c0
--- /dev/null
+++ b/target/linux/ixp4xx/patches/520-compex_mtd_microcode.patch
@@ -0,0 +1,55 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/compex-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/compex-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/compex-setup.c	2007-04-09 20:51:57.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/compex-setup.c	2007-04-09 21:48:22.000000000 +0200
+@@ -17,6 +17,7 @@
+ #include <linux/serial.h>
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
++#include <linux/mtd/mtd.h>
+ #include <linux/slab.h>
+ 
+ #include <asm/types.h>
+@@ -136,11 +137,34 @@
+ 	.resource       = &res_mac1,
+ };
+ 
++struct npe_ucode_platform_data compex_npe_ucode_data = {
++	.mtd_partition	= "RedBoot",
++};
++
++static struct platform_device compex_npe_ucode = {
++	.name			= "ixp4xx_npe_ucode",
++	.id			= 0,
++	.dev.platform_data	= &compex_npe_ucode_data,
++};
++
+ static struct platform_device *compex_devices[] __initdata = {
+ 	&compex_flash,
+ 	&compex_uart,
+ 	&mac0,
+ 	&mac1,
++	&compex_npe_ucode,
++};
++
++static void compex_flash_add(struct mtd_info *mtd)
++{
++}
++
++static void compex_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier compex_flash_notifier = {
++	.add = compex_flash_add,
++	.remove = compex_flash_remove,
+ };
+ 
+ static void __init compex_init(void)
+@@ -152,6 +176,8 @@
+ 		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+ 
+ 	platform_add_devices(compex_devices, ARRAY_SIZE(compex_devices));
++
++	register_mtd_user(&compex_flash_notifier);
+ }
+ 
+ #ifdef CONFIG_ARCH_COMPEX
diff --git a/target/linux/ixp4xx/patches/600-wrt300nv2.patch b/target/linux/ixp4xx/patches/600-wrt300nv2.patch
new file mode 100644
index 0000000000..9697e5d5f2
--- /dev/null
+++ b/target/linux/ixp4xx/patches/600-wrt300nv2.patch
@@ -0,0 +1,229 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Kconfig	2007-05-03 23:17:47.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Kconfig	2007-04-24 14:25:02.000000000 +0200
+@@ -65,6 +65,14 @@
+ 	  WP18 or NP18A boards. For more information on this
+ 	  platform, see http://openwrt.org
+ 
++config MACH_WRT300NV2
++	bool "Linksys WRT300N v2"
++	select PCI
++	help
++	  Say 'Y' here if you want your kernel to support Linksys' 
++	  WRT300N v2 router. For more information on this
++	  platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ 	bool "IXDP425"
+ 	help
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/Makefile	2007-05-03 23:17:47.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/Makefile	2007-04-24 14:25:02.000000000 +0200
+@@ -15,6 +15,7 @@
+ obj-pci-$(CONFIG_MACH_WG302V2)		+= wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-pci.o
+ obj-pci-$(CONFIG_MACH_COMPEX)		+= ixdp425-pci.o
++obj-pci-$(CONFIG_MACH_WRT300NV2)		+= wrt300nv2-pci.o
+ 
+ obj-y	+= common.o
+ 
+@@ -28,5 +29,6 @@
+ obj-$(CONFIG_MACH_WG302V2)	+= wg302v2-setup.o
+ obj-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-setup.o
+ obj-$(CONFIG_MACH_COMPEX)	+= compex-setup.o
++obj-$(CONFIG_MACH_WRT300NV2)	+= wrt300nv2-setup.o
+ 
+ obj-$(CONFIG_PCI)		+= $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/wrt300nv2-pci.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wrt300nv2-pci.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/wrt300nv2-pci.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wrt300nv2-pci.c	2007-05-10 10:40:54.000000000 +0200
+@@ -0,0 +1,65 @@
++/*
++ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c
++ *
++ * PCI setup routines for Linksys WRT300N v2
++ *
++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ *	Copyright (C) 2002 Jungo Software Technologies.
++ *	Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init wrt300nv2_pci_preinit(void)
++{
++	set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
++
++	ixp4xx_pci_preinit();
++}
++
++static int __init wrt300nv2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	if (slot == 1)
++		return IRQ_IXP4XX_GPIO8;
++	else return -1;
++}
++
++struct hw_pci wrt300nv2_pci __initdata = {
++	.nr_controllers = 1,
++	.preinit =        wrt300nv2_pci_preinit,
++	.swizzle =        pci_std_swizzle,
++	.setup =          ixp4xx_setup,
++	.scan =           ixp4xx_scan_bus,
++	.map_irq =        wrt300nv2_map_irq,
++};
++
++int __init wrt300nv2_pci_init(void)
++{
++	if (machine_is_wrt300nv2())
++		pci_common_init(&wrt300nv2_pci);
++	return 0;
++}
++
++subsys_initcall(wrt300nv2_pci_init);
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/wrt300nv2-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/wrt300nv2-setup.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c	2007-05-03 23:16:53.000000000 +0200
+@@ -0,0 +1,108 @@
++/*
++ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c
++ *
++ * Board setup for the Linksys WRT300N v2
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ *      Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data wrt300nv2_flash_data = {
++	.map_name	= "cfi_probe",
++	.width		= 2,
++};
++
++static struct resource wrt300nv2_flash_resource = {
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct platform_device wrt300nv2_flash = {
++	.name		= "IXP4XX-Flash",
++	.id		= 0,
++	.dev		= {
++		.platform_data = &wrt300nv2_flash_data,
++	},
++	.num_resources	= 1,
++	.resource	= &wrt300nv2_flash_resource,
++};
++
++static struct resource wrt300nv2_uart_resource = {
++	.start	= IXP4XX_UART2_BASE_PHYS,
++	.end	= IXP4XX_UART2_BASE_PHYS + 0x0fff,
++	.flags	= IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port wrt300nv2_uart_data[] = {
++	{
++		.mapbase	= IXP4XX_UART2_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART2,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{ },
++};
++
++static struct platform_device wrt300nv2_uart = {
++	.name		= "serial8250",
++	.id		= PLAT8250_DEV_PLATFORM,
++	.dev			= {
++		.platform_data	= wrt300nv2_uart_data,
++	},
++	.num_resources	= 1,
++	.resource	= &wrt300nv2_uart_resource,
++};
++
++static struct platform_device *wrt300nv2_devices[] __initdata = {
++	&wrt300nv2_flash,
++	&wrt300nv2_uart
++};
++
++static void __init wrt300nv2_init(void)
++{
++	ixp4xx_sys_init();
++
++	wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++	wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++	*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++	platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices));
++}
++
++#ifdef CONFIG_MACH_WRT300NV2
++MACHINE_START(WRT300NV2, "Linksys WRT300N v2")
++	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
++	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++	.map_io		= ixp4xx_map_io,
++	.init_irq	= ixp4xx_init_irq,
++	.timer		= &ixp4xx_timer,
++	.boot_params	= 0x0100,
++	.init_machine	= wrt300nv2_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.19.2/include/asm-arm/arch-ixp4xx/uncompress.h linux-2.6.19.2-owrt/include/asm-arm/arch-ixp4xx/uncompress.h
+--- linux-2.6.19.2/include/asm-arm/arch-ixp4xx/uncompress.h	2007-05-03 23:17:48.000000000 +0200
++++ linux-2.6.19.2-owrt/include/asm-arm/arch-ixp4xx/uncompress.h	2007-04-24 14:25:02.000000000 +0200
+@@ -40,7 +40,7 @@
+ 	/*
+ 	 * Some boards are using UART2 as console
+ 	 */
+-	if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2() || machine_is_pronghorn_metro())
++	if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2() || machine_is_pronghorn_metro() || machine_is_wrt300nv2())
+ 		uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ 	else
+ 		uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/target/linux/ixp4xx/patches/610-wrt300nv2_setup_mac.patch b/target/linux/ixp4xx/patches/610-wrt300nv2_setup_mac.patch
new file mode 100644
index 0000000000..145ad76ef7
--- /dev/null
+++ b/target/linux/ixp4xx/patches/610-wrt300nv2_setup_mac.patch
@@ -0,0 +1,62 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/wrt300nv2-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/wrt300nv2-setup.c	2007-04-24 14:25:02.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c	2007-04-24 14:31:09.000000000 +0200
+@@ -76,9 +76,57 @@
+ 	.resource	= &wrt300nv2_uart_resource,
+ };
+ 
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct resource res_mac1 = {
++	.start		= IXP4XX_EthC_BASE_PHYS,
++	.end		= IXP4XX_EthC_BASE_PHYS + 0x1ff,
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= -1,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct mac_plat_info plat_mac1 = {
++	.npe_id		= 2,
++	.phy_id		= 1,
++	.eth_id		= 1,
++	.rxq_id		= 28,
++	.txq_id		= 25,
++	.rxdoneq_id	= 5,
++};
++
++static struct platform_device mac0 = {
++	.name		= "ixp4xx_mac",
++	.id		= 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources	= 1,
++	.resource	= &res_mac0,
++};
++
++static struct platform_device mac1 = {
++	.name		= "ixp4xx_mac",
++	.id		= 1,
++	.dev.platform_data = &plat_mac1,
++	.num_resources	= 1,
++	.resource	= &res_mac1,
++};
++
+ static struct platform_device *wrt300nv2_devices[] __initdata = {
+ 	&wrt300nv2_flash,
+-	&wrt300nv2_uart
++	&wrt300nv2_uart,
++	&mac0,
++	&mac1,
+ };
+ 
+ static void __init wrt300nv2_init(void)
diff --git a/target/linux/ixp4xx/patches/720-avila_setup_mac.patch b/target/linux/ixp4xx/patches/720-avila_setup_mac.patch
new file mode 100644
index 0000000000..3784852e31
--- /dev/null
+++ b/target/linux/ixp4xx/patches/720-avila_setup_mac.patch
@@ -0,0 +1,70 @@
+---
+ arch/arm/mach-ixp4xx/avila-setup.c |   50 ++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 49 insertions(+), 1 deletion(-)
+
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/avila-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/avila-setup.c
++++ linux-2.6.19/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -104,10 +104,60 @@ static struct platform_device avila_uart
+ 	.resource		= avila_uart_resources
+ };
+ 
++/* MACs */
++static struct resource res_mac0 = {
++	.start		= IXP4XX_EthB_BASE_PHYS,
++	.end		= IXP4XX_EthB_BASE_PHYS + 0x1ff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct resource res_mac1 = {
++	.start		= IXP4XX_EthC_BASE_PHYS,
++	.end		= IXP4XX_EthC_BASE_PHYS + 0x1ff,
++	.flags          = IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++	.npe_id		= 1,
++	.phy_id		= 0,
++	.eth_id		= 0,
++	.rxq_id		= 27,
++	.txq_id		= 24,
++	.rxdoneq_id	= 4,
++};
++
++static struct mac_plat_info plat_mac1 = {
++	.npe_id		= 2,
++	.phy_id		= 1,
++	.eth_id		= 1,
++	.rxq_id		= 28,
++	.txq_id		= 25,
++	.rxdoneq_id	= 5,
++};
++
++static struct platform_device mac0 = {
++	.name           = "ixp4xx_mac",
++	.id             = 0,
++	.dev.platform_data = &plat_mac0,
++	.num_resources  = 1,
++	.resource       = &res_mac0,
++};
++
++static struct platform_device mac1 = {
++	.name           = "ixp4xx_mac",
++	.id             = 1,
++	.dev.platform_data = &plat_mac1,
++	.num_resources  = 1,
++	.resource       = &res_mac1,
++};
++
+ static struct platform_device *avila_devices[] __initdata = {
+ 	&avila_i2c_controller,
+ 	&avila_flash,
+-	&avila_uart
++	&avila_uart,
++	&mac0,
++	&mac1,
++
+ };
+ 
+ static void __init avila_init(void)
diff --git a/target/linux/ixp4xx/patches/740-avila_loft_mac_platform.patch b/target/linux/ixp4xx/patches/740-avila_loft_mac_platform.patch
new file mode 100644
index 0000000000..952a05506e
--- /dev/null
+++ b/target/linux/ixp4xx/patches/740-avila_loft_mac_platform.patch
@@ -0,0 +1,50 @@
+Index: linux-2.6.19/arch/arm/mach-ixp4xx/avila-setup.c
+===================================================================
+--- linux-2.6.19.orig/arch/arm/mach-ixp4xx/avila-setup.c	2007-01-23 03:12:36.000000000 -0800
++++ linux-2.6.19/arch/arm/mach-ixp4xx/avila-setup.c	2007-01-23 03:12:47.000000000 -0800
+@@ -18,6 +18,10 @@
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
+ #include <linux/slab.h>
++#ifdef CONFIG_SENSORS_EEPROM
++#include <linux/i2c.h>
++#include <linux/eeprom.h>
++#endif
+ 
+ #include <asm/types.h>
+ #include <asm/setup.h>
+@@ -198,9 +202,34 @@
+ 	&avila_npe_ucode,
+ };
+ 
++#ifdef CONFIG_SENSORS_EEPROM
++static int loft_eeprom_do(struct notifier_block *self, unsigned long event, void *t)
++{
++       struct eeprom_data *data = t;
++
++       char macs[12];
++
++       /* The MACs are the first 12 bytes in the eeprom at address 0x51 */
++       if (event == EEPROM_REGISTER && data->client.addr == 0x51) {
++               data->attr->read(&data->client.dev.kobj, macs, 0, 12);
++               memcpy(&plat_mac0.hwaddr, macs, 6);
++               memcpy(&plat_mac1.hwaddr, macs + 6, 6);
++       }
++
++       return NOTIFY_DONE;
++}
++
++static struct notifier_block loft_eeprom_notifier = {
++       .notifier_call = loft_eeprom_do
++};
++#endif
++
+ static void __init avila_init(void)
+ {
+ 	ixp4xx_sys_init();
++#ifdef CONFIG_SENSORS_EEPROM
++       register_eeprom_notifier(&loft_eeprom_notifier);
++#endif
+ 
+ 	avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ 	avila_flash_resource.end =
diff --git a/target/linux/ixp4xx/patches/750-avila_mtd_microcode.patch b/target/linux/ixp4xx/patches/750-avila_mtd_microcode.patch
new file mode 100644
index 0000000000..0ecd3a5617
--- /dev/null
+++ b/target/linux/ixp4xx/patches/750-avila_mtd_microcode.patch
@@ -0,0 +1,28 @@
+diff -Nur linux-2.6.19.2/arch/arm/mach-ixp4xx/avila-setup.c linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/avila-setup.c
+--- linux-2.6.19.2/arch/arm/mach-ixp4xx/avila-setup.c	2007-05-10 12:30:54.000000000 +0200
++++ linux-2.6.19.2-owrt/arch/arm/mach-ixp4xx/avila-setup.c	2007-05-10 12:33:08.000000000 +0200
+@@ -155,13 +155,23 @@
+ 	.resource       = &res_mac1,
+ };
+ 
++struct npe_ucode_platform_data avila_npe_ucode_data = {
++	 .mtd_partition  = "RedBoot",
++};
++
++static struct platform_device avila_npe_ucode = {
++       .name                   = "ixp4xx_npe_ucode",
++       .id                     = 0,
++       .dev.platform_data      = &avila_npe_ucode_data,
++};
++
+ static struct platform_device *avila_devices[] __initdata = {
+ 	&avila_i2c_controller,
+ 	&avila_flash,
+ 	&avila_uart,
+ 	&mac0,
+ 	&mac1,
+-
++	&avila_npe_ucode,
+ };
+ 
+ #ifdef CONFIG_SENSORS_EEPROM
diff --git a/target/linux/ixp4xx/patches/800-eeprom_new_notifier.patch b/target/linux/ixp4xx/patches/800-eeprom_new_notifier.patch
new file mode 100644
index 0000000000..79a097128c
--- /dev/null
+++ b/target/linux/ixp4xx/patches/800-eeprom_new_notifier.patch
@@ -0,0 +1,201 @@
+Add EEPROM notifiers
+
+These help board level code by allowing a callback when EEPROMs are
+loaded, this permits system level configuration to be loaded from the
+EEPROM.  This is particularly useful when the ethernet MAC ids are
+stored in EEPROM and when the ethernet hardware is generic (so it
+has no board level knowledge), then the MACs can be loaded into
+the 'maclist' code and read out by the ethernet config.
+
+Signed-off-by: John Bowler <jbowler@acm.org>
+
+Index: linux-2.6.21-rc1-arm/drivers/i2c/chips/eeprom.c
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/drivers/i2c/chips/eeprom.c	2007-02-21 02:24:14.000000000 -0800
++++ linux-2.6.21-rc1-arm/drivers/i2c/chips/eeprom.c	2007-02-21 02:25:01.000000000 -0800
+@@ -33,6 +33,8 @@
+ #include <linux/jiffies.h>
+ #include <linux/i2c.h>
+ #include <linux/mutex.h>
++#include <linux/notifier.h>
++#include <linux/eeprom.h>
+ 
+ /* Addresses to scan */
+ static unsigned short normal_i2c[] = { 0x50, 0x51, 0x52, 0x53, 0x54,
+@@ -41,26 +43,7 @@
+ /* Insmod parameters */
+ I2C_CLIENT_INSMOD_1(eeprom);
+ 
+-
+-/* Size of EEPROM in bytes */
+-#define EEPROM_SIZE		256
+-
+-/* possible types of eeprom devices */
+-enum eeprom_nature {
+-	UNKNOWN,
+-	VAIO,
+-};
+-
+-/* Each client has this additional data */
+-struct eeprom_data {
+-	struct i2c_client client;
+-	struct mutex update_lock;
+-	u8 valid;			/* bitfield, bit!=0 if slice is valid */
+-	unsigned long last_updated[8];	/* In jiffies, 8 slices */
+-	u8 data[EEPROM_SIZE];		/* Register values */
+-	enum eeprom_nature nature;
+-};
+-
++ATOMIC_NOTIFIER_HEAD(eeprom_chain);
+ 
+ static int eeprom_attach_adapter(struct i2c_adapter *adapter);
+ static int eeprom_detect(struct i2c_adapter *adapter, int address, int kind);
+@@ -189,6 +172,7 @@
+ 	data->valid = 0;
+ 	mutex_init(&data->update_lock);
+ 	data->nature = UNKNOWN;
++	data->attr = &eeprom_attr;
+ 
+ 	/* Tell the I2C layer a new client has arrived */
+ 	if ((err = i2c_attach_client(new_client)))
+@@ -212,6 +196,9 @@
+ 	if (err)
+ 		goto exit_detach;
+ 
++	/* call the notifier chain */
++	atomic_notifier_call_chain(&eeprom_chain, EEPROM_REGISTER, data);
++
+ 	return 0;
+ 
+ exit_detach:
+@@ -237,6 +224,41 @@
+ 	return 0;
+ }
+ 
++/**
++ * register_eeprom_notifier - register a 'user' of EEPROM devices.
++ * @nb: pointer to notifier info structure
++ *
++ * Registers a callback function to be called upon detection
++ * of an EEPROM device.  Detection invokes the 'add' callback
++ * with the kobj of the mutex and a bin_attribute which allows
++ * read from the EEPROM.  The intention is that the notifier
++ * will be able to read system configuration from the notifier.
++ *
++ * Only EEPROMs detected *after* the addition of the notifier
++ * are notified.  I.e. EEPROMs already known to the system
++ * will not be notified - add the notifier from board level
++ * code!
++ */
++int register_eeprom_notifier(struct notifier_block *nb)
++{
++	return atomic_notifier_chain_register(&eeprom_chain, nb);
++}
++
++/**
++ *	unregister_eeprom_notifier - unregister a 'user' of EEPROM devices.
++ *	@old: pointer to notifier info structure
++ *
++ *	Removes a callback function from the list of 'users' to be
++ *	notified upon detection of EEPROM devices.
++ */
++int unregister_eeprom_notifier(struct notifier_block *nb)
++{
++	return atomic_notifier_chain_unregister(&eeprom_chain, nb);
++}
++
++EXPORT_SYMBOL_GPL(register_eeprom_notifier);
++EXPORT_SYMBOL_GPL(unregister_eeprom_notifier);
++
+ static int __init eeprom_init(void)
+ {
+ 	return i2c_add_driver(&eeprom_driver);
+Index: linux-2.6.21-rc1-arm/include/linux/eeprom.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.21-rc1-arm/include/linux/eeprom.h	2007-02-21 02:25:01.000000000 -0800
+@@ -0,0 +1,71 @@
++#ifndef _LINUX_EEPROM_H
++#define _LINUX_EEPROM_H
++/*
++ * $Id: 45-eeprom-new-notifier.patch,v 1.2 2006/03/27 11:10:19 azummo Exp $
++ *
++ *  Copyright (C) 2006 John Bowler
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __KERNEL__
++#error This is a kernel header
++#endif
++
++#include <linux/list.h>
++#include <linux/kobject.h>
++#include <linux/sysfs.h>
++
++/* Size of EEPROM in bytes */
++#define EEPROM_SIZE             256
++
++/* possible types of eeprom devices */
++enum eeprom_nature {
++	UNKNOWN,
++	VAIO,
++};
++
++/* Each client has this additional data */
++struct eeprom_data {
++	struct i2c_client client;
++	struct mutex update_lock;
++	u8 valid;			/* bitfield, bit!=0 if slice is valid */
++	unsigned long last_updated[8];	/* In jiffies, 8 slices */
++	u8 data[EEPROM_SIZE];		/* Register values */
++	enum eeprom_nature nature;
++	struct bin_attribute *attr;
++};
++
++/*
++ * This is very basic.
++ *
++ * If an EEPROM is detected on the I2C bus (this only works for
++ * I2C EEPROMs) the notifier chain  is called with
++ * both the I2C information and the kobject for the sysfs
++ * device which has been registers.  It is then possible to
++ * read from the device via the bin_attribute::read method
++ * to extract configuration information.
++ *
++ * Register the notifier in the board level code, there is no
++ * need to unregister it but you can if you want (it will save
++ * a little bit or kernel memory to do so).
++ */
++
++extern int register_eeprom_notifier(struct notifier_block *nb);
++extern int unregister_eeprom_notifier(struct notifier_block *nb);
++
++#endif /* _LINUX_EEPROM_H */
+Index: linux-2.6.21-rc1-arm/include/linux/notifier.h
+===================================================================
+--- linux-2.6.21-rc1-arm.orig/include/linux/notifier.h	2007-02-21 02:24:14.000000000 -0800
++++ linux-2.6.21-rc1-arm/include/linux/notifier.h	2007-02-21 02:25:01.000000000 -0800
+@@ -187,5 +187,8 @@
+ #define CPU_DOWN_FAILED		0x0006 /* CPU (unsigned)v NOT going down */
+ #define CPU_DEAD		0x0007 /* CPU (unsigned)v dead */
+ 
++/* eeprom notifier chain */
++#define EEPROM_REGISTER		0x0001
++
+ #endif /* __KERNEL__ */
+ #endif /* _LINUX_NOTIFIER_H */
diff --git a/target/linux/ixp4xx/patches/900-no_loader_workaround.patch b/target/linux/ixp4xx/patches/900-no_loader_workaround.patch
new file mode 100644
index 0000000000..f84f15b09e
--- /dev/null
+++ b/target/linux/ixp4xx/patches/900-no_loader_workaround.patch
@@ -0,0 +1,19 @@
+diff -Nur linux-2.6.19/arch/arm/boot/compressed/head-xscale.S linux-2.6.19-owrt/arch/arm/boot/compressed/head-xscale.S
+--- linux-2.6.19/arch/arm/boot/compressed/head-xscale.S	2006-12-19 12:56:21.000000000 +0100
++++ linux-2.6.19-owrt/arch/arm/boot/compressed/head-xscale.S	2006-12-19 12:58:15.000000000 +0100
+@@ -41,6 +41,7 @@
+ 		mov	r7, #MACH_TYPE_COTULLA_IDP
+ #endif
+ 
++/* let the arm-magic.sh script do the dirty work
+ #ifdef  CONFIG_MACH_GTWX5715
+                mov     r7, #(MACH_TYPE_GTWX5715 & 0xff)
+                orr     r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00)
+@@ -50,6 +51,7 @@
+                mov     r7, #(MACH_TYPE_GATEWAY7001 & 0xff)
+                orr     r7, r7, #(MACH_TYPE_GATEWAY7001 & 0xff00)
+ #endif
++ */
+ 
+ #ifdef CONFIG_ARCH_IXP2000
+ 		mov	r1, #-1
diff --git a/target/linux/ixp4xx/patches/996-fsg3_support.patch b/target/linux/ixp4xx/patches/996-fsg3_support.patch
new file mode 100644
index 0000000000..ecf5d750a5
--- /dev/null
+++ b/target/linux/ixp4xx/patches/996-fsg3_support.patch
@@ -0,0 +1,429 @@
+Index: linux-2.6.21.5-armeb/arch/arm/mach-ixp4xx/fsg-pci.c
+===================================================================
+--- /dev/null
++++ linux-2.6.21.5-armeb/arch/arm/mach-ixp4xx/fsg-pci.c
+@@ -0,0 +1,71 @@
++/*
++ * arch/arch/mach-ixp4xx/fsg-pci.c
++ *
++ * FSG board-level PCI initialization
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Maintainer: http://www.nslu2-linux.org/
++ *
++ * based on ixdp425-pci.c:
++ *	Copyright (C) 2002 Intel Corporation.
++ *	Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach/pci.h>
++#include <asm/mach-types.h>
++
++void __init fsg_pci_preinit(void)
++{
++	set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
++	set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
++	set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
++
++	ixp4xx_pci_preinit();
++}
++
++static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
++		IRQ_FSG_PCI_INTC,
++		IRQ_FSG_PCI_INTB,
++		IRQ_FSG_PCI_INTA,
++	};
++
++	int irq = -1;
++	slot = slot - 11;
++
++	if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
++		pin >= 1 && pin <= FSG_PCI_IRQ_LINES) {
++			irq = pci_irq_table[(slot - 1)];
++	}
++        printk("%s: Mapped slot %d pin %d to IRQ %d\n", __FUNCTION__,slot, pin, irq);
++
++        return irq;
++}
++
++struct hw_pci fsg_pci __initdata = {
++	.nr_controllers = 1,
++	.preinit =        fsg_pci_preinit,
++	.swizzle =        pci_std_swizzle,
++	.setup =          ixp4xx_setup,
++	.scan =           ixp4xx_scan_bus,
++	.map_irq =        fsg_map_irq,
++};
++
++int __init fsg_pci_init(void)
++{
++	if (machine_is_fsg())
++		pci_common_init(&fsg_pci);
++	return 0;
++}
++
++subsys_initcall(fsg_pci_init);
+Index: linux-2.6.21.5-armeb/arch/arm/mach-ixp4xx/fsg-setup.c
+===================================================================
+--- /dev/null
++++ linux-2.6.21.5-armeb/arch/arm/mach-ixp4xx/fsg-setup.c
+@@ -0,0 +1,223 @@
++/*
++ * arch/arm/mach-ixp4xx/fsg-setup.c
++ *
++ * FSG board-setup
++ *
++ * based ixdp425-setup.c:
++ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Maintainers: http://www.nslu2-linux.org/
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++#include <linux/leds.h>
++#include <linux/mtd/mtd.h>
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data fsg_flash_data = {
++	.map_name		= "cfi_probe",
++	.width			= 2,
++};
++
++static struct resource fsg_flash_resource = {
++	.flags			= IORESOURCE_MEM,
++};
++
++static struct platform_device fsg_flash = {
++	.name			= "IXP4XX-Flash",
++	.id			= 0,
++	.dev.platform_data	= &fsg_flash_data,
++	.num_resources		= 1,
++	.resource		= &fsg_flash_resource,
++};
++
++static struct ixp4xx_i2c_pins fsg_i2c_gpio_pins = {
++	.sda_pin		= FSG_SDA_PIN,
++	.scl_pin		= FSG_SCL_PIN,
++};
++
++static struct platform_device fsg_i2c_controller = {
++        .name                   = "IXP4XX-I2C",
++        .id                     = 0,
++        .dev.platform_data      = &fsg_i2c_gpio_pins,
++        .num_resources          = 0,
++};
++
++static struct resource fsg_uart_resources[] = {
++	{
++		.start		= IXP4XX_UART1_BASE_PHYS,
++		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
++		.flags		= IORESOURCE_MEM,
++	},
++	{
++		.start		= IXP4XX_UART2_BASE_PHYS,
++		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
++		.flags		= IORESOURCE_MEM,
++	}
++};
++
++static struct plat_serial8250_port fsg_uart_data[] = {
++	{
++		.mapbase	= IXP4XX_UART1_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART1,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{
++		.mapbase	= IXP4XX_UART2_BASE_PHYS,
++		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++		.irq		= IRQ_IXP4XX_UART2,
++		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++		.iotype		= UPIO_MEM,
++		.regshift	= 2,
++		.uartclk	= IXP4XX_UART_XTAL,
++	},
++	{ }
++};
++
++static struct platform_device fsg_uart = {
++	.name			= "serial8250",
++	.id			= PLAT8250_DEV_PLATFORM,
++	.dev.platform_data	= fsg_uart_data,
++	.num_resources		= ARRAY_SIZE(fsg_uart_resources),
++	.resource		= fsg_uart_resources,
++};
++
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct resource res_mac0 = {
++        .start          = IXP4XX_EthB_BASE_PHYS,
++        .end            = IXP4XX_EthB_BASE_PHYS + 0x1ff,
++        .flags          = IORESOURCE_MEM,
++};
++
++static struct resource res_mac1 = {
++        .start          = IXP4XX_EthC_BASE_PHYS,
++        .end            = IXP4XX_EthC_BASE_PHYS + 0x1ff,
++        .flags          = IORESOURCE_MEM,
++};
++
++static struct mac_plat_info plat_mac0 = {
++        .npe_id         = 1,
++        .phy_id         = 5,
++        .eth_id         = 0,
++        .rxq_id         = 27,
++        .txq_id         = 24,
++	.rxdoneq_id     = 4,
++};
++
++static struct mac_plat_info plat_mac1 = {
++        .npe_id         = 2,
++        .phy_id         = 4,
++        .eth_id         = 1,
++        .rxq_id         = 28,
++        .txq_id         = 25,
++	.rxdoneq_id     = 5,
++};
++
++static struct platform_device mac0 = {
++        .name           = "ixp4xx_mac",
++        .id             = 0,
++        .dev.platform_data = &plat_mac0,
++        .num_resources  = 1,
++        .resource       = &res_mac0,
++};
++
++static struct platform_device mac1 = {
++        .name           = "ixp4xx_mac",
++        .id             = 1,
++        .dev.platform_data = &plat_mac1,
++        .num_resources  = 1,
++        .resource       = &res_mac1,
++};
++
++struct npe_ucode_platform_data fsg_npe_ucode_data = {
++	.mtd_partition	= "microcode",
++};
++
++static struct platform_device fsg_npe_ucode = {
++	.name			= "ixp4xx_npe_ucode",
++	.id			= 0,
++	.dev.platform_data	= &fsg_npe_ucode_data,
++};
++
++static struct platform_device *fsg_devices[] __initdata = {
++	&fsg_i2c_controller,
++	&fsg_flash,
++        &mac0,
++        &mac1,
++	&fsg_npe_ucode,
++};
++
++static void fsg_flash_add(struct mtd_info *mtd)
++{
++	if (strcmp(mtd->name, "RedBoot config") == 0) {
++		size_t retlen;
++		u_char mac[6];
++
++		if (mtd->read(mtd, 0x0422, 6, &retlen, mac) == 0 && retlen == 6) {
++			printk(KERN_INFO "eth0 mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++				mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++			memcpy(plat_mac0.hwaddr, mac, 6);
++			mac[5]++;
++			printk(KERN_INFO "eth1 mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++				mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++			memcpy(plat_mac1.hwaddr, mac, 6);
++		} else {
++			printk(KERN_ERR "fsg mac: read failed\n");
++		}
++	}
++}
++
++static void fsg_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier fsg_flash_notifier = {
++	.add = fsg_flash_add,
++	.remove = fsg_flash_remove,
++};
++
++static void __init fsg_init(void)
++{
++	ixp4xx_sys_init();
++
++	fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++	fsg_flash_resource.end =
++		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
++
++	*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++	/* Configure CS2 for operation, 8bit and writable */
++	*IXP4XX_EXP_CS2 = 0xbfff0002;
++
++	/* This is only useful on a modified machine, but it is valuable
++	 * to have it first in order to see debug messages, and so that
++	 * it does *not* get removed if platform_add_devices fails!
++	 */
++	(void)platform_device_register(&fsg_uart);
++
++	platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
++
++	register_mtd_user(&fsg_flash_notifier);
++}
++
++MACHINE_START(FSG, "Freecom FSG-3")
++	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
++	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++	.map_io		= ixp4xx_map_io,
++	.init_irq	= ixp4xx_init_irq,
++	.timer		= &ixp4xx_timer,
++	.boot_params	= 0x0100,
++	.init_machine	= fsg_init,
++MACHINE_END
++
+Index: linux-2.6.21.5-armeb/include/asm-arm/arch-ixp4xx/fsg.h
+===================================================================
+--- /dev/null
++++ linux-2.6.21.5-armeb/include/asm-arm/arch-ixp4xx/fsg.h
+@@ -0,0 +1,58 @@
++/*
++ * include/asm-arm/arch-ixp4xx/fsg.h
++ *
++ * Freecom FSG-3 platform specific definitions
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
++ * Maintainers: http://www.nslu2-linux.org
++ *
++ * Based on coyote.h by
++ * Copyright 2004 (c) MontaVista, Software, Inc.
++ *
++ * This file is licensed under  the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __ASM_ARCH_HARDWARE_H__
++#error "Do not include this directly, instead #include <asm/hardware.h>"
++#endif
++
++#define FSG_SDA_PIN		12
++#define FSG_SCL_PIN		13
++
++/*
++ * FSG PCI IRQs
++ */
++#define FSG_PCI_MAX_DEV		3
++#define FSG_PCI_IRQ_LINES	3
++
++
++/* PCI controller GPIO to IRQ pin mappings */
++#define FSG_PCI_INTA_PIN	6
++#define FSG_PCI_INTB_PIN	7
++#define FSG_PCI_INTC_PIN	5
++
++/* Buttons */
++
++#define FSG_SB_GPIO		4
++#define FSG_RB_GPIO		9
++#define FSG_UB_GPIO		10
++
++#define FSG_SB_IRQ		IRQ_IXP4XX_GPIO4
++#define FSG_RB_IRQ		IRQ_IXP4XX_GPIO9
++#define FSG_UB_IRQ		IRQ_IXP4XX_GPIO10
++
++#define FSG_SB_BM		(1L << FSG_SB_GPIO)
++#define FSG_RB_BM		(1L << FSG_RB_GPIO)
++#define FSG_UB_BM		(1L << FSG_UB_GPIO)
++
++/* LEDs */
++
++#define FSG_LED_RING_BIT	0
++#define FSG_LED_SYNC_BIT	1
++#define FSG_LED_USB_BIT		2
++#define FSG_LED_SATA_BIT	3
++#define FSG_LED_WAN_BIT		4
++#define FSG_LED_WLAN_BIT	5
+Index: linux-2.6.21.5-armeb/include/asm-arm/arch-ixp4xx/hardware.h
+===================================================================
+--- linux-2.6.21.5-armeb.orig/include/asm-arm/arch-ixp4xx/hardware.h
++++ linux-2.6.21.5-armeb/include/asm-arm/arch-ixp4xx/hardware.h
+@@ -48,5 +48,6 @@ extern unsigned int processor_id;
+ #include "nslu2.h"
+ #include "nas100d.h"
+ #include "dsmg600.h"
++#include "fsg.h"
+ 
+ #endif  /* _ASM_ARCH_HARDWARE_H */
+Index: linux-2.6.21.5-armeb/include/asm-arm/arch-ixp4xx/irqs.h
+===================================================================
+--- linux-2.6.21.5-armeb.orig/include/asm-arm/arch-ixp4xx/irqs.h
++++ linux-2.6.21.5-armeb/include/asm-arm/arch-ixp4xx/irqs.h
+@@ -128,4 +128,11 @@
+ #define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
+ #define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
+ 
++/*
++ * Freecom FSG-3 board IRQs
++ */
++#define        IRQ_FSG_PCI_INTA        IRQ_IXP4XX_GPIO6
++#define        IRQ_FSG_PCI_INTB        IRQ_IXP4XX_GPIO7
++#define        IRQ_FSG_PCI_INTC        IRQ_IXP4XX_GPIO5
++
+ #endif
+--- linux-2.6.21.6/arch/arm/mach-ixp4xx/Makefile~	2007-07-11 22:20:52.000000000 +0930
++++ linux-2.6.21.6/arch/arm/mach-ixp4xx/Makefile	2007-07-11 22:22:02.000000000 +0930
+@@ -13,6 +13,7 @@
+ obj-pci-$(CONFIG_MACH_NSLU2)		+= nslu2-pci.o
+ obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
+ obj-pci-$(CONFIG_MACH_DSMG600)		+= dsmg600-pci.o
++obj-pci-$(CONFIG_MACH_FSG)		+= fsg-pci.o
+ obj-pci-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2)		+= wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-pci.o
+@@ -29,6 +30,7 @@
+ obj-$(CONFIG_MACH_NSLU2)	+= nslu2-setup.o nslu2-power.o
+ obj-$(CONFIG_MACH_NAS100D)	+= nas100d-setup.o nas100d-power.o
+ obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o dsmg600-power.o
++obj-$(CONFIG_MACH_FSG)          += fsg-setup.o
+ obj-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-setup.o
+ obj-$(CONFIG_MACH_WG302V2)	+= wg302v2-setup.o
+ obj-$(CONFIG_MACH_PRONGHORNMETRO)	+= pronghornmetro-setup.o
+--- linux-2.6.21.6/arch/arm/mach-ixp4xx/Kconfig~	2007-07-11 22:23:24.000000000 +0930
++++ linux-2.6.21.6/arch/arm/mach-ixp4xx/Kconfig	2007-07-11 22:23:47.000000000 +0930
+@@ -138,6 +138,14 @@
+ 	  DSM-G600 RevA device. For more information on this platform,
+ 	  see http://www.nslu2-linux.org/wiki/DSMG600/HomePage
+ 
++config MACH_FSG
++	bool
++	prompt "Freecom FSG-3"
++	help
++	  Say 'Y' here if you want your kernel to support Freecom's
++	  FSG-3 device. For more information on this
++	  platform see http://www.openfsg.com/
++
+ #
+ # Avila and IXDP share the same source for now. Will change in future
+ #