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| author | Robert Marko <robimarko@gmail.com> | 2022-02-05 23:40:51 +0100 |
|---|---|---|
| committer | Robert Marko <robimarko@gmail.com> | 2023-01-16 12:42:23 +0100 |
| commit | b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8 (patch) | |
| tree | 18915922531fa451228c6aa6d136005c4e8b1c86 /target/linux/ipq807x/patches-5.15/0053-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch | |
| parent | 4f592fb819ca96b0f7a621b1bcc852e1f675f707 (diff) | |
| download | upstream-b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8.tar.gz upstream-b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8.tar.bz2 upstream-b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8.zip | |
ipq807x: add Qualcomm Atheros IPQ807x target
Qualcomm Atheros IPQ807x is a modern WiSoC featuring:
* Quad Core ARMv8 Cortex A-53
* @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye
* @ 1.4 GHz (IPQ8070A/1A) Codename Acorn
* Dual Band simultaneaous IEEE 802.11ax
* 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A)
* 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A)
* 5G: 2x2/80MHz (IPQ8070A)
* 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A)
* 2G: 2x2/40MHz (IPQ8070A/1A)
* 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports)
* 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye
* 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn
* DDR3L/4 32/16 bit up to 2400MT/s
* SDIO 3.0/SD card 3.0/eMMC 5.1
* Dual USB 3.0
* One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane)
* Parallel NAND (ONFI)/LCD
* 6x QUP BLSP SPI/I2C/UART
* I2S, PCM, and TDMA
* HW PWM
* 1.8V configurable GPIO
* Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc)
Note that only v2 SOC models aka the ones ending with A suffix are
supported, v1 models do not comply to the final 802.11ax and have
lower clocks, lack the Gen3 PCIe etc.
SoC itself has two UBI32 cores for the NSS offloading system, however
currently no offloading is supported.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Diffstat (limited to 'target/linux/ipq807x/patches-5.15/0053-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch')
| -rw-r--r-- | target/linux/ipq807x/patches-5.15/0053-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/target/linux/ipq807x/patches-5.15/0053-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch b/target/linux/ipq807x/patches-5.15/0053-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch new file mode 100644 index 0000000000..2594d26cfe --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0053-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch @@ -0,0 +1,36 @@ +From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001 +From: Robert Marko <robimarko@gmail.com> +Date: Sun, 30 Oct 2022 18:57:03 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC + +Pass XO and sleep clocks to the GCC controller so it does not have to +find them by matching globaly by name. + +If not passed directly, driver maintains backwards compatibility by then +falling back to global lookup. + +Since we are here, set cell numbers in decimal instead of hex. + +Signed-off-by: Robert Marko <robimarko@gmail.com> +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -360,9 +360,11 @@ + gcc: gcc@1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x01800000 0x80000>; +- #clock-cells = <0x1>; ++ clocks = <&xo>, <&sleep_clk>; ++ clock-names = "xo", "sleep_clk"; ++ #clock-cells = <1>; + #power-domain-cells = <1>; +- #reset-cells = <0x1>; ++ #reset-cells = <1>; + }; + + tcsr_mutex: hwlock@1905000 { |