diff options
| author | Robert Marko <robimarko@gmail.com> | 2022-02-05 23:40:51 +0100 |
|---|---|---|
| committer | Robert Marko <robimarko@gmail.com> | 2023-01-16 12:42:23 +0100 |
| commit | b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8 (patch) | |
| tree | 18915922531fa451228c6aa6d136005c4e8b1c86 /target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch | |
| parent | 4f592fb819ca96b0f7a621b1bcc852e1f675f707 (diff) | |
| download | upstream-b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8.tar.gz upstream-b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8.tar.bz2 upstream-b5f32064ed0c3a8b897377ec2fc895dc7a5f1bc8.zip | |
ipq807x: add Qualcomm Atheros IPQ807x target
Qualcomm Atheros IPQ807x is a modern WiSoC featuring:
* Quad Core ARMv8 Cortex A-53
* @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye
* @ 1.4 GHz (IPQ8070A/1A) Codename Acorn
* Dual Band simultaneaous IEEE 802.11ax
* 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A)
* 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A)
* 5G: 2x2/80MHz (IPQ8070A)
* 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A)
* 2G: 2x2/40MHz (IPQ8070A/1A)
* 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports)
* 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye
* 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn
* DDR3L/4 32/16 bit up to 2400MT/s
* SDIO 3.0/SD card 3.0/eMMC 5.1
* Dual USB 3.0
* One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane)
* Parallel NAND (ONFI)/LCD
* 6x QUP BLSP SPI/I2C/UART
* I2S, PCM, and TDMA
* HW PWM
* 1.8V configurable GPIO
* Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc)
Note that only v2 SOC models aka the ones ending with A suffix are
supported, v1 models do not comply to the final 802.11ax and have
lower clocks, lack the Gen3 PCIe etc.
SoC itself has two UBI32 cores for the NSS offloading system, however
currently no offloading is supported.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Diffstat (limited to 'target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch')
| -rw-r--r-- | target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch b/target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch new file mode 100644 index 0000000000..529f6715f2 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0018-v6.0-arm64-dts-qcom-Fix-sdhci-node-names-use-mmc.patch @@ -0,0 +1,34 @@ +From 2e9703ffe97a1c447c0d00c061526fbeeade6107 Mon Sep 17 00:00:00 2001 +From: Bhupesh Sharma <bhupesh.sharma@linaro.org> +Date: Sun, 15 May 2022 03:24:19 +0530 +Subject: [PATCH] arm64: dts: qcom: Fix sdhci node names - use 'mmc@' + +Since the Qualcomm sdhci-msm device-tree binding has been converted +to yaml format, 'make dtbs_check' reports issues with +inconsistent 'sdhci@' convention used for specifying the +sdhci nodes. The generic mmc bindings expect 'mmc@' format +instead. + +Fix the same. + +Cc: Bjorn Andersson <bjorn.andersson@linaro.org> +Cc: Rob Herring <robh@kernel.org> +Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> +[bjorn: Moved non-arm64 changes to separate commit] +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -375,7 +375,7 @@ + cell-index = <0>; + }; + +- sdhc_1: sdhci@7824900 { ++ sdhc_1: mmc@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7824900 0x500>, <0x7824000 0x800>; + reg-names = "hc_mem", "core_mem"; |