ipq807x: add Qualcomm Atheros IPQ807x target

Qualcomm Atheros IPQ807x is a modern WiSoC featuring:
* Quad Core ARMv8 Cortex A-53
	* @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye
	* @ 1.4 GHz (IPQ8070A/1A) Codename Acorn
* Dual Band simultaneaous IEEE 802.11ax
	* 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A)
	* 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A)
	* 5G: 2x2/80MHz (IPQ8070A)
	* 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A)
	* 2G: 2x2/40MHz (IPQ8070A/1A)
* 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports)
* 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye
* 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn
* DDR3L/4 32/16 bit up to 2400MT/s
* SDIO 3.0/SD card 3.0/eMMC 5.1
* Dual USB 3.0
* One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane)
* Parallel NAND (ONFI)/LCD
* 6x QUP BLSP SPI/I2C/UART
* I2S, PCM, and TDMA
* HW PWM
* 1.8V configurable GPIO
* Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc)

Note that only v2 SOC models aka the ones ending with A suffix are
supported, v1 models do not comply to the final 802.11ax and have
lower clocks, lack the Gen3 PCIe etc.

SoC itself has two UBI32 cores for the NSS offloading system, however
currently no offloading is supported.

Signed-off-by: Robert Marko <robimarko@gmail.com>

5 files changed, 1149 insertions, 0 deletions

diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-512m.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-512m.dtsi
new file mode 100644
index 0000000000..dace4008b3
--- /dev/null
+++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-512m.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "ipq8074.dtsi"
+
+&tzapp_region {
+	reg = <0x0 0x4a400000 0x0 0x100000>;
+};
+
+&q6_region {
+	reg = <0x0 0x4b000000 0x0 0x3700000>;
+};
+
+&q6_etr_region {
+	reg = <0x0 0x4e700000 0x0 0x100000>;
+};
+
+&m3_dump_region {
+	reg = <0x0 0x4e800000 0x0 0x100000>;
+};
diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi
new file mode 100644
index 0000000000..dbc9baa2b9
--- /dev/null
+++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <dt-bindings/thermal/thermal.h>
+#include "ipq8074-cpr-regulator.dtsi"
+
+&CPU0 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+
+&CPU1 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+
+&CPU2 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+
+&CPU3 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+&cpu0_thermal {
+	trips {
+		cpu0_passive: cpu-passive {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu0_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu0_passive>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cpu1_thermal {
+	trips {
+		cpu1_passive: cpu-passive {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu1_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu1_passive>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cpu2_thermal {
+	trips {
+		cpu2_passive: cpu-passive {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu2_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu2_passive>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cpu3_thermal {
+	trips {
+		cpu3_passive: cpu-passive {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu3_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu3_passive>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cluster_thermal {
+	trips {
+		cluster_passive: cluster-passive {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cluster_crit: cluster_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cluster_passive>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi
new file mode 100644
index 0000000000..e351a2e759
--- /dev/null
+++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "pmp8074.dtsi"
+
+&soc {
+	apc_apm: apm@b111000 {
+		compatible = "qcom,ipq807x-apm";
+		reg = <0xb111000 0x1000>;
+		reg-names = "pm-apcc-glb";
+		qcom,apm-post-halt-delay = <0x2>;
+		qcom,apm-halt-clk-delay = <0x11>;
+		qcom,apm-resume-clk-delay = <0x10>;
+		qcom,apm-sel-switch-delay = <0x01>;
+	};
+
+	apc_cpr: cpr4-ctrl@b018000 {
+		compatible = "qcom,cpr4-ipq807x-apss-regulator";
+		reg = <0xb018000 0x4000>, <0xa4000 0x1000>, <0x0193d008 0x4>;
+		reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg";
+		interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "cpr";
+		qcom,cpr-ctrl-name = "apc";
+		qcom,cpr-sensor-time = <1000>;
+		qcom,cpr-loop-time = <5000000>;
+		qcom,cpr-idle-cycles = <15>;
+		qcom,cpr-step-quot-init-min = <12>;
+		qcom,cpr-step-quot-init-max = <14>;
+		qcom,cpr-count-mode = <0>;		/* All-at-once */
+		qcom,cpr-count-repeat = <14>;
+		qcom,cpr-down-error-step-limit = <1>;
+		qcom,cpr-up-error-step-limit = <1>;
+		qcom,apm-ctrl = <&apc_apm>;
+		qcom,apm-threshold-voltage = <848000>;
+		vdd-supply = <&s3>;
+		qcom,voltage-step = <8000>;
+
+		thread@0 {
+			qcom,cpr-thread-id = <0>;
+			qcom,cpr-consecutive-up = <0>;
+			qcom,cpr-consecutive-down = <0>;
+			qcom,cpr-up-threshold = <4>;
+			qcom,cpr-down-threshold = <1>;
+
+			apc_vreg: regulator {
+				regulator-name = "apc_corner";
+				regulator-min-microvolt = <1>;
+				regulator-max-microvolt = <6>;
+				qcom,cpr-part-types = <2>;
+				qcom,cpr-parts-voltage = <1048000>;
+				qcom,cpr-parts-voltage-v2 = <992000>;
+				qcom,cpr-fuse-corners = <4>;
+				qcom,cpr-fuse-combos = <8>;
+				qcom,cpr-corners = <6>;
+				qcom,cpr-speed-bins = <1>;
+				qcom,cpr-speed-bin-corners = <6>;
+				qcom,cpr-corner-fmax-map = <1 3 5 6>;
+				qcom,allow-voltage-interpolation;
+				qcom,allow-quotient-interpolation;
+				qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+				qcom,cpr-voltage-ceiling =
+					<840000 904000 944000
+					 984000 992000 1064000>;
+				qcom,cpr-voltage-floor =
+					<592000 648000 712000
+					 744000 784000 848000>;
+				qcom,corner-frequencies =
+					<1017600000 1382400000 1651200000
+					1843200000 1920000000 2208000000>;
+
+				/* TT/FF parts i.e. turbo L1 OL voltage < 1048 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0 12000>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				/* SS parts i.e turbo L1 OL voltage >= 1048 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					< 20000  26000      0 20000>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				/* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0 =
+                                        /* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				/* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1 =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     0   7000  36000  4000>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				/* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
+				qcom,cpr-closed-loop-voltage-adjustment-v2-0 =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				/* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
+				qcom,cpr-closed-loop-voltage-adjustment-v2-1 =
+					/* Speed bin 0; CPR rev 0..7 */
+					<     0      0      0     0>,
+					<     0      0      19000 0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>,
+					<     0      0      0     0>;
+
+				qcom,cpr-ro-scaling-factor =
+					< 3970 4150 0    2280 2520 2470 2250 2280
+					  2390 2330 2530 2500  850 2900 2510 2170 >,
+					< 3970 4150 0    2280 2520 2470 2250 2280
+					  2390 2330 2530 2500  850 2900 2510 2170 >,
+					< 3970 4150 0    2280 2520 2470 2250 2280
+					  2390 2330 2530 2500  850 2900 2510 2170 >,
+					< 3970 4150 0    2280 2520 2470 2250 2280
+					  2390 2330 2530 2500  850 2900 2510 2170 >;
+
+				qcom,cpr-floor-to-ceiling-max-range =
+					< 40000 40000 40000 40000 40000 40000>,
+					< 40000 40000 40000 40000 40000 40000>,
+					< 40000 40000 40000 40000 40000 40000>,
+					< 40000 40000 40000 40000 40000 40000>,
+					< 40000 40000 40000 40000 40000 40000>,
+					< 40000 40000 40000 40000 40000 40000>,
+					< 40000 40000 40000 40000 40000 40000>,
+					< 40000 40000 40000 40000 40000 40000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	npu_cpr: npu-cpr {
+		compatible = "qcom,cpr3-ipq807x-npu-regulator";
+		reg = <0xa4000 0x1000>, <0x0193d008 0x4>;
+		reg-names = "fuse_base", "cpr_tcsr_reg";
+		qcom,cpr-ctrl-name = "npu";
+		vdd-supply = <&s4>;
+		qcom,voltage-step = <8000>;
+		thread@0 {
+			qcom,cpr-thread-id = <0>;
+			qcom,cpr-consecutive-up = <0>;
+			qcom,cpr-consecutive-down = <2>;
+			qcom,cpr-up-threshold = <2>;
+			qcom,cpr-down-threshold = <1>;
+
+			npu_vreg: regulator {
+				regulator-name = "npu_corner";
+				regulator-min-microvolt = <1>;
+				regulator-max-microvolt = <3>;
+				qcom,cpr-part-types = <2>;
+				qcom,cpr-parts-voltage = <968000>;
+				qcom,cpr-parts-voltage-v2 = <832001>;
+				qcom,cpr-cold-temp-threshold-v2 = <30>;
+				qcom,cpr-fuse-corners = <2>;
+				qcom,cpr-fuse-combos = <1>;
+				qcom,cpr-corners = <2>;
+				qcom,cpr-speed-bins = <1>;
+				qcom,cpr-speed-bin-corners = <2>;
+				qcom,allow-voltage-interpolation;
+				qcom,cpr-corner-fmax-map = <1 2>;
+				qcom,cpr-voltage-ceiling =
+					<912000 992000>;
+				qcom,cpr-voltage-floor =
+					<752000 792000>;
+				qcom,corner-frequencies =
+					<1497600000 1689600000>;
+
+				/* TT/FF parts i.e. turbo OL voltage < 968 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
+					< 40000   40000>;
+
+				/* SS parts i.e turbo OL voltage >= 968 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
+					< 24000   24000>;
+
+				/* FF parts i.e. turbo OL voltage <= 832 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0=
+					<40000   40000>;
+
+				 /* TT/SS parts i.e turbo OL voltage > 832 mV */
+				qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1=
+					<40000   40000>;
+
+				/* FF parts i.e. turbo OL voltage <= 832 mV */
+				qcom,cpr-cold-temp-voltage-adjustment-v2-0 =
+					<0   0>;
+
+				/* TT/SS parts i.e turbo OL voltage > 832 mV */
+				qcom,cpr-cold-temp-voltage-adjustment-v2-1 =
+					<35000   27000>;
+			};
+		};
+	};
+};
diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
new file mode 100644
index 0000000000..129266c50d
--- /dev/null
+++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+&clocks {
+	bias_pll_cc_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <300000000>;
+		#clock-cells = <0>;
+	};
+
+	bias_pll_nss_noc_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <416500000>;
+		#clock-cells = <0>;
+	};
+};
+
+&soc {
+	switch: ess-switch@3a000000 {
+		compatible = "qcom,ess-switch-ipq807x";
+		reg = <0x3a000000 0x1000000>;
+		switch_access_mode = "local bus";
+		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
+		switch_inner_bmp = <0x80>; /*inner port bitmap*/
+		clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+			 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
+			 <&gcc GCC_UNIPHY0_AHB_CLK>,
+			 <&gcc GCC_UNIPHY0_SYS_CLK>,
+			 <&gcc GCC_UNIPHY1_AHB_CLK>,
+			 <&gcc GCC_UNIPHY1_SYS_CLK>,
+			 <&gcc GCC_UNIPHY2_AHB_CLK>,
+			 <&gcc GCC_UNIPHY2_SYS_CLK>,
+			 <&gcc GCC_PORT1_MAC_CLK>,
+			 <&gcc GCC_PORT2_MAC_CLK>,
+			 <&gcc GCC_PORT3_MAC_CLK>,
+			 <&gcc GCC_PORT4_MAC_CLK>,
+			 <&gcc GCC_PORT5_MAC_CLK>,
+			 <&gcc GCC_PORT6_MAC_CLK>,
+			 <&gcc GCC_NSS_PPE_CLK>,
+			 <&gcc GCC_NSS_PPE_CFG_CLK>,
+			 <&gcc GCC_NSSNOC_PPE_CLK>,
+			 <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
+			 <&gcc GCC_NSS_EDMA_CLK>,
+			 <&gcc GCC_NSS_EDMA_CFG_CLK>,
+			 <&gcc GCC_NSS_PPE_IPE_CLK>,
+			 <&gcc GCC_NSS_PPE_BTQ_CLK>,
+			 <&gcc GCC_MDIO_AHB_CLK>,
+			 <&gcc GCC_NSS_NOC_CLK>,
+			 <&gcc GCC_NSSNOC_SNOC_CLK>,
+			 <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
+			 <&gcc GCC_NSS_CRYPTO_CLK>,
+			 <&gcc GCC_NSS_IMEM_CLK>,
+			 <&gcc GCC_NSS_PTP_REF_CLK>,
+			 <&gcc GCC_NSS_PORT1_RX_CLK>,
+			 <&gcc GCC_NSS_PORT1_TX_CLK>,
+			 <&gcc GCC_NSS_PORT2_RX_CLK>,
+			 <&gcc GCC_NSS_PORT2_TX_CLK>,
+			 <&gcc GCC_NSS_PORT3_RX_CLK>,
+			 <&gcc GCC_NSS_PORT3_TX_CLK>,
+			 <&gcc GCC_NSS_PORT4_RX_CLK>,
+			 <&gcc GCC_NSS_PORT4_TX_CLK>,
+			 <&gcc GCC_NSS_PORT5_RX_CLK>,
+			 <&gcc GCC_NSS_PORT5_TX_CLK>,
+			 <&gcc GCC_NSS_PORT6_RX_CLK>,
+			 <&gcc GCC_NSS_PORT6_TX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
+			 <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
+			 <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
+			 <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
+			 <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
+			 <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
+			 <&gcc NSS_PORT5_RX_CLK_SRC>,
+			 <&gcc NSS_PORT5_TX_CLK_SRC>;
+		clock-names = "cmn_ahb_clk", "cmn_sys_clk",
+			      "uniphy0_ahb_clk", "uniphy0_sys_clk",
+			      "uniphy1_ahb_clk", "uniphy1_sys_clk",
+			      "uniphy2_ahb_clk", "uniphy2_sys_clk",
+			      "port1_mac_clk", "port2_mac_clk",
+			      "port3_mac_clk", "port4_mac_clk",
+			      "port5_mac_clk", "port6_mac_clk",
+			      "nss_ppe_clk", "nss_ppe_cfg_clk",
+			      "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
+			      "nss_edma_clk", "nss_edma_cfg_clk",
+			      "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
+			      "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
+			      "gcc_nssnoc_snoc_clk",
+			      "gcc_mem_noc_nss_axi_clk",
+			      "gcc_nss_crypto_clk",
+			      "gcc_nss_imem_clk",
+			      "gcc_nss_ptp_ref_clk",
+			      "nss_port1_rx_clk", "nss_port1_tx_clk",
+			      "nss_port2_rx_clk", "nss_port2_tx_clk",
+			      "nss_port3_rx_clk", "nss_port3_tx_clk",
+			      "nss_port4_rx_clk", "nss_port4_tx_clk",
+			      "nss_port5_rx_clk", "nss_port5_tx_clk",
+			      "nss_port6_rx_clk", "nss_port6_tx_clk",
+			      "uniphy0_port1_rx_clk",
+			      "uniphy0_port1_tx_clk",
+			      "uniphy0_port2_rx_clk",
+			      "uniphy0_port2_tx_clk",
+			      "uniphy0_port3_rx_clk",
+			      "uniphy0_port3_tx_clk",
+			      "uniphy0_port4_rx_clk",
+			      "uniphy0_port4_tx_clk",
+			      "uniphy0_port5_rx_clk",
+			      "uniphy0_port5_tx_clk",
+			      "uniphy1_port5_rx_clk",
+			      "uniphy1_port5_tx_clk",
+			      "uniphy2_port6_rx_clk",
+			      "uniphy2_port6_tx_clk",
+			      "nss_port5_rx_clk_src",
+			      "nss_port5_tx_clk_src";
+		resets = <&gcc GCC_PPE_FULL_RESET>,
+			 <&gcc GCC_UNIPHY0_SOFT_RESET>,
+			 <&gcc GCC_UNIPHY0_XPCS_RESET>,
+			 <&gcc GCC_UNIPHY1_SOFT_RESET>,
+			 <&gcc GCC_UNIPHY1_XPCS_RESET>,
+			 <&gcc GCC_UNIPHY2_SOFT_RESET>,
+			 <&gcc GCC_UNIPHY2_XPCS_RESET>,
+			 <&gcc GCC_NSSPORT1_RESET>,
+			 <&gcc GCC_NSSPORT2_RESET>,
+			 <&gcc GCC_NSSPORT3_RESET>,
+			 <&gcc GCC_NSSPORT4_RESET>,
+			 <&gcc GCC_NSSPORT5_RESET>,
+			 <&gcc GCC_NSSPORT6_RESET>;
+		reset-names = "ppe_rst", "uniphy0_soft_rst",
+			      "uniphy0_xpcs_rst", "uniphy1_soft_rst",
+			      "uniphy1_xpcs_rst", "uniphy2_soft_rst",
+			      "uniphy2_xpcs_rst", "nss_port1_rst",
+			      "nss_port2_rst", "nss_port3_rst",
+			      "nss_port4_rst", "nss_port5_rst",
+			      "nss_port6_rst";
+		mdio-bus = <&mdio>;
+		status = "disabled";
+
+		port_scheduler_resource {
+			port@0 {
+				port_id = <0>;
+				ucast_queue = <0 143>;
+				mcast_queue = <256 271>;
+				l0sp = <0 35>;
+				l0cdrr = <0 47>;
+				l0edrr = <0 47>;
+				l1cdrr = <0 7>;
+				l1edrr = <0 7>;
+			};
+			port@1 {
+				port_id = <1>;
+				ucast_queue = <144 159>;
+				mcast_queue = <272 275>;
+				l0sp = <36 39>;
+				l0cdrr = <48 63>;
+				l0edrr = <48 63>;
+				l1cdrr = <8 11>;
+				l1edrr = <8 11>;
+			};
+			port@2 {
+				port_id = <2>;
+				ucast_queue = <160 175>;
+				mcast_queue = <276 279>;
+				l0sp = <40 43>;
+				l0cdrr = <64 79>;
+				l0edrr = <64 79>;
+				l1cdrr = <12 15>;
+				l1edrr = <12 15>;
+			};
+			port@3 {
+				port_id = <3>;
+				ucast_queue = <176 191>;
+				mcast_queue = <280 283>;
+				l0sp = <44 47>;
+				l0cdrr = <80 95>;
+				l0edrr = <80 95>;
+				l1cdrr = <16 19>;
+				l1edrr = <16 19>;
+			};
+			port@4 {
+				port_id = <4>;
+				ucast_queue = <192 207>;
+				mcast_queue = <284 287>;
+				l0sp = <48 51>;
+				l0cdrr = <96 111>;
+				l0edrr = <96 111>;
+				l1cdrr = <20 23>;
+				l1edrr = <20 23>;
+			};
+			port@5 {
+				port_id = <5>;
+				ucast_queue = <208 223>;
+				mcast_queue = <288 291>;
+				l0sp = <52 55>;
+				l0cdrr = <112 127>;
+				l0edrr = <112 127>;
+				l1cdrr = <24 27>;
+				l1edrr = <24 27>;
+			};
+			port@6 {
+				port_id = <6>;
+				ucast_queue = <224 239>;
+				mcast_queue = <292 295>;
+				l0sp = <56 59>;
+				l0cdrr = <128 143>;
+				l0edrr = <128 143>;
+				l1cdrr = <28 31>;
+				l1edrr = <28 31>;
+			};
+			port@7 {
+				port_id = <7>;
+				ucast_queue = <240 255>;
+				mcast_queue = <296 299>;
+				l0sp = <60 63>;
+				l0cdrr = <144 159>;
+				l0edrr = <144 159>;
+				l1cdrr = <32 35>;
+				l1edrr = <32 35>;
+			};
+		};
+		port_scheduler_config {
+			port@0 {
+				port_id = <0>;
+				l1scheduler {
+					group@0 {
+						sp = <0 1>; /*L0 SPs*/
+						/*cpri cdrr epri edrr*/
+						cfg = <0 0 0 0>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						/*unicast queues*/
+						ucast_queue = <0 4 8>;
+						/*multicast queues*/
+						mcast_queue = <256 260>;
+						/*sp cpri cdrr epri edrr*/
+						cfg = <0 0 0 0 0>;
+					};
+					group@1 {
+						ucast_queue = <1 5 9>;
+						mcast_queue = <257 261>;
+						cfg = <0 1 1 1 1>;
+					};
+					group@2 {
+						ucast_queue = <2 6 10>;
+						mcast_queue = <258 262>;
+						cfg = <0 2 2 2 2>;
+					};
+					group@3 {
+						ucast_queue = <3 7 11>;
+						mcast_queue = <259 263>;
+						cfg = <0 3 3 3 3>;
+					};
+				};
+			};
+			port@1 {
+				port_id = <1>;
+				l1scheduler {
+					group@0 {
+						sp = <36>;
+						cfg = <0 8 0 8>;
+					};
+					group@1 {
+						sp = <37>;
+						cfg = <1 9 1 9>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						ucast_queue = <144>;
+						ucast_loop_pri = <16>;
+						mcast_queue = <272>;
+						mcast_loop_pri = <4>;
+						cfg = <36 0 48 0 48>;
+					};
+				};
+			};
+			port@2 {
+				port_id = <2>;
+				l1scheduler {
+					group@0 {
+						sp = <40>;
+						cfg = <0 12 0 12>;
+					};
+					group@1 {
+						sp = <41>;
+						cfg = <1 13 1 13>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						ucast_queue = <160>;
+						ucast_loop_pri = <16>;
+						mcast_queue = <276>;
+						mcast_loop_pri = <4>;
+						cfg = <40 0 64 0 64>;
+					};
+				};
+			};
+			port@3 {
+				port_id = <3>;
+				l1scheduler {
+					group@0 {
+						sp = <44>;
+						cfg = <0 16 0 16>;
+					};
+					group@1 {
+						sp = <45>;
+						cfg = <1 17 1 17>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						ucast_queue = <176>;
+						ucast_loop_pri = <16>;
+						mcast_queue = <280>;
+						mcast_loop_pri = <4>;
+						cfg = <44 0 80 0 80>;
+					};
+				};
+			};
+			port@4 {
+				port_id = <4>;
+				l1scheduler {
+					group@0 {
+						sp = <48>;
+						cfg = <0 20 0 20>;
+					};
+					group@1 {
+						sp = <49>;
+						cfg = <1 21 1 21>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						ucast_queue = <192>;
+						ucast_loop_pri = <16>;
+						mcast_queue = <284>;
+						mcast_loop_pri = <4>;
+						cfg = <48 0 96 0 96>;
+					};
+				};
+			};
+			port@5 {
+				port_id = <5>;
+				l1scheduler {
+					group@0 {
+						sp = <52>;
+						cfg = <0 24 0 24>;
+					};
+					group@1 {
+						sp = <53>;
+						cfg = <1 25 1 25>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						ucast_queue = <208>;
+						ucast_loop_pri = <16>;
+						mcast_queue = <288>;
+						mcast_loop_pri = <4>;
+						cfg = <52 0 112 0 112>;
+					};
+				};
+			};
+			port@6 {
+				port_id = <6>;
+				l1scheduler {
+					group@0 {
+						sp = <56>;
+						cfg = <0 28 0 28>;
+					};
+					group@1 {
+						sp = <57>;
+						cfg = <1 29 1 29>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						ucast_queue = <224>;
+						ucast_loop_pri = <16>;
+						mcast_queue = <292>;
+						mcast_loop_pri = <4>;
+						cfg = <56 0 128 0 128>;
+					};
+				};
+			};
+			port@7 {
+				port_id = <7>;
+				l1scheduler {
+					group@0 {
+						sp = <60>;
+						cfg = <0 32 0 32>;
+					};
+					group@1 {
+						sp = <61>;
+						cfg = <1 33 1 33>;
+					};
+				};
+				l0scheduler {
+					group@0 {
+						ucast_queue = <240>;
+						ucast_loop_pri = <16>;
+						mcast_queue = <296>;
+						cfg = <60 0 144 0 144>;
+					};
+				};
+			};
+		};
+	};
+
+	ess-uniphy@7a00000 {
+		compatible = "qcom,ess-uniphy";
+		reg = <0x7a00000 0x30000>;
+		uniphy_access_mode = "local bus";
+	};
+
+	edma: edma@3ab00000 {
+		compatible = "qcom,edma";
+		reg = <0x3ab00000 0x76900>;
+		reg-names = "edma-reg-base";
+		qcom,txdesc-ring-start = <23>;
+		qcom,txdesc-rings = <1>;
+		qcom,txcmpl-ring-start = <7>;
+		qcom,txcmpl-rings = <1>;
+		qcom,rxfill-ring-start = <7>;
+		qcom,rxfill-rings = <1>;
+		qcom,rxdesc-ring-start = <15>;
+		qcom,rxdesc-rings = <1>;
+		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+		resets = <&gcc GCC_EDMA_HW_RESET>;
+		reset-names = "edma_rst";
+		status = "disabled";
+	};
+
+	dp1: dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <1>;
+		reg = <0x3a001000 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+
+	dp2: dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x3a001200 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+
+	dp3: dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x3a001400 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+
+	dp4: dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+
+	dp5: dp5 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a001800 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+
+	dp6: dp6 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <6>;
+		reg = <0x3a001a00 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+
+	dp5_syn: dp5-syn {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a003000 0x3fff>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+
+	dp6_syn: dp6-syn {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <6>;
+		reg = <0x3a007000 0x3fff>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+		status = "disabled";
+	};
+};
diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi
new file mode 100644
index 0000000000..8485814969
--- /dev/null
+++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <dt-bindings/thermal/thermal.h>
+#include "ipq8074-cpr-regulator.dtsi"
+
+&CPU0 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+
+&CPU1 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+
+&CPU2 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+
+&CPU3 {
+	cpu-supply = <&apc_vreg>;
+	voltage-tolerance = <1>;
+};
+&cpu0_thermal {
+	trips {
+		cpu0_passive_low: cpu-passive-low {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu0_passive_high: cpu-passive-high {
+			temperature = <100000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu0_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu0_passive_low>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+		map1 {
+			trip = <&cpu0_passive_high>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cpu1_thermal {
+	trips {
+		cpu1_passive_low: cpu-passive-low {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu1_passive_high: cpu-passive-high {
+			temperature = <100000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu1_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu1_passive_low>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+		map1 {
+			trip = <&cpu1_passive_high>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cpu2_thermal {
+	trips {
+		cpu2_passive_low: cpu-passive-low {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu2_passive_high: cpu-passive-high {
+			temperature = <100000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu2_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu2_passive_low>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+		map1 {
+			trip = <&cpu2_passive_high>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cpu3_thermal {
+	trips {
+		cpu3_passive_low: cpu-passive-low {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu3_passive_high: cpu-passive-high {
+			temperature = <100000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cpu3_crit: cpu_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cpu3_passive_low>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+		map1 {
+			trip = <&cpu3_passive_high>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&cluster_thermal {
+	trips {
+		cluster_passive_low: cluster-passive {
+			temperature = <95000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cluster_passive_high: cluster-passive-high {
+			temperature = <100000>;
+			hysteresis = <2000>;
+			type = "passive";
+		};
+
+		cluster_crit: cluster_crit {
+			temperature = <110000>;
+			hysteresis = <1000>;
+			type = "critical";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&cluster_passive_low>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+		map1 {
+			trip = <&cluster_passive_high>;
+			cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};