diff options
| author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-03-01 01:10:03 +0100 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2021-05-07 07:05:16 +0200 |
| commit | e17fb62293d59861646ad20aca6d440a7c08b45a (patch) | |
| tree | fdcb9e470c14ac500af900bc042ddf18f7106bb5 /target/linux/ipq806x | |
| parent | e2b0ad1114d46bc4dc1c89a9a4a7636e2c209c60 (diff) | |
| download | upstream-e17fb62293d59861646ad20aca6d440a7c08b45a.tar.gz upstream-e17fb62293d59861646ad20aca6d440a7c08b45a.tar.bz2 upstream-e17fb62293d59861646ad20aca6d440a7c08b45a.zip | |
ipq806x: drop upstream patch
Drop upstream patch already included in the kernel 5.10
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Diffstat (limited to 'target/linux/ipq806x')
16 files changed, 0 insertions, 2131 deletions
diff --git a/target/linux/ipq806x/patches-5.10/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq806x/patches-5.10/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch deleted file mode 100644 index 0dc9debbfd..0000000000 --- a/target/linux/ipq806x/patches-5.10/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch +++ /dev/null @@ -1,70 +0,0 @@ -From patchwork Mon May 21 20:57:38 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property -X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com> -X-Patchwork-Id: 917856 -Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com> -To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org -Cc: Bjorn Andersson <bjorn.andersson@linaro.org>, - Linus Walleij <linus.walleij@linaro.org>, - Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>, - Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, - Andy Gross <andy.gross@linaro.org>, - Sven Eckelmann <sven.eckelmann@openmesh.com> -Date: Mon, 21 May 2018 22:57:38 +0200 -From: Christian Lamparter <chunkeey@gmail.com> -List-Id: <linux-gpio.vger.kernel.org> - -This patch adds the gpio-ranges property to almost all of -the Qualcomm ARM platforms that utilize the pinctrl-msm -framework. - -The gpio-ranges property is part of the gpiolib subsystem. -As a result, the binding text is available in section -"2.1 gpio- and pin-controller interaction" of -Documentation/devicetree/bindings/gpio/gpio.txt - -For more information please see the patch titled: -"pinctrl: msm: fix gpio-hog related boot issues" from -this series. - -Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> -Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] -Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> -Signed-off-by: Christian Lamparter <chunkeey@gmail.com> -Reviewed-by: Linus Walleij <linus.walleij@linaro.org> ---- -To help with git bisect, the DT update patch has been intentionally -placed after the "pinctrl: msm: fix gpio-hog related boot issues". -Otherwise - if the order was reveresed - and bisect decides to split -between these two patches, the gpiochip_add_pin_ranges() function -will be executed twice with the same parameters for the same pinctrl. ---- - arch/arm/boot/dts/qcom-apq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + - arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 + - arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8960.dtsi | 1 + - arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 + - arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 + - 13 files changed, 14 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -119,6 +119,7 @@ - reg = <0x800000 0x4000>; - - gpio-controller; -+ gpio-ranges = <&qcom_pinmux 0 0 69>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; diff --git a/target/linux/ipq806x/patches-5.10/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch b/target/linux/ipq806x/patches-5.10/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch deleted file mode 100644 index f5483ac734..0000000000 --- a/target/linux/ipq806x/patches-5.10/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 51befb888f62b1a62434fb4b82328d698a30f9de Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Thu, 19 Mar 2020 23:44:24 +0100 -Subject: ARM: dts: qcom: add scm definition to ipq806x - -Add missing scm definition for ipq806x soc - -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Link: https://lore.kernel.org/r/20200319224424.18473-1-ansuelsmth@gmail.com -Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -93,6 +93,12 @@ - }; - }; - -+ firmware { -+ scm { -+ compatible = "qcom,scm-ipq806x", "qcom,scm"; -+ }; -+ }; -+ - soc: soc { - #address-cells = <1>; - #size-cells = <1>; diff --git a/target/linux/ipq806x/patches-5.10/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch b/target/linux/ipq806x/patches-5.10/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch deleted file mode 100644 index 2b5171fc54..0000000000 --- a/target/linux/ipq806x/patches-5.10/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001 -From: Ajay Kishore <akisho@codeaurora.org> -Date: Fri, 27 Mar 2020 23:32:08 +0100 -Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps - -For IPQ806x targets, TZ protects the registers that are used to -configure the routing of interrupts to a target processor. -To resolve this, this patch uses scm call to route GPIO interrupts -to application processor. Also the scm call interface is changed. - -Signed-off-by: Ajay Kishore <akisho@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com -Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------ - 1 file changed, 37 insertions(+), 6 deletions(-) - -(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c') - ---- a/drivers/pinctrl/qcom/pinctrl-msm.c -+++ b/drivers/pinctrl/qcom/pinctrl-msm.c -@@ -22,6 +22,8 @@ - #include <linux/reboot.h> - #include <linux/pm.h> - #include <linux/log2.h> -+#include <linux/qcom_scm.h> -+#include <linux/io.h> - - #include "../core.h" - #include "../pinconf.h" -@@ -57,6 +59,8 @@ struct msm_pinctrl { - struct irq_chip irq_chip; - int irq; - -+ bool intr_target_use_scm; -+ - raw_spinlock_t lock; - - DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); -@@ -64,6 +68,7 @@ struct msm_pinctrl { - - const struct msm_pinctrl_soc_data *soc; - void __iomem *regs[MAX_NR_TILES]; -+ u32 phys_base[MAX_NR_TILES]; - }; - - #define MSM_ACCESSOR(name) \ -@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct - else - clear_bit(d->hwirq, pctrl->dual_edge_irqs); - -- /* Route interrupts to application cpu */ -- val = msm_readl_intr_target(pctrl, g); -- val &= ~(7 << g->intr_target_bit); -- val |= g->intr_target_kpss_val << g->intr_target_bit; -- msm_writel_intr_target(val, pctrl, g); -+ /* Route interrupts to application cpu. -+ * With intr_target_use_scm interrupts are routed to -+ * application cpu using scm calls. -+ */ -+ if (pctrl->intr_target_use_scm) { -+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg; -+ int ret; -+ -+ qcom_scm_io_readl(addr, &val); -+ -+ val &= ~(7 << g->intr_target_bit); -+ val |= g->intr_target_kpss_val << g->intr_target_bit; -+ -+ ret = qcom_scm_io_writel(addr, val); -+ if (ret) -+ dev_err(pctrl->dev, -+ "Failed routing %lu interrupt to Apps proc", -+ d->hwirq); -+ } else { -+ val = msm_readl_intr_target(pctrl, g); -+ val &= ~(7 << g->intr_target_bit); -+ val |= g->intr_target_kpss_val << g->intr_target_bit; -+ msm_writel_intr_target(val, pctrl, g); -+ } - - /* Update configuration for gpio. - * RAW_STATUS_EN is left on for all gpio irqs. Due to the -@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de - pctrl->dev = &pdev->dev; - pctrl->soc = soc_data; - pctrl->chip = msm_gpio_template; -+ pctrl->intr_target_use_scm = of_device_is_compatible( -+ pctrl->dev->of_node, -+ "qcom,ipq8064-pinctrl"); - - raw_spin_lock_init(&pctrl->lock); - -@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de - pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pctrl->regs[0])) - return PTR_ERR(pctrl->regs[0]); -+ -+ pctrl->phys_base[0] = res->start; - } - - msm_pinctrl_setup_pm_reset(pctrl); diff --git a/target/linux/ipq806x/patches-5.10/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch b/target/linux/ipq806x/patches-5.10/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch deleted file mode 100644 index 612c33cd0e..0000000000 --- a/target/linux/ipq806x/patches-5.10/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Wed, 19 Feb 2020 18:59:39 +0100 -Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions - -Add missing gpio definition for mdio and rgmii2. - -Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com -Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c -+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c -@@ -299,7 +299,7 @@ static const char * const gpio_groups[] - }; - - static const char * const mdio_groups[] = { -- "gpio0", "gpio1", "gpio10", "gpio11", -+ "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66", - }; - - static const char * const mi2s_groups[] = { -@@ -403,8 +403,8 @@ static const char * const usb2_hsic_grou - }; - - static const char * const rgmii2_groups[] = { -- "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", -- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", -+ "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66", - }; - - static const char * const sata_groups[] = { -@@ -539,7 +539,7 @@ static const struct msm_function ipq8064 - static const struct msm_pingroup ipq8064_groups[] = { - PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), -- PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), -+ PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), -@@ -603,7 +603,7 @@ static const struct msm_pingroup ipq8064 - PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), -- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), -+ PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), diff --git a/target/linux/ipq806x/patches-5.10/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch b/target/linux/ipq806x/patches-5.10/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch deleted file mode 100644 index 605eb7d07b..0000000000 --- a/target/linux/ipq806x/patches-5.10/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Tue, 4 Feb 2020 20:56:48 +0100 -Subject: watchdog: qcom-wdt: disable pretimeout on timer platform - -Some platform like ipq806x doesn't support pretimeout and define -some interrupts used by qcom,msm-timer. Change the driver to check -and use pretimeout only on qcom,kpss-wdt as it's the only platform -that actually supports it. - -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Reviewed-by: Guenter Roeck <linux@roeck-us.net> -Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com -[groeck: Conflict resolution] -Signed-off-by: Guenter Roeck <linux@roeck-us.net> -Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> ---- - drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++-------- - 1 file changed, 23 insertions(+), 8 deletions(-) - ---- a/drivers/watchdog/qcom-wdt.c -+++ b/drivers/watchdog/qcom-wdt.c -@@ -40,6 +40,11 @@ static const u32 reg_offset_data_kpss[] - [WDT_BITE_TIME] = 0x14, - }; - -+struct qcom_wdt_match_data { -+ const u32 *offset; -+ bool pretimeout; -+}; -+ - struct qcom_wdt { - struct watchdog_device wdd; - unsigned long rate; -@@ -179,19 +184,29 @@ static void qcom_clk_disable_unprepare(v - clk_disable_unprepare(data); - } - -+static const struct qcom_wdt_match_data match_data_apcs_tmr = { -+ .offset = reg_offset_data_apcs_tmr, -+ .pretimeout = false, -+}; -+ -+static const struct qcom_wdt_match_data match_data_kpss = { -+ .offset = reg_offset_data_kpss, -+ .pretimeout = true, -+}; -+ - static int qcom_wdt_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; - struct qcom_wdt *wdt; - struct resource *res; - struct device_node *np = dev->of_node; -- const u32 *regs; -+ const struct qcom_wdt_match_data *data; - u32 percpu_offset; - int irq, ret; - struct clk *clk; - -- regs = of_device_get_match_data(dev); -- if (!regs) { -+ data = of_device_get_match_data(dev); -+ if (!data) { - dev_err(dev, "Unsupported QCOM WDT module\n"); - return -ENODEV; - } -@@ -247,7 +262,7 @@ static int qcom_wdt_probe(struct platfor - - /* check if there is pretimeout support */ - irq = platform_get_irq_optional(pdev, 0); -- if (irq > 0) { -+ if (data->pretimeout && irq > 0) { - ret = devm_request_irq(dev, irq, qcom_wdt_isr, - IRQF_TRIGGER_RISING, - "wdt_bark", &wdt->wdd); -@@ -267,7 +282,7 @@ static int qcom_wdt_probe(struct platfor - wdt->wdd.min_timeout = 1; - wdt->wdd.max_timeout = 0x10000000U / wdt->rate; - wdt->wdd.parent = dev; -- wdt->layout = regs; -+ wdt->layout = data->offset; - - if (readl(wdt_addr(wdt, WDT_STS)) & 1) - wdt->wdd.bootstatus = WDIOF_CARDRESET; -@@ -311,9 +326,9 @@ static int __maybe_unused qcom_wdt_resum - static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume); - - static const struct of_device_id qcom_wdt_of_table[] = { -- { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr }, -- { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr }, -- { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss }, -+ { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr }, -+ { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr }, -+ { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss }, - { }, - }; - MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); diff --git a/target/linux/ipq806x/patches-5.10/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch b/target/linux/ipq806x/patches-5.10/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch deleted file mode 100644 index 015a917e20..0000000000 --- a/target/linux/ipq806x/patches-5.10/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001 -From: Abhishek Sahu <absahu@codeaurora.org> -Date: Wed, 18 Mar 2020 14:16:56 +0100 -Subject: ipq806x: gcc: Added the enable regs and mask for PRNG - -Kernel got hanged while reading from /dev/hwrng at the -time of PRNG clock enable - -Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" -Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com -Signed-off-by: Stephen Boyd <sboyd@kernel.org> ---- - drivers/clk/qcom/gcc-ipq806x.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -1225,6 +1225,8 @@ static struct clk_rcg prng_src = { - .parent_map = gcc_pxo_pll8_map, - }, - .clkr = { -+ .enable_reg = 0x2e80, -+ .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "prng_src", - .parent_names = gcc_pxo_pll8, diff --git a/target/linux/ipq806x/patches-5.10/090-v5.8-clk-clk-rpm-fixes.patch b/target/linux/ipq806x/patches-5.10/090-v5.8-clk-clk-rpm-fixes.patch deleted file mode 100644 index a28570974e..0000000000 --- a/target/linux/ipq806x/patches-5.10/090-v5.8-clk-clk-rpm-fixes.patch +++ /dev/null @@ -1,90 +0,0 @@ -From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Tue, 10 Mar 2020 15:37:56 +0100 -Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x - -Add missing definition of rpm clk for ipq806x soc - -Signed-off-by: John Crispin <john@phrozen.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Acked-by: John Crispin <john@phrozen.org> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com -Signed-off-by: Stephen Boyd <sboyd@kernel.org> ---- - .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + - drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++ - include/dt-bindings/clock/qcom,rpmcc.h | 4 +++ - 3 files changed, 40 insertions(+) - ---- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt -+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt -@@ -15,6 +15,7 @@ Required properties : - "qcom,rpmcc-msm8916", "qcom,rpmcc" - "qcom,rpmcc-msm8974", "qcom,rpmcc" - "qcom,rpmcc-apq8064", "qcom,rpmcc" -+ "qcom,rpmcc-ipq806x", "qcom,rpmcc" - "qcom,rpmcc-msm8996", "qcom,rpmcc" - "qcom,rpmcc-msm8998", "qcom,rpmcc" - "qcom,rpmcc-qcs404", "qcom,rpmcc" ---- a/drivers/clk/qcom/clk-rpm.c -+++ b/drivers/clk/qcom/clk-rpm.c -@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk - .num_clks = ARRAY_SIZE(apq8064_clks), - }; - -+/* ipq806x */ -+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -+DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -+DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK); -+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK); -+ -+static struct clk_rpm *ipq806x_clks[] = { -+ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk, -+ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk, -+ [RPM_CFPB_CLK] = &ipq806x_cfpb_clk, -+ [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk, -+ [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk, -+ [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk, -+ [RPM_EBI1_CLK] = &ipq806x_ebi1_clk, -+ [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk, -+ [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk, -+ [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk, -+ [RPM_SFPB_CLK] = &ipq806x_sfpb_clk, -+ [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk, -+ [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk, -+ [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk, -+ [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk, -+ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk, -+}; -+ -+static const struct rpm_clk_desc rpm_clk_ipq806x = { -+ .clks = ipq806x_clks, -+ .num_clks = ARRAY_SIZE(ipq806x_clks), -+}; -+ - static const struct of_device_id rpm_clk_match_table[] = { - { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 }, - { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 }, - { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 }, -+ { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x }, - { } - }; - MODULE_DEVICE_TABLE(of, rpm_clk_match_table); ---- a/include/dt-bindings/clock/qcom,rpmcc.h -+++ b/include/dt-bindings/clock/qcom,rpmcc.h -@@ -37,6 +37,10 @@ - #define RPM_XO_A0 27 - #define RPM_XO_A1 28 - #define RPM_XO_A2 29 -+#define RPM_NSS_FABRIC_0_CLK 30 -+#define RPM_NSS_FABRIC_0_A_CLK 31 -+#define RPM_NSS_FABRIC_1_CLK 32 -+#define RPM_NSS_FABRIC_1_A_CLK 33 - - /* SMD RPM clocks */ - #define RPM_SMD_XO_CLK_SRC 0 diff --git a/target/linux/ipq806x/patches-5.10/091-v5.8-regulator-add-smb208-support.patch b/target/linux/ipq806x/patches-5.10/091-v5.8-regulator-add-smb208-support.patch deleted file mode 100644 index 42a02865a3..0000000000 --- a/target/linux/ipq806x/patches-5.10/091-v5.8-regulator-add-smb208-support.patch +++ /dev/null @@ -1,63 +0,0 @@ -From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Wed, 19 Feb 2020 17:37:11 +0100 -Subject: regulator: add smb208 support - -Smb208 regulators are used on some ipq806x soc. -Add support for it to make it avaiable on some routers -that use it. - -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Adrian Panella <ianchi74@outlook.com> -Acked-by: Lee Jones <lee.jones@linaro.org> -Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com -Signed-off-by: Mark Brown <broonie@kernel.org> ---- - Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++ - drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++ - 2 files changed, 13 insertions(+) - ---- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt -+++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt -@@ -61,6 +61,7 @@ Regulator nodes are identified by their - "qcom,rpm-pm8901-regulators" - "qcom,rpm-pm8921-regulators" - "qcom,rpm-pm8018-regulators" -+ "qcom,rpm-smb208-regulators" - - - vdd_l0_l1_lvs-supply: - - vdd_l2_l11_l12-supply: -@@ -171,6 +172,9 @@ pm8018: - s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, lvs1 - -+smb208: -+ s1a, s1b, s2a, s2b -+ - The content of each sub-node is defined by the standard binding for regulators - - see regulator.txt - with additional custom properties described below: - ---- a/drivers/regulator/qcom_rpm-regulator.c -+++ b/drivers/regulator/qcom_rpm-regulator.c -@@ -925,12 +925,21 @@ static const struct rpm_regulator_data r - { } - }; - -+static const struct rpm_regulator_data rpm_smb208_regulators[] = { -+ { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" }, -+ { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" }, -+ { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" }, -+ { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" }, -+ { } -+}; -+ - static const struct of_device_id rpm_of_match[] = { - { .compatible = "qcom,rpm-pm8018-regulators", - .data = &rpm_pm8018_regulators }, - { .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators }, - { .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators }, - { .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators }, -+ { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators }, - { } - }; - MODULE_DEVICE_TABLE(of, rpm_of_match); diff --git a/target/linux/ipq806x/patches-5.10/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch b/target/linux/ipq806x/patches-5.10/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch deleted file mode 100644 index be20756a10..0000000000 --- a/target/linux/ipq806x/patches-5.10/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch +++ /dev/null @@ -1,361 +0,0 @@ -From a8811ec764f95a04ba82f6f457e28c5e9e36e36b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Fri, 13 Mar 2020 18:52:13 +0100 -Subject: cpufreq: qcom: Add support for krait based socs - -In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974 -that has KRAIT processors the voltage/current value of each OPP -varies based on the silicon variant in use. - -The required OPP related data is determined based on -the efuse value. This is similar to the existing code for -kryo cores. So adding support for krait cores here. - -Signed-off-by: Sricharan R <sricharan@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> ---- - .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +- - drivers/cpufreq/Kconfig.arm | 2 +- - drivers/cpufreq/cpufreq-dt-platdev.c | 5 + - drivers/cpufreq/qcom-cpufreq-nvmem.c | 191 +++++++++++++++++++-- - 4 files changed, 183 insertions(+), 18 deletions(-) - ---- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt -+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt -@@ -19,7 +19,8 @@ In 'cpu' nodes: - - In 'operating-points-v2' table: - - compatible: Should be -- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. -+ - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974, -+ apq8064, ipq8064, msm8960 and ipq8074. - - Optional properties: - -------------------- ---- a/drivers/cpufreq/Kconfig.arm -+++ b/drivers/cpufreq/Kconfig.arm -@@ -135,7 +135,7 @@ config ARM_OMAP2PLUS_CPUFREQ - - config ARM_QCOM_CPUFREQ_NVMEM - tristate "Qualcomm nvmem based CPUFreq" -- depends on ARM64 -+ depends on ARCH_QCOM - depends on QCOM_QFPROM - depends on QCOM_SMEM - select PM_OPP ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -138,6 +138,11 @@ static const struct of_device_id blackli - { .compatible = "ti,am43", }, - { .compatible = "ti,dra7", }, - -+ { .compatible = "qcom,ipq8064", }, -+ { .compatible = "qcom,apq8064", }, -+ { .compatible = "qcom,msm8974", }, -+ { .compatible = "qcom,msm8960", }, -+ - { } - }; - ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -49,12 +49,14 @@ struct qcom_cpufreq_drv; - struct qcom_cpufreq_match_data { - int (*get_version)(struct device *cpu_dev, - struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, - struct qcom_cpufreq_drv *drv); - const char **genpd_names; - }; - - struct qcom_cpufreq_drv { -- struct opp_table **opp_tables; -+ struct opp_table **names_opp_tables; -+ struct opp_table **hw_opp_tables; - struct opp_table **genpd_opp_tables; - u32 versions; - const struct qcom_cpufreq_match_data *data; -@@ -62,6 +64,84 @@ struct qcom_cpufreq_drv { - - static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; - -+static void get_krait_bin_format_a(struct device *cpu_dev, -+ int *speed, int *pvs, int *pvs_ver, -+ struct nvmem_cell *pvs_nvmem, u8 *buf) -+{ -+ u32 pte_efuse; -+ -+ pte_efuse = *((u32 *)buf); -+ -+ *speed = pte_efuse & 0xf; -+ if (*speed == 0xf) -+ *speed = (pte_efuse >> 4) & 0xf; -+ -+ if (*speed == 0xf) { -+ *speed = 0; -+ dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed); -+ } else { -+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); -+ } -+ -+ *pvs = (pte_efuse >> 10) & 0x7; -+ if (*pvs == 0x7) -+ *pvs = (pte_efuse >> 13) & 0x7; -+ -+ if (*pvs == 0x7) { -+ *pvs = 0; -+ dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs); -+ } else { -+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); -+ } -+} -+ -+static void get_krait_bin_format_b(struct device *cpu_dev, -+ int *speed, int *pvs, int *pvs_ver, -+ struct nvmem_cell *pvs_nvmem, u8 *buf) -+{ -+ u32 pte_efuse, redundant_sel; -+ -+ pte_efuse = *((u32 *)buf); -+ redundant_sel = (pte_efuse >> 24) & 0x7; -+ -+ *pvs_ver = (pte_efuse >> 4) & 0x3; -+ -+ switch (redundant_sel) { -+ case 1: -+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); -+ *speed = (pte_efuse >> 27) & 0xf; -+ break; -+ case 2: -+ *pvs = (pte_efuse >> 27) & 0xf; -+ *speed = pte_efuse & 0x7; -+ break; -+ default: -+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */ -+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); -+ *speed = pte_efuse & 0x7; -+ } -+ -+ /* Check SPEED_BIN_BLOW_STATUS */ -+ if (pte_efuse & BIT(3)) { -+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); -+ } else { -+ dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n"); -+ *speed = 0; -+ } -+ -+ /* Check PVS_BLOW_STATUS */ -+ pte_efuse = *(((u32 *)buf) + 4); -+ pte_efuse &= BIT(21); -+ if (pte_efuse) { -+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); -+ } else { -+ dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n"); -+ *pvs = 0; -+ } -+ -+ dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); -+} -+ - static enum _msm8996_version qcom_cpufreq_get_msm_id(void) - { - size_t len; -@@ -93,11 +173,13 @@ static enum _msm8996_version qcom_cpufre - - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, - struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, - struct qcom_cpufreq_drv *drv) - { - size_t len; - u8 *speedbin; - enum _msm8996_version msm8996_version; -+ *pvs_name = NULL; - - msm8996_version = qcom_cpufreq_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { -@@ -125,10 +207,51 @@ static int qcom_cpufreq_kryo_name_versio - return 0; - } - -+static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, -+ struct nvmem_cell *speedbin_nvmem, -+ char **pvs_name, -+ struct qcom_cpufreq_drv *drv) -+{ -+ int speed = 0, pvs = 0, pvs_ver = 0; -+ u8 *speedbin; -+ size_t len; -+ -+ speedbin = nvmem_cell_read(speedbin_nvmem, &len); -+ -+ if (IS_ERR(speedbin)) -+ return PTR_ERR(speedbin); -+ -+ switch (len) { -+ case 4: -+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, -+ speedbin_nvmem, speedbin); -+ break; -+ case 8: -+ get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver, -+ speedbin_nvmem, speedbin); -+ break; -+ default: -+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); -+ return -ENODEV; -+ } -+ -+ snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d", -+ speed, pvs, pvs_ver); -+ -+ drv->versions = (1 << speed); -+ -+ kfree(speedbin); -+ return 0; -+} -+ - static const struct qcom_cpufreq_match_data match_data_kryo = { - .get_version = qcom_cpufreq_kryo_name_version, - }; - -+static const struct qcom_cpufreq_match_data match_data_krait = { -+ .get_version = qcom_cpufreq_krait_name_version, -+}; -+ - static const char *qcs404_genpd_names[] = { "cpr", NULL }; - - static const struct qcom_cpufreq_match_data match_data_qcs404 = { -@@ -141,6 +264,7 @@ static int qcom_cpufreq_probe(struct pla - struct nvmem_cell *speedbin_nvmem; - struct device_node *np; - struct device *cpu_dev; -+ char *pvs_name = "speedXX-pvsXX-vXX"; - unsigned cpu; - const struct of_device_id *match; - int ret; -@@ -153,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla - if (!np) - return -ENOENT; - -- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); -+ ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu"); - if (!ret) { - of_node_put(np); - return -ENOENT; -@@ -181,7 +305,8 @@ static int qcom_cpufreq_probe(struct pla - goto free_drv; - } - -- ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv); -+ ret = drv->data->get_version(cpu_dev, -+ speedbin_nvmem, &pvs_name, drv); - if (ret) { - nvmem_cell_put(speedbin_nvmem); - goto free_drv; -@@ -190,12 +315,20 @@ static int qcom_cpufreq_probe(struct pla - } - of_node_put(np); - -- drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables), -+ drv->names_opp_tables = kcalloc(num_possible_cpus(), -+ sizeof(*drv->names_opp_tables), - GFP_KERNEL); -- if (!drv->opp_tables) { -+ if (!drv->names_opp_tables) { - ret = -ENOMEM; - goto free_drv; - } -+ drv->hw_opp_tables = kcalloc(num_possible_cpus(), -+ sizeof(*drv->hw_opp_tables), -+ GFP_KERNEL); -+ if (!drv->hw_opp_tables) { -+ ret = -ENOMEM; -+ goto free_opp_names; -+ } - - drv->genpd_opp_tables = kcalloc(num_possible_cpus(), - sizeof(*drv->genpd_opp_tables), -@@ -213,11 +346,23 @@ static int qcom_cpufreq_probe(struct pla - } - - if (drv->data->get_version) { -- drv->opp_tables[cpu] = -- dev_pm_opp_set_supported_hw(cpu_dev, -- &drv->versions, 1); -- if (IS_ERR(drv->opp_tables[cpu])) { -- ret = PTR_ERR(drv->opp_tables[cpu]); -+ -+ if (pvs_name) { -+ drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name( -+ cpu_dev, -+ pvs_name); -+ if (IS_ERR(drv->names_opp_tables[cpu])) { -+ ret = PTR_ERR(drv->names_opp_tables[cpu]); -+ dev_err(cpu_dev, "Failed to add OPP name %s\n", -+ pvs_name); -+ goto free_opp; -+ } -+ } -+ -+ drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw( -+ cpu_dev, &drv->versions, 1); -+ if (IS_ERR(drv->hw_opp_tables[cpu])) { -+ ret = PTR_ERR(drv->hw_opp_tables[cpu]); - dev_err(cpu_dev, - "Failed to set supported hardware\n"); - goto free_genpd_opp; -@@ -259,11 +404,18 @@ free_genpd_opp: - kfree(drv->genpd_opp_tables); - free_opp: - for_each_possible_cpu(cpu) { -- if (IS_ERR_OR_NULL(drv->opp_tables[cpu])) -+ if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu])) -+ break; -+ dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]); -+ } -+ for_each_possible_cpu(cpu) { -+ if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu])) - break; -- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); -+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]); - } -- kfree(drv->opp_tables); -+ kfree(drv->hw_opp_tables); -+free_opp_names: -+ kfree(drv->names_opp_tables); - free_drv: - kfree(drv); - -@@ -278,13 +430,16 @@ static int qcom_cpufreq_remove(struct pl - platform_device_unregister(cpufreq_dt_pdev); - - for_each_possible_cpu(cpu) { -- if (drv->opp_tables[cpu]) -- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]); -+ if (drv->names_opp_tables[cpu]) -+ dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]); -+ if (drv->hw_opp_tables[cpu]) -+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]); - if (drv->genpd_opp_tables[cpu]) - dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); - } - -- kfree(drv->opp_tables); -+ kfree(drv->names_opp_tables); -+ kfree(drv->hw_opp_tables); - kfree(drv->genpd_opp_tables); - kfree(drv); - -@@ -303,6 +458,10 @@ static const struct of_device_id qcom_cp - { .compatible = "qcom,apq8096", .data = &match_data_kryo }, - { .compatible = "qcom,msm8996", .data = &match_data_kryo }, - { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, -+ { .compatible = "qcom,ipq8064", .data = &match_data_krait }, -+ { .compatible = "qcom,apq8064", .data = &match_data_krait }, -+ { .compatible = "qcom,msm8974", .data = &match_data_krait }, -+ { .compatible = "qcom,msm8960", .data = &match_data_krait }, - {}, - }; - MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); diff --git a/target/linux/ipq806x/patches-5.10/092-2-v5.7-cpufreq-qcom-fix-wrong-compatible-binding.patch b/target/linux/ipq806x/patches-5.10/092-2-v5.7-cpufreq-qcom-fix-wrong-compatible-binding.patch deleted file mode 100644 index 764a917c1f..0000000000 --- a/target/linux/ipq806x/patches-5.10/092-2-v5.7-cpufreq-qcom-fix-wrong-compatible-binding.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2dea651680cea1f3a29925de51002f33d1f55711 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Fri, 1 May 2020 00:22:25 +0200 -Subject: cpufreq: qcom: fix wrong compatible binding - -Binding in Documentation is still "operating-points-v2-kryo-cpu". -Restore the old binding to fix the compatibility problem. - -Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs") -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> ---- - drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -277,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla - if (!np) - return -ENOENT; - -- ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu"); -+ ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); - if (!ret) { - of_node_put(np); - return -ENOENT; diff --git a/target/linux/ipq806x/patches-5.10/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch b/target/linux/ipq806x/patches-5.10/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch deleted file mode 100644 index 95531508b6..0000000000 --- a/target/linux/ipq806x/patches-5.10/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch +++ /dev/null @@ -1,228 +0,0 @@ -From 6a114526af4689938863bf34976c83bfd279f517 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Mon, 15 Jun 2020 23:06:02 +0200 -Subject: PCI: qcom: Use bulk clk api and assert on error - -Rework 2.1.0 revision to use bulk clk api and fix missing assert on -reset_control_deassert error. - -Link: https://lore.kernel.org/r/20200615210608.21469-7-ansuelsmth@gmail.com -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> ---- - drivers/pci/controller/dwc/pcie-qcom.c | 131 ++++++++++++--------------------- - 1 file changed, 46 insertions(+), 85 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -99,12 +99,9 @@ - #define SLV_ADDR_SPACE_SZ 0x10000000 - - #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 -+#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 - struct qcom_pcie_resources_2_1_0 { -- struct clk *iface_clk; -- struct clk *core_clk; -- struct clk *phy_clk; -- struct clk *aux_clk; -- struct clk *ref_clk; -+ struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; - struct reset_control *pci_reset; - struct reset_control *axi_reset; - struct reset_control *ahb_reset; -@@ -244,25 +241,21 @@ static int qcom_pcie_get_resources_2_1_0 - if (ret) - return ret; - -- res->iface_clk = devm_clk_get(dev, "iface"); -- if (IS_ERR(res->iface_clk)) -- return PTR_ERR(res->iface_clk); -- -- res->core_clk = devm_clk_get(dev, "core"); -- if (IS_ERR(res->core_clk)) -- return PTR_ERR(res->core_clk); -- -- res->phy_clk = devm_clk_get(dev, "phy"); -- if (IS_ERR(res->phy_clk)) -- return PTR_ERR(res->phy_clk); -- -- res->aux_clk = devm_clk_get_optional(dev, "aux"); -- if (IS_ERR(res->aux_clk)) -- return PTR_ERR(res->aux_clk); -- -- res->ref_clk = devm_clk_get_optional(dev, "ref"); -- if (IS_ERR(res->ref_clk)) -- return PTR_ERR(res->ref_clk); -+ res->clks[0].id = "iface"; -+ res->clks[1].id = "core"; -+ res->clks[2].id = "phy"; -+ res->clks[3].id = "aux"; -+ res->clks[4].id = "ref"; -+ -+ /* iface, core, phy are required */ -+ ret = devm_clk_bulk_get(dev, 3, res->clks); -+ if (ret < 0) -+ return ret; -+ -+ /* aux, ref are optional */ -+ ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); -+ if (ret < 0) -+ return ret; - - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) -@@ -292,17 +285,13 @@ static void qcom_pcie_deinit_2_1_0(struc - { - struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - -- clk_disable_unprepare(res->phy_clk); -+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); - reset_control_assert(res->pci_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); - reset_control_assert(res->ext_reset); - reset_control_assert(res->phy_reset); -- clk_disable_unprepare(res->iface_clk); -- clk_disable_unprepare(res->core_clk); -- clk_disable_unprepare(res->aux_clk); -- clk_disable_unprepare(res->ref_clk); - - writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); - -@@ -334,47 +323,45 @@ static int qcom_pcie_init_2_1_0(struct q - return ret; - } - -- ret = reset_control_assert(res->ahb_reset); -+ ret = reset_control_deassert(res->ahb_reset); - if (ret) { -- dev_err(dev, "cannot assert ahb reset\n"); -- goto err_assert_ahb; -+ dev_err(dev, "cannot deassert ahb reset\n"); -+ goto err_deassert_ahb; - } - -- ret = clk_prepare_enable(res->iface_clk); -+ ret = reset_control_deassert(res->ext_reset); - if (ret) { -- dev_err(dev, "cannot prepare/enable iface clock\n"); -- goto err_assert_ahb; -+ dev_err(dev, "cannot deassert ext reset\n"); -+ goto err_deassert_ext; - } - -- ret = clk_prepare_enable(res->core_clk); -+ ret = reset_control_deassert(res->phy_reset); - if (ret) { -- dev_err(dev, "cannot prepare/enable core clock\n"); -- goto err_clk_core; -+ dev_err(dev, "cannot deassert phy reset\n"); -+ goto err_deassert_phy; - } - -- ret = clk_prepare_enable(res->aux_clk); -+ ret = reset_control_deassert(res->pci_reset); - if (ret) { -- dev_err(dev, "cannot prepare/enable aux clock\n"); -- goto err_clk_aux; -+ dev_err(dev, "cannot deassert pci reset\n"); -+ goto err_deassert_pci; - } - -- ret = clk_prepare_enable(res->ref_clk); -+ ret = reset_control_deassert(res->por_reset); - if (ret) { -- dev_err(dev, "cannot prepare/enable ref clock\n"); -- goto err_clk_ref; -+ dev_err(dev, "cannot deassert por reset\n"); -+ goto err_deassert_por; - } - -- ret = reset_control_deassert(res->ahb_reset); -+ ret = reset_control_deassert(res->axi_reset); - if (ret) { -- dev_err(dev, "cannot deassert ahb reset\n"); -- goto err_deassert_ahb; -+ dev_err(dev, "cannot deassert axi reset\n"); -+ goto err_deassert_axi; - } - -- ret = reset_control_deassert(res->ext_reset); -- if (ret) { -- dev_err(dev, "cannot deassert ext reset\n"); -- goto err_deassert_ahb; -- } -+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); -+ if (ret) -+ goto err_clks; - - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); -@@ -406,36 +393,6 @@ static int qcom_pcie_init_2_1_0(struct q - val |= PHY_REFCLK_SSP_EN; - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); - -- ret = reset_control_deassert(res->phy_reset); -- if (ret) { -- dev_err(dev, "cannot deassert phy reset\n"); -- return ret; -- } -- -- ret = reset_control_deassert(res->pci_reset); -- if (ret) { -- dev_err(dev, "cannot deassert pci reset\n"); -- return ret; -- } -- -- ret = reset_control_deassert(res->por_reset); -- if (ret) { -- dev_err(dev, "cannot deassert por reset\n"); -- return ret; -- } -- -- ret = reset_control_deassert(res->axi_reset); -- if (ret) { -- dev_err(dev, "cannot deassert axi reset\n"); -- return ret; -- } -- -- ret = clk_prepare_enable(res->phy_clk); -- if (ret) { -- dev_err(dev, "cannot prepare/enable phy clock\n"); -- goto err_deassert_ahb; -- } -- - /* wait for clock acquisition */ - usleep_range(1000, 1500); - -@@ -448,15 +405,19 @@ static int qcom_pcie_init_2_1_0(struct q - - return 0; - -+err_clks: -+ reset_control_assert(res->axi_reset); -+err_deassert_axi: -+ reset_control_assert(res->por_reset); -+err_deassert_por: -+ reset_control_assert(res->pci_reset); -+err_deassert_pci: -+ reset_control_assert(res->phy_reset); -+err_deassert_phy: -+ reset_control_assert(res->ext_reset); -+err_deassert_ext: -+ reset_control_assert(res->ahb_reset); - err_deassert_ahb: -- clk_disable_unprepare(res->ref_clk); --err_clk_ref: -- clk_disable_unprepare(res->aux_clk); --err_clk_aux: -- clk_disable_unprepare(res->core_clk); --err_clk_core: -- clk_disable_unprepare(res->iface_clk); --err_assert_ahb: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; diff --git a/target/linux/ipq806x/patches-5.10/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch b/target/linux/ipq806x/patches-5.10/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch deleted file mode 100644 index c3d61f164c..0000000000 --- a/target/linux/ipq806x/patches-5.10/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 8df093fe2ae1717389df0dcdc620c02cc35abb21 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Mon, 15 Jun 2020 23:06:05 +0200 -Subject: PCI: qcom: Add ipq8064 rev2 variant - -Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit -different offset based on the revision. - -Link: https://lore.kernel.org/r/20200615210608.21469-10-ansuelsmth@gmail.com -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> ---- - drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -368,7 +368,8 @@ static int qcom_pcie_init_2_1_0(struct q - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - -- if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { -+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || -+ of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { - writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | - PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | - PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), -@@ -1328,6 +1329,7 @@ err_pm_runtime_put: - static const struct of_device_id qcom_pcie_match[] = { - { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, - { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, -+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, - { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, - { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, - { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, diff --git a/target/linux/ipq806x/patches-5.10/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch b/target/linux/ipq806x/patches-5.10/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch deleted file mode 100644 index 02ac7460e8..0000000000 --- a/target/linux/ipq806x/patches-5.10/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 51ed2c2b60265006bde7531d10993cf24def0aee Mon Sep 17 00:00:00 2001 -From: Sham Muthayyan <smuthayy@codeaurora.org> -Date: Mon, 15 Jun 2020 23:06:07 +0200 -Subject: PCI: qcom: Support pci speed set for ipq806x - -Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to -some hardware limitations. Add support for speed setting defined by the -max-link-speed binding. If not defined the max speed is set to GEN2 by -default. - -Link: https://lore.kernel.org/r/20200615210608.21469-12-ansuelsmth@gmail.com -Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> ---- - -Backported with light changes: -* One include is missing in kernel 5.4 - - drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -27,6 +27,7 @@ - #include <linux/slab.h> - #include <linux/types.h> - -+#include "../../pci.h" - #include "pcie-designware.h" - - #define PCIE20_PARF_SYS_CTRL 0x00 -@@ -98,6 +99,8 @@ - #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 - #define SLV_ADDR_SPACE_SZ 0x10000000 - -+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 -+ - #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 - #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 - struct qcom_pcie_resources_2_1_0 { -@@ -184,6 +187,7 @@ struct qcom_pcie { - struct phy *phy; - struct gpio_desc *reset; - const struct qcom_pcie_ops *ops; -+ int gen; - }; - - #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) -@@ -397,6 +401,11 @@ static int qcom_pcie_init_2_1_0(struct q - /* wait for clock acquisition */ - usleep_range(1000, 1500); - -+ if (pcie->gen == 1) { -+ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); -+ val |= PCI_EXP_LNKSTA_CLS_2_5GB; -+ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); -+ } - - /* Set the Max TLP size to 2K, instead of using default of 4K */ - writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, -@@ -1261,6 +1270,10 @@ static int qcom_pcie_probe(struct platfo - goto err_pm_runtime_put; - } - -+ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node); -+ if (pcie->gen < 0) -+ pcie->gen = 2; -+ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); - pcie->parf = devm_ioremap_resource(dev, res); - if (IS_ERR(pcie->parf)) { diff --git a/target/linux/ipq806x/patches-5.10/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch b/target/linux/ipq806x/patches-5.10/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch deleted file mode 100644 index 328942dad9..0000000000 --- a/target/linux/ipq806x/patches-5.10/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch +++ /dev/null @@ -1,216 +0,0 @@ -From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Wed, 4 Mar 2020 22:38:32 +0100 -Subject: net: mdio: add ipq8064 mdio driver - -Currently ipq806x soc use generic bitbang driver to -comunicate with the gmac ethernet interface. -Add a dedicated driver created by chunkeey to fix this. - -Co-developed-by: Christian Lamparter <chunkeey@gmail.com> -Signed-off-by: Christian Lamparter <chunkeey@gmail.com> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: David S. Miller <davem@davemloft.net> ---- - drivers/net/phy/Kconfig | 8 ++ - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 175 insertions(+) - create mode 100644 drivers/net/phy/mdio-ipq8064.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -156,6 +156,14 @@ config MDIO_I2C - - This is library mode. - -+config MDIO_IPQ8064 -+ tristate "Qualcomm IPQ8064 MDIO interface support" -+ depends on HAS_IOMEM && OF_MDIO -+ depends on MFD_SYSCON -+ help -+ This driver supports the MDIO interface found in the network -+ interface units of the IPQ8064 SoC -+ - config MDIO_MOXART - tristate "MOXA ART MDIO interface support" - depends on ARCH_MOXART || COMPILE_TEST ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -50,6 +50,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium - obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o - obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o - obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o -+obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o - obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o - obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o ---- /dev/null -+++ b/drivers/net/phy/mdio-ipq8064.c -@@ -0,0 +1,166 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Qualcomm IPQ8064 MDIO interface driver -+ * -+ * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com> -+ * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com> -+ */ -+ -+#include <linux/delay.h> -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/regmap.h> -+#include <linux/of_mdio.h> -+#include <linux/phy.h> -+#include <linux/platform_device.h> -+#include <linux/mfd/syscon.h> -+ -+/* MII address register definitions */ -+#define MII_ADDR_REG_ADDR 0x10 -+#define MII_BUSY BIT(0) -+#define MII_WRITE BIT(1) -+#define MII_CLKRANGE_60_100M (0 << 2) -+#define MII_CLKRANGE_100_150M (1 << 2) -+#define MII_CLKRANGE_20_35M (2 << 2) -+#define MII_CLKRANGE_35_60M (3 << 2) -+#define MII_CLKRANGE_150_250M (4 << 2) -+#define MII_CLKRANGE_250_300M (5 << 2) -+#define MII_CLKRANGE_MASK GENMASK(4, 2) -+#define MII_REG_SHIFT 6 -+#define MII_REG_MASK GENMASK(10, 6) -+#define MII_ADDR_SHIFT 11 -+#define MII_ADDR_MASK GENMASK(15, 11) -+ -+#define MII_DATA_REG_ADDR 0x14 -+ -+#define MII_MDIO_DELAY_USEC (1000) -+#define MII_MDIO_RETRY_MSEC (10) -+ -+struct ipq8064_mdio { -+ struct regmap *base; /* NSS_GMAC0_BASE */ -+}; -+ -+static int -+ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv) -+{ -+ u32 busy; -+ -+ return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy, -+ !(busy & MII_BUSY), MII_MDIO_DELAY_USEC, -+ MII_MDIO_RETRY_MSEC * USEC_PER_MSEC); -+} -+ -+static int -+ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) -+{ -+ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M; -+ struct ipq8064_mdio *priv = bus->priv; -+ u32 ret_val; -+ int err; -+ -+ /* Reject clause 45 */ -+ if (reg_offset & MII_ADDR_C45) -+ return -EOPNOTSUPP; -+ -+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | -+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); -+ -+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); -+ usleep_range(8, 10); -+ -+ err = ipq8064_mdio_wait_busy(priv); -+ if (err) -+ return err; -+ -+ regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); -+ return (int)ret_val; -+} -+ -+static int -+ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) -+{ -+ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M; -+ struct ipq8064_mdio *priv = bus->priv; -+ -+ /* Reject clause 45 */ -+ if (reg_offset & MII_ADDR_C45) -+ return -EOPNOTSUPP; -+ -+ regmap_write(priv->base, MII_DATA_REG_ADDR, data); -+ -+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | -+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); -+ -+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); -+ usleep_range(8, 10); -+ -+ return ipq8064_mdio_wait_busy(priv); -+} -+ -+static int -+ipq8064_mdio_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct ipq8064_mdio *priv; -+ struct mii_bus *bus; -+ int ret; -+ -+ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); -+ if (!bus) -+ return -ENOMEM; -+ -+ bus->name = "ipq8064_mdio_bus"; -+ bus->read = ipq8064_mdio_read; -+ bus->write = ipq8064_mdio_write; -+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); -+ bus->parent = &pdev->dev; -+ -+ priv = bus->priv; -+ priv->base = device_node_to_regmap(np); -+ if (IS_ERR(priv->base)) { -+ if (priv->base == ERR_PTR(-EPROBE_DEFER)) -+ return -EPROBE_DEFER; -+ -+ dev_err(&pdev->dev, "error getting device regmap, error=%pe\n", -+ priv->base); -+ return PTR_ERR(priv->base); -+ } -+ -+ ret = of_mdiobus_register(bus, np); -+ if (ret) -+ return ret; -+ -+ platform_set_drvdata(pdev, bus); -+ return 0; -+} -+ -+static int -+ipq8064_mdio_remove(struct platform_device *pdev) -+{ -+ struct mii_bus *bus = platform_get_drvdata(pdev); -+ -+ mdiobus_unregister(bus); -+ -+ return 0; -+} -+ -+static const struct of_device_id ipq8064_mdio_dt_ids[] = { -+ { .compatible = "qcom,ipq8064-mdio" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids); -+ -+static struct platform_driver ipq8064_mdio_driver = { -+ .probe = ipq8064_mdio_probe, -+ .remove = ipq8064_mdio_remove, -+ .driver = { -+ .name = "ipq8064-mdio", -+ .of_match_table = ipq8064_mdio_dt_ids, -+ }, -+}; -+ -+module_platform_driver(ipq8064_mdio_driver); -+ -+MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver"); -+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>"); -+MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ipq806x/patches-5.10/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch b/target/linux/ipq806x/patches-5.10/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch deleted file mode 100644 index 47dc455715..0000000000 --- a/target/linux/ipq806x/patches-5.10/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch +++ /dev/null @@ -1,621 +0,0 @@ -From ef19b117b83466e1c030368101a24367a34be7f0 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Fri, 17 Jul 2020 15:16:31 +0200 -Subject: phy: qualcomm: add qcom ipq806x dwc usb phy driver - -This has lost in the original push for the dwc3 qcom driver. -This is needed for ipq806x SoC as without this the usb ports -doesn't work at all. - -Signed-off-by: Andy Gross <agross@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Tested-by: Jonathan McDowell <noodles@earth.li> -Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com -Signed-off-by: Vinod Koul <vkoul@kernel.org> ---- - -Light modification to Kconfig as some config are missing in kernel 5.4 - - drivers/phy/qualcomm/Kconfig | 10 + - drivers/phy/qualcomm/Makefile | 1 + - drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 571 ++++++++++++++++++++++++++++ - 3 files changed, 582 insertions(+) - create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c - ---- a/drivers/phy/qualcomm/Kconfig -+++ b/drivers/phy/qualcomm/Kconfig -@@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC - select GENERIC_PHY - help - Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. -+ -+config PHY_QCOM_IPQ806X_USB -+ tristate "Qualcomm IPQ806x DWC3 USB PHY driver" -+ depends on HAS_IOMEM -+ depends on OF && (ARCH_QCOM || COMPILE_TEST) -+ select GENERIC_PHY -+ help -+ This option enables support for the Synopsis PHYs present inside the -+ Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports -+ both HS and SS PHY controllers. ---- a/drivers/phy/qualcomm/Makefile -+++ b/drivers/phy/qualcomm/Makefile -@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy- - obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o - obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o - obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o -+obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o ---- /dev/null -+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c -@@ -0,0 +1,571 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include <linux/clk.h> -+#include <linux/err.h> -+#include <linux/io.h> -+#include <linux/module.h> -+#include <linux/of_device.h> -+#include <linux/phy/phy.h> -+#include <linux/platform_device.h> -+#include <linux/delay.h> -+#include <linux/regmap.h> -+#include <linux/mfd/syscon.h> -+ -+/* USB QSCRATCH Hardware registers */ -+#define QSCRATCH_GENERAL_CFG (0x08) -+#define HSUSB_PHY_CTRL_REG (0x10) -+ -+/* PHY_CTRL_REG */ -+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24) -+#define HSUSB_CTRL_USB2_SUSPEND BIT(23) -+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) -+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) -+#define HSUSB_CTRL_USE_CLKCORE BIT(18) -+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17) -+#define HSUSB_CTRL_COMMONONN BIT(11) -+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) -+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8) -+#define HSUSB_CTRL_CLAMP_EN BIT(7) -+#define HSUSB_CTRL_RETENABLEN BIT(1) -+#define HSUSB_CTRL_POR BIT(0) -+ -+/* QSCRATCH_GENERAL_CFG */ -+#define HSUSB_GCFG_XHCI_REV BIT(2) -+ -+/* USB QSCRATCH Hardware registers */ -+#define SSUSB_PHY_CTRL_REG (0x00) -+#define SSUSB_PHY_PARAM_CTRL_1 (0x04) -+#define SSUSB_PHY_PARAM_CTRL_2 (0x08) -+#define CR_PROTOCOL_DATA_IN_REG (0x0c) -+#define CR_PROTOCOL_DATA_OUT_REG (0x10) -+#define CR_PROTOCOL_CAP_ADDR_REG (0x14) -+#define CR_PROTOCOL_CAP_DATA_REG (0x18) -+#define CR_PROTOCOL_READ_REG (0x1c) -+#define CR_PROTOCOL_WRITE_REG (0x20) -+ -+/* PHY_CTRL_REG */ -+#define SSUSB_CTRL_REF_USE_PAD BIT(28) -+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27) -+#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) -+#define SSUSB_CTRL_SS_PHY_EN BIT(8) -+#define SSUSB_CTRL_SS_PHY_RESET BIT(7) -+ -+/* SSPHY control registers - Does this need 0x30? */ -+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane)) -+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane)) -+ -+/* SSPHY SoC version specific values */ -+#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */ -+/* Override value for transmit preemphasis */ -+#define SSPHY_TX_DEEMPH_3_5DB 23 -+/* Override value for mpll */ -+#define SSPHY_MPLL_VALUE 0 -+ -+/* QSCRATCH PHY_PARAM_CTRL1 fields */ -+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19) -+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13) -+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7) -+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2) -+ -+#define PHY_PARAM_CTRL1_MASK \ -+ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \ -+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \ -+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \ -+ PHY_PARAM_CTRL1_LOS_BIAS_MASK) -+ -+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \ -+ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK) -+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \ -+ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK) -+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \ -+ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK) -+#define PHY_PARAM_CTRL1_LOS_BIAS(x) \ -+ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK) -+ -+/* RX OVRD IN HI bits */ -+#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13) -+#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12) -+#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) -+#define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7) -+#define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8) -+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7) -+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6) -+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5) -+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2) -+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2) -+#define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0) -+ -+/* TX OVRD DRV LO register bits */ -+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0) -+#define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6) -+#define TX_OVRD_DRV_LO_PREEMPH(x) ((x) << 7) -+#define TX_OVRD_DRV_LO_EN BIT(14) -+ -+/* MPLL bits */ -+#define SSPHY_MPLL_MASK GENMASK(8, 5) -+#define SSPHY_MPLL(x) ((x) << 5) -+ -+/* SS CAP register bits */ -+#define SS_CR_CAP_ADDR_REG BIT(0) -+#define SS_CR_CAP_DATA_REG BIT(0) -+#define SS_CR_READ_REG BIT(0) -+#define SS_CR_WRITE_REG BIT(0) -+ -+struct usb_phy { -+ void __iomem *base; -+ struct device *dev; -+ struct clk *xo_clk; -+ struct clk *ref_clk; -+ u32 rx_eq; -+ u32 tx_deamp_3_5db; -+ u32 mpll; -+}; -+ -+struct phy_drvdata { -+ struct phy_ops ops; -+ u32 clk_rate; -+}; -+ -+/** -+ * Write register and read back masked value to confirm it is written -+ * -+ * @base - QCOM DWC3 PHY base virtual address. -+ * @offset - register offset. -+ * @mask - register bitmask specifying what should be updated -+ * @val - value to write. -+ */ -+static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3, -+ u32 offset, -+ const u32 mask, u32 val) -+{ -+ u32 write_val, tmp = readl(phy_dwc3->base + offset); -+ -+ tmp &= ~mask; /* retain other bits */ -+ write_val = tmp | val; -+ -+ writel(write_val, phy_dwc3->base + offset); -+ -+ /* Read back to see if val was written */ -+ tmp = readl(phy_dwc3->base + offset); -+ tmp &= mask; /* clear other bits */ -+ -+ if (tmp != val) -+ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset); -+} -+ -+static int wait_for_latch(void __iomem *addr) -+{ -+ u32 retry = 10; -+ -+ while (true) { -+ if (!readl(addr)) -+ break; -+ -+ if (--retry == 0) -+ return -ETIMEDOUT; -+ -+ usleep_range(10, 20); -+ } -+ -+ return 0; -+} -+ -+/** -+ * Write SSPHY register -+ * -+ * @base - QCOM DWC3 PHY base virtual address. -+ * @addr - SSPHY address to write. -+ * @val - value to write. -+ */ -+static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3, -+ u32 addr, u32 val) -+{ -+ int ret; -+ -+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG); -+ writel(SS_CR_CAP_ADDR_REG, -+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG); -+ if (ret) -+ goto err_wait; -+ -+ writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG); -+ writel(SS_CR_CAP_DATA_REG, -+ phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG); -+ if (ret) -+ goto err_wait; -+ -+ writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG); -+ -+err_wait: -+ if (ret) -+ dev_err(phy_dwc3->dev, "timeout waiting for latch\n"); -+ return ret; -+} -+ -+/** -+ * Read SSPHY register. -+ * -+ * @base - QCOM DWC3 PHY base virtual address. -+ * @addr - SSPHY address to read. -+ */ -+static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3, -+ u32 addr, u32 *val) -+{ -+ int ret; -+ -+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG); -+ writel(SS_CR_CAP_ADDR_REG, -+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG); -+ if (ret) -+ goto err_wait; -+ -+ /* -+ * Due to hardware bug, first read of SSPHY register might be -+ * incorrect. Hence as workaround, SW should perform SSPHY register -+ * read twice, but use only second read and ignore first read. -+ */ -+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG); -+ if (ret) -+ goto err_wait; -+ -+ /* throwaway read */ -+ readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG); -+ -+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG); -+ -+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG); -+ if (ret) -+ goto err_wait; -+ -+ *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG); -+ -+err_wait: -+ return ret; -+} -+ -+static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy) -+{ -+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ int ret; -+ u32 val; -+ -+ ret = clk_prepare_enable(phy_dwc3->xo_clk); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(phy_dwc3->ref_clk); -+ if (ret) { -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ return ret; -+ } -+ -+ /* -+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel -+ * enable clamping, and disable RETENTION (power-on default is ENABLED) -+ */ -+ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP | -+ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN | -+ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP | -+ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID | -+ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70; -+ -+ /* use core clock if external reference is not present */ -+ if (!phy_dwc3->xo_clk) -+ val |= HSUSB_CTRL_USE_CLKCORE; -+ -+ writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG); -+ usleep_range(2000, 2200); -+ -+ /* Disable (bypass) VBUS and ID filters */ -+ writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG); -+ -+ return 0; -+} -+ -+static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy) -+{ -+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ -+ clk_disable_unprepare(phy_dwc3->ref_clk); -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ -+ return 0; -+} -+ -+static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy) -+{ -+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ int ret; -+ u32 data; -+ -+ ret = clk_prepare_enable(phy_dwc3->xo_clk); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(phy_dwc3->ref_clk); -+ if (ret) { -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ return ret; -+ } -+ -+ /* reset phy */ -+ data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG); -+ writel(data | SSUSB_CTRL_SS_PHY_RESET, -+ phy_dwc3->base + SSUSB_PHY_CTRL_REG); -+ usleep_range(2000, 2200); -+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG); -+ -+ /* clear REF_PAD if we don't have XO clk */ -+ if (!phy_dwc3->xo_clk) -+ data &= ~SSUSB_CTRL_REF_USE_PAD; -+ else -+ data |= SSUSB_CTRL_REF_USE_PAD; -+ -+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG); -+ -+ /* wait for ref clk to become stable, this can take up to 30ms */ -+ msleep(30); -+ -+ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT; -+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG); -+ -+ /* -+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates -+ * in HS mode instead of SS mode. Workaround it by asserting -+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode -+ */ -+ ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data |= (1 << 7); -+ ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data); -+ if (ret) -+ goto err_phy_trans; -+ -+ ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data &= ~0xff0; -+ data |= 0x20; -+ ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data); -+ if (ret) -+ goto err_phy_trans; -+ -+ /* -+ * Fix RX Equalization setting as follows -+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 -+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 -+ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version -+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 -+ */ -+ ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data &= ~RX_OVRD_IN_HI_RX_EQ_EN; -+ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD; -+ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK; -+ data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq); -+ data |= RX_OVRD_IN_HI_RX_EQ_OVRD; -+ ret = usb_ss_write_phycreg(phy_dwc3, -+ SSPHY_CTRL_RX_OVRD_IN_HI(0), data); -+ if (ret) -+ goto err_phy_trans; -+ -+ /* -+ * Set EQ and TX launch amplitudes as follows -+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version -+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 -+ * LANE0.TX_OVRD_DRV_LO.EN set to 1. -+ */ -+ ret = usb_ss_read_phycreg(phy_dwc3, -+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK; -+ data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db); -+ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK; -+ data |= 0x6E; -+ data |= TX_OVRD_DRV_LO_EN; -+ ret = usb_ss_write_phycreg(phy_dwc3, -+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data); -+ if (ret) -+ goto err_phy_trans; -+ -+ data = 0; -+ data &= ~SSPHY_MPLL_MASK; -+ data |= SSPHY_MPLL(phy_dwc3->mpll); -+ usb_ss_write_phycreg(phy_dwc3, 0x30, data); -+ -+ /* -+ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows -+ * TX_FULL_SWING [26:20] amplitude to 110 -+ * TX_DEEMPH_6DB [19:14] to 32 -+ * TX_DEEMPH_3_5DB [13:8] set based on SoC version -+ * LOS_BIAS [7:3] to 9 -+ */ -+ data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1); -+ -+ data &= ~PHY_PARAM_CTRL1_MASK; -+ -+ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) | -+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) | -+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) | -+ PHY_PARAM_CTRL1_LOS_BIAS(0x9); -+ -+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1, -+ PHY_PARAM_CTRL1_MASK, data); -+ -+err_phy_trans: -+ return ret; -+} -+ -+static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy) -+{ -+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy); -+ -+ /* Sequence to put SSPHY in low power state: -+ * 1. Clear REF_PHY_EN in PHY_CTRL_REG -+ * 2. Clear REF_USE_PAD in PHY_CTRL_REG -+ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention -+ */ -+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, -+ SSUSB_CTRL_SS_PHY_EN, 0x0); -+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, -+ SSUSB_CTRL_REF_USE_PAD, 0x0); -+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, -+ SSUSB_CTRL_TEST_POWERDOWN, 0x0); -+ -+ clk_disable_unprepare(phy_dwc3->ref_clk); -+ clk_disable_unprepare(phy_dwc3->xo_clk); -+ -+ return 0; -+} -+ -+static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = { -+ .ops = { -+ .init = qcom_ipq806x_usb_hs_phy_init, -+ .exit = qcom_ipq806x_usb_hs_phy_exit, -+ .owner = THIS_MODULE, -+ }, -+ .clk_rate = 60000000, -+}; -+ -+static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = { -+ .ops = { -+ .init = qcom_ipq806x_usb_ss_phy_init, -+ .exit = qcom_ipq806x_usb_ss_phy_exit, -+ .owner = THIS_MODULE, -+ }, -+ .clk_rate = 125000000, -+}; -+ -+static const struct of_device_id qcom_ipq806x_usb_phy_table[] = { -+ { .compatible = "qcom,ipq806x-usb-phy-hs", -+ .data = &qcom_ipq806x_usb_hs_drvdata }, -+ { .compatible = "qcom,ipq806x-usb-phy-ss", -+ .data = &qcom_ipq806x_usb_ss_drvdata }, -+ { /* Sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table); -+ -+static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ resource_size_t size; -+ struct phy *generic_phy; -+ struct usb_phy *phy_dwc3; -+ const struct phy_drvdata *data; -+ struct phy_provider *phy_provider; -+ -+ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL); -+ if (!phy_dwc3) -+ return -ENOMEM; -+ -+ data = of_device_get_match_data(&pdev->dev); -+ -+ phy_dwc3->dev = &pdev->dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -EINVAL; -+ size = resource_size(res); -+ phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size); -+ -+ if (IS_ERR(phy_dwc3->base)) { -+ dev_err(phy_dwc3->dev, "failed to map reg\n"); -+ return PTR_ERR(phy_dwc3->base); -+ } -+ -+ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref"); -+ if (IS_ERR(phy_dwc3->ref_clk)) { -+ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n"); -+ return PTR_ERR(phy_dwc3->ref_clk); -+ } -+ -+ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate); -+ -+ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo"); -+ if (IS_ERR(phy_dwc3->xo_clk)) { -+ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n"); -+ phy_dwc3->xo_clk = NULL; -+ } -+ -+ /* Parse device node to probe HSIO settings */ -+ if (device_property_read_u32(&pdev->dev, "qcom,rx-eq", -+ &phy_dwc3->rx_eq)) -+ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE; -+ -+ if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db", -+ &phy_dwc3->tx_deamp_3_5db)) -+ phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB; -+ -+ if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll)) -+ phy_dwc3->mpll = SSPHY_MPLL_VALUE; -+ -+ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops); -+ -+ if (IS_ERR(generic_phy)) -+ return PTR_ERR(generic_phy); -+ -+ phy_set_drvdata(generic_phy, phy_dwc3); -+ platform_set_drvdata(pdev, phy_dwc3); -+ -+ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev, -+ of_phy_simple_xlate); -+ -+ if (IS_ERR(phy_provider)) -+ return PTR_ERR(phy_provider); -+ -+ return 0; -+} -+ -+static struct platform_driver qcom_ipq806x_usb_phy_driver = { -+ .probe = qcom_ipq806x_usb_phy_probe, -+ .driver = { -+ .name = "qcom-ipq806x-usb-phy", -+ .owner = THIS_MODULE, -+ .of_match_table = qcom_ipq806x_usb_phy_table, -+ }, -+}; -+ -+module_platform_driver(qcom_ipq806x_usb_phy_driver); -+ -+MODULE_ALIAS("platform:phy-qcom-ipq806x-usb"); -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); -+MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); -+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver"); diff --git a/target/linux/ipq806x/patches-5.10/095-2-v5.9-phy-qualcomm-fix-setting-of-tx_deamp_3_5db-when-device-property-read-fails.patch b/target/linux/ipq806x/patches-5.10/095-2-v5.9-phy-qualcomm-fix-setting-of-tx_deamp_3_5db-when-device-property-read-fails.patch deleted file mode 100644 index dedbb51049..0000000000 --- a/target/linux/ipq806x/patches-5.10/095-2-v5.9-phy-qualcomm-fix-setting-of-tx_deamp_3_5db-when-device-property-read-fails.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 3d7b0ca5300bd01b176f2b4c10e173db802560d8 Mon Sep 17 00:00:00 2001 -From: Colin Ian King <colin.king@canonical.com> -Date: Tue, 21 Jul 2020 16:06:13 +0100 -Subject: phy: qualcomm: fix setting of tx_deamp_3_5db when device property - read fails - -Currently when reading of the device property for "qcom,tx-deamp_3_5db" -fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This -looks like a copy-n-paste error and in fact should be assigning the -default instead to phy_dwc3->tx_deamp_3_5db - -Addresses-Coverity: ("Copy-paste error") -Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver") -Signed-off-by: Colin Ian King <colin.king@canonical.com> -Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.com -Signed-off-by: Vinod Koul <vkoul@kernel.org> ---- - drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c -+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c -@@ -531,7 +531,7 @@ static int qcom_ipq806x_usb_phy_probe(st - - if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db", - &phy_dwc3->tx_deamp_3_5db)) -- phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB; -+ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB; - - if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll)) - phy_dwc3->mpll = SSPHY_MPLL_VALUE; |