kernel: bump 5.4 to 5.4.60

Deleted upstream patches:
  generic:
    041-genirq-affinity-Make-affinity-setting-if-activated-o.patch
  ipq806x:
    093-5-v5.8-ipq806x-PCI-qcom-Define-some-PARF-params-needed-for-ipq8064-SoC.patch
    093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch

Merged manually:
  ipq806x:
    093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
  layerscape:
    804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch

Build-tested: ath79/generic, ipq806x, layerscape/armv7, layerscape/armv8_64b
Run-tested: ipq806x (R7800)

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>

6 files changed, 86 insertions, 206 deletions

diff --git a/target/linux/ipq806x/patches-5.4/093-1-v5.8-ipq806x-PCI-qcom-Add-missing-ipq806x-clocks-in-PCIe-driver.patch b/target/linux/ipq806x/patches-5.4/093-1-v5.8-ipq806x-PCI-qcom-Add-missing-ipq806x-clocks-in-PCIe-driver.patch
index 7eb79cae4d..6098cb8fe0 100644
--- a/target/linux/ipq806x/patches-5.4/093-1-v5.8-ipq806x-PCI-qcom-Add-missing-ipq806x-clocks-in-PCIe-driver.patch
+++ b/target/linux/ipq806x/patches-5.4/093-1-v5.8-ipq806x-PCI-qcom-Add-missing-ipq806x-clocks-in-PCIe-driver.patch
@@ -19,7 +19,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -85,6 +85,8 @@ struct qcom_pcie_resources_2_1_0 {
+@@ -103,6 +103,8 @@ struct qcom_pcie_resources_2_1_0 {
  	struct clk *iface_clk;
  	struct clk *core_clk;
  	struct clk *phy_clk;
@@ -28,7 +28,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	struct reset_control *pci_reset;
  	struct reset_control *axi_reset;
  	struct reset_control *ahb_reset;
-@@ -235,6 +237,14 @@ static int qcom_pcie_get_resources_2_1_0
+@@ -253,6 +255,14 @@ static int qcom_pcie_get_resources_2_1_0
  	if (IS_ERR(res->phy_clk))
  		return PTR_ERR(res->phy_clk);
  
@@ -43,7 +43,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
  	if (IS_ERR(res->pci_reset))
  		return PTR_ERR(res->pci_reset);
-@@ -267,6 +277,8 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -285,6 +295,8 @@ static void qcom_pcie_deinit_2_1_0(struc
  	clk_disable_unprepare(res->iface_clk);
  	clk_disable_unprepare(res->core_clk);
  	clk_disable_unprepare(res->phy_clk);
@@ -52,7 +52,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
  }
  
-@@ -296,16 +308,28 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -315,16 +327,28 @@ static int qcom_pcie_init_2_1_0(struct q
  		goto err_assert_ahb;
  	}
  
@@ -84,7 +84,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	}
  
  	ret = reset_control_deassert(res->ahb_reset);
-@@ -361,10 +385,14 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -400,10 +424,14 @@ static int qcom_pcie_init_2_1_0(struct q
  	return 0;
  
  err_deassert_ahb:
diff --git a/target/linux/ipq806x/patches-5.4/093-2-v5.8-ipq806x-PCI-qcom-Change-duplicate-PCI-reset-to-phy-reset.patch b/target/linux/ipq806x/patches-5.4/093-2-v5.8-ipq806x-PCI-qcom-Change-duplicate-PCI-reset-to-phy-reset.patch
index a2d44a4fb0..9600419710 100644
--- a/target/linux/ipq806x/patches-5.4/093-2-v5.8-ipq806x-PCI-qcom-Change-duplicate-PCI-reset-to-phy-reset.patch
+++ b/target/linux/ipq806x/patches-5.4/093-2-v5.8-ipq806x-PCI-qcom-Change-duplicate-PCI-reset-to-phy-reset.patch
@@ -18,7 +18,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -269,14 +269,14 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -287,14 +287,14 @@ static void qcom_pcie_deinit_2_1_0(struc
  {
  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
  
@@ -35,7 +35,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	clk_disable_unprepare(res->aux_clk);
  	clk_disable_unprepare(res->ref_clk);
  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
-@@ -314,12 +314,6 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -333,12 +333,6 @@ static int qcom_pcie_init_2_1_0(struct q
  		goto err_clk_core;
  	}
  
@@ -48,7 +48,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	ret = clk_prepare_enable(res->aux_clk);
  	if (ret) {
  		dev_err(dev, "cannot prepare/enable aux clock\n");
-@@ -372,6 +366,12 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -411,6 +405,12 @@ static int qcom_pcie_init_2_1_0(struct q
  		return ret;
  	}
  
@@ -61,7 +61,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	/* wait for clock acquisition */
  	usleep_range(1000, 1500);
  
-@@ -389,8 +389,6 @@ err_deassert_ahb:
+@@ -428,8 +428,6 @@ err_deassert_ahb:
  err_clk_ref:
  	clk_disable_unprepare(res->aux_clk);
  err_clk_aux:
diff --git a/target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch b/target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch
index e9595dc2a9..fe31e55de3 100644
--- a/target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch
+++ b/target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch
@@ -20,7 +20,7 @@ Cc: stable@vger.kernel.org # v4.5+
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -92,6 +92,7 @@ struct qcom_pcie_resources_2_1_0 {
+@@ -110,6 +110,7 @@ struct qcom_pcie_resources_2_1_0 {
  	struct reset_control *ahb_reset;
  	struct reset_control *por_reset;
  	struct reset_control *phy_reset;
@@ -28,7 +28,7 @@ Cc: stable@vger.kernel.org # v4.5+
  	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
  };
  
-@@ -261,6 +262,10 @@ static int qcom_pcie_get_resources_2_1_0
+@@ -279,6 +280,10 @@ static int qcom_pcie_get_resources_2_1_0
  	if (IS_ERR(res->por_reset))
  		return PTR_ERR(res->por_reset);
  
@@ -39,7 +39,7 @@ Cc: stable@vger.kernel.org # v4.5+
  	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
  	return PTR_ERR_OR_ZERO(res->phy_reset);
  }
-@@ -274,6 +279,7 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -292,6 +297,7 @@ static void qcom_pcie_deinit_2_1_0(struc
  	reset_control_assert(res->axi_reset);
  	reset_control_assert(res->ahb_reset);
  	reset_control_assert(res->por_reset);
@@ -47,7 +47,7 @@ Cc: stable@vger.kernel.org # v4.5+
  	reset_control_assert(res->phy_reset);
  	clk_disable_unprepare(res->iface_clk);
  	clk_disable_unprepare(res->core_clk);
-@@ -332,6 +338,12 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -351,6 +357,12 @@ static int qcom_pcie_init_2_1_0(struct q
  		goto err_deassert_ahb;
  	}
  
diff --git a/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch b/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
index 4d2da5f768..32fc297fe0 100644
--- a/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
+++ b/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
@@ -17,7 +17,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
 
 --- a/drivers/pci/controller/dwc/pcie-qcom.c
 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -81,12 +81,9 @@
+@@ -99,12 +99,9 @@
  #define SLV_ADDR_SPACE_SZ			0x10000000
  
  #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
@@ -32,7 +32,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	struct reset_control *pci_reset;
  	struct reset_control *axi_reset;
  	struct reset_control *ahb_reset;
-@@ -226,25 +223,21 @@ static int qcom_pcie_get_resources_2_1_0
+@@ -244,25 +241,21 @@ static int qcom_pcie_get_resources_2_1_0
  	if (ret)
  		return ret;
  
@@ -73,7 +73,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  
  	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
  	if (IS_ERR(res->pci_reset))
-@@ -274,17 +267,13 @@ static void qcom_pcie_deinit_2_1_0(struc
+@@ -292,17 +285,13 @@ static void qcom_pcie_deinit_2_1_0(struc
  {
  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
  
@@ -92,111 +92,113 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
  }
  
-@@ -302,36 +291,6 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -321,47 +310,45 @@ static int qcom_pcie_init_2_1_0(struct q
  		return ret;
  	}
  
 -	ret = reset_control_assert(res->ahb_reset);
--	if (ret) {
++	ret = reset_control_deassert(res->ahb_reset);
+ 	if (ret) {
 -		dev_err(dev, "cannot assert ahb reset\n");
 -		goto err_assert_ahb;
--	}
--
++		dev_err(dev, "cannot deassert ahb reset\n");
++		goto err_deassert_ahb;
+ 	}
+ 
 -	ret = clk_prepare_enable(res->iface_clk);
--	if (ret) {
++	ret = reset_control_deassert(res->ext_reset);
+ 	if (ret) {
 -		dev_err(dev, "cannot prepare/enable iface clock\n");
 -		goto err_assert_ahb;
--	}
--
--	ret = clk_prepare_enable(res->core_clk);
--	if (ret) {
--		dev_err(dev, "cannot prepare/enable core clock\n");
--		goto err_clk_core;
--	}
--
--	ret = clk_prepare_enable(res->aux_clk);
--	if (ret) {
--		dev_err(dev, "cannot prepare/enable aux clock\n");
--		goto err_clk_aux;
--	}
--
--	ret = clk_prepare_enable(res->ref_clk);
--	if (ret) {
--		dev_err(dev, "cannot prepare/enable ref clock\n");
--		goto err_clk_ref;
--	}
--
- 	ret = reset_control_deassert(res->ahb_reset);
- 	if (ret) {
- 		dev_err(dev, "cannot deassert ahb reset\n");
-@@ -341,48 +300,46 @@ static int qcom_pcie_init_2_1_0(struct q
- 	ret = reset_control_deassert(res->ext_reset);
- 	if (ret) {
- 		dev_err(dev, "cannot deassert ext reset\n");
--		goto err_deassert_ahb;
++		dev_err(dev, "cannot deassert ext reset\n");
 +		goto err_deassert_ext;
  	}
  
--	/* enable PCIe clocks and resets */
--	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
--	val &= ~BIT(0);
--	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
--
--	/* enable external reference clock */
--	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
--	val |= BIT(16);
--	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
--
- 	ret = reset_control_deassert(res->phy_reset);
+-	ret = clk_prepare_enable(res->core_clk);
++	ret = reset_control_deassert(res->phy_reset);
  	if (ret) {
- 		dev_err(dev, "cannot deassert phy reset\n");
--		return ret;
+-		dev_err(dev, "cannot prepare/enable core clock\n");
+-		goto err_clk_core;
++		dev_err(dev, "cannot deassert phy reset\n");
 +		goto err_deassert_phy;
  	}
  
- 	ret = reset_control_deassert(res->pci_reset);
+-	ret = clk_prepare_enable(res->aux_clk);
++	ret = reset_control_deassert(res->pci_reset);
  	if (ret) {
- 		dev_err(dev, "cannot deassert pci reset\n");
--		return ret;
+-		dev_err(dev, "cannot prepare/enable aux clock\n");
+-		goto err_clk_aux;
++		dev_err(dev, "cannot deassert pci reset\n");
 +		goto err_deassert_pci;
  	}
  
- 	ret = reset_control_deassert(res->por_reset);
+-	ret = clk_prepare_enable(res->ref_clk);
++	ret = reset_control_deassert(res->por_reset);
  	if (ret) {
- 		dev_err(dev, "cannot deassert por reset\n");
--		return ret;
+-		dev_err(dev, "cannot prepare/enable ref clock\n");
+-		goto err_clk_ref;
++		dev_err(dev, "cannot deassert por reset\n");
 +		goto err_deassert_por;
  	}
  
- 	ret = reset_control_deassert(res->axi_reset);
+-	ret = reset_control_deassert(res->ahb_reset);
++	ret = reset_control_deassert(res->axi_reset);
  	if (ret) {
- 		dev_err(dev, "cannot deassert axi reset\n");
--		return ret;
+-		dev_err(dev, "cannot deassert ahb reset\n");
+-		goto err_deassert_ahb;
++		dev_err(dev, "cannot deassert axi reset\n");
 +		goto err_deassert_axi;
  	}
  
--	ret = clk_prepare_enable(res->phy_clk);
+-	ret = reset_control_deassert(res->ext_reset);
 -	if (ret) {
--		dev_err(dev, "cannot prepare/enable phy clock\n");
+-		dev_err(dev, "cannot deassert ext reset\n");
 -		goto err_deassert_ahb;
 -	}
 +	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
 +	if (ret)
 +		goto err_clks;
-+
-+	/* enable PCIe clocks and resets */
-+	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
-+	val &= ~BIT(0);
-+	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-+
-+	/* enable external reference clock */
-+	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
-+	val |= BIT(16);
-+	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
  
+ 	/* enable PCIe clocks and resets */
+ 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+@@ -393,36 +380,6 @@ static int qcom_pcie_init_2_1_0(struct q
+ 	val |= PHY_REFCLK_SSP_EN;
+ 	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ 
+-	ret = reset_control_deassert(res->phy_reset);
+-	if (ret) {
+-		dev_err(dev, "cannot deassert phy reset\n");
+-		return ret;
+-	}
+-
+-	ret = reset_control_deassert(res->pci_reset);
+-	if (ret) {
+-		dev_err(dev, "cannot deassert pci reset\n");
+-		return ret;
+-	}
+-
+-	ret = reset_control_deassert(res->por_reset);
+-	if (ret) {
+-		dev_err(dev, "cannot deassert por reset\n");
+-		return ret;
+-	}
+-
+-	ret = reset_control_deassert(res->axi_reset);
+-	if (ret) {
+-		dev_err(dev, "cannot deassert axi reset\n");
+-		return ret;
+-	}
+-
+-	ret = clk_prepare_enable(res->phy_clk);
+-	if (ret) {
+-		dev_err(dev, "cannot prepare/enable phy clock\n");
+-		goto err_deassert_ahb;
+-	}
+-
  	/* wait for clock acquisition */
  	usleep_range(1000, 1500);
-@@ -396,15 +353,19 @@ static int qcom_pcie_init_2_1_0(struct q
+ 
+@@ -435,15 +392,19 @@ static int qcom_pcie_init_2_1_0(struct q
  
  	return 0;
  
diff --git a/target/linux/ipq806x/patches-5.4/093-5-v5.8-ipq806x-PCI-qcom-Define-some-PARF-params-needed-for-ipq8064-SoC.patch b/target/linux/ipq806x/patches-5.4/093-5-v5.8-ipq806x-PCI-qcom-Define-some-PARF-params-needed-for-ipq8064-SoC.patch
deleted file mode 100644
index ff3f34cbf8..0000000000
--- a/target/linux/ipq806x/patches-5.4/093-5-v5.8-ipq806x-PCI-qcom-Define-some-PARF-params-needed-for-ipq8064-SoC.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 5149901e9e6deca487c01cc434a3ac4125c7b00b Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 15 Jun 2020 23:06:03 +0200
-Subject: PCI: qcom: Define some PARF params needed for ipq8064 SoC
-
-Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
-needed on some ipq8064 based device (Netgear R7800 for example). Without
-this the system locks on kernel load.
-
-Link: https://lore.kernel.org/r/20200615210608.21469-8-ansuelsmth@gmail.com
-Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
-Cc: stable@vger.kernel.org # v4.5+
----
- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -76,6 +76,18 @@
- #define DBI_RO_WR_EN				1
- 
- #define PERST_DELAY_US				1000
-+/* PARF registers */
-+#define PCIE20_PARF_PCS_DEEMPH			0x34
-+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		((x) << 16)
-+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	((x) << 8)
-+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	((x) << 0)
-+
-+#define PCIE20_PARF_PCS_SWING			0x38
-+#define PCS_SWING_TX_SWING_FULL(x)		((x) << 8)
-+#define PCS_SWING_TX_SWING_LOW(x)		((x) << 0)
-+
-+#define PCIE20_PARF_CONFIG_BITS		0x50
-+#define PHY_RX0_EQ(x)				((x) << 24)
- 
- #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
- #define SLV_ADDR_SPACE_SZ			0x10000000
-@@ -282,6 +294,7 @@ static int qcom_pcie_init_2_1_0(struct q
- 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- 	struct dw_pcie *pci = pcie->pci;
- 	struct device *dev = pci->dev;
-+	struct device_node *node = dev->of_node;
- 	u32 val;
- 	int ret;
- 
-@@ -336,6 +349,17 @@ static int qcom_pcie_init_2_1_0(struct q
- 	val &= ~BIT(0);
- 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
- 
-+	if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
-+		writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
-+			       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
-+			       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
-+		       pcie->parf + PCIE20_PARF_PCS_DEEMPH);
-+		writel(PCS_SWING_TX_SWING_FULL(120) |
-+			       PCS_SWING_TX_SWING_LOW(120),
-+		       pcie->parf + PCIE20_PARF_PCS_SWING);
-+		writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
-+	}
-+
- 	/* enable external reference clock */
- 	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- 	val |= BIT(16);
diff --git a/target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch b/target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch
deleted file mode 100644
index 911c18e69d..0000000000
--- a/target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From de3c4bf648975ea0b1d344d811e9b0748907b47c Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 15 Jun 2020 23:06:04 +0200
-Subject: PCI: qcom: Add support for tx term offset for rev 2.1.0
-
-Add tx term offset support to pcie qcom driver need in some revision of
-the ipq806x SoC. Ipq8064 needs tx term offset set to 7.
-
-Link: https://lore.kernel.org/r/20200615210608.21469-9-ansuelsmth@gmail.com
-Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
-Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
-Cc: stable@vger.kernel.org # v4.5+
----
- drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++-
- 1 file changed, 16 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -45,7 +45,13 @@
- #define PCIE_CAP_CPL_TIMEOUT_DISABLE		0x10
- 
- #define PCIE20_PARF_PHY_CTRL			0x40
-+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK	GENMASK(20, 16)
-+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)		((x) << 16)
-+
- #define PCIE20_PARF_PHY_REFCLK			0x4C
-+#define PHY_REFCLK_SSP_EN			BIT(16)
-+#define PHY_REFCLK_USE_PAD			BIT(12)
-+
- #define PCIE20_PARF_DBI_BASE_ADDR		0x168
- #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
- #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
-@@ -360,9 +366,18 @@ static int qcom_pcie_init_2_1_0(struct q
- 		writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
- 	}
- 
-+	if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
-+		/* set TX termination offset */
-+		val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
-+		val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
-+		val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
-+		writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-+	}
-+
- 	/* enable external reference clock */
- 	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
--	val |= BIT(16);
-+	val &= ~PHY_REFCLK_USE_PAD;
-+	val |= PHY_REFCLK_SSP_EN;
- 	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
- 
- 	/* wait for clock acquisition */