ipq806x: Add support for IPQ806x chip family

Patches are generated using the "format-patch" command from the
following location:
*https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base
*rev=0771849495b4128cac2faf7d49c85c729fc48b20
Patches numbered 76/77/102/103 have already been integrated in 3.14.12,
so they're not in this list.

All these patches are either integrated are pending integration into
kernel.org, therefore these patches should go away once the kernel
gets upgraded to 3.16.

Support is currently limited to AP148 board but can be extended to other
platforms in the future.

These changes do not cover ethernet connectivity.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42334 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 63 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches/0034-pinctrl-msm-Add-SPI8-pin-definitions.patch b/target/linux/ipq806x/patches/0034-pinctrl-msm-Add-SPI8-pin-definitions.patch
new file mode 100644
index 0000000000..b8df704ec0
--- /dev/null
+++ b/target/linux/ipq806x/patches/0034-pinctrl-msm-Add-SPI8-pin-definitions.patch
@@ -0,0 +1,63 @@
+From 77e4b572fcc4015e235f22fd93b8df35e452baf0 Mon Sep 17 00:00:00 2001
+From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
+Date: Thu, 6 Feb 2014 17:28:48 +0200
+Subject: [PATCH 034/182] pinctrl-msm: Add SPI8 pin definitions
+
+Add pin, group and function definitions for SPI#8
+controller.
+
+Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
+Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-msm8x74.c |   13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c
+index bb5ded69f..dde5529 100644
+--- a/drivers/pinctrl/pinctrl-msm8x74.c
++++ b/drivers/pinctrl/pinctrl-msm8x74.c
+@@ -405,6 +405,7 @@ enum msm8x74_functions {
+ 	MSM_MUX_blsp_i2c6,
+ 	MSM_MUX_blsp_i2c11,
+ 	MSM_MUX_blsp_spi1,
++	MSM_MUX_blsp_spi8,
+ 	MSM_MUX_blsp_uart2,
+ 	MSM_MUX_blsp_uart8,
+ 	MSM_MUX_slimbus,
+@@ -415,6 +416,9 @@ static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
+ static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
+ static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
+ static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" };
++static const char * const blsp_spi8_groups[] = {
++	"gpio45", "gpio46", "gpio47", "gpio48"
++};
+ static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" };
+ static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" };
+ static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
+@@ -424,6 +428,7 @@ static const struct msm_function msm8x74_functions[] = {
+ 	FUNCTION(blsp_i2c6),
+ 	FUNCTION(blsp_i2c11),
+ 	FUNCTION(blsp_spi1),
++	FUNCTION(blsp_spi8),
+ 	FUNCTION(blsp_uart2),
+ 	FUNCTION(blsp_uart8),
+ 	FUNCTION(slimbus),
+@@ -475,10 +480,10 @@ static const struct msm_pingroup msm8x74_groups[] = {
+ 	PINGROUP(42,  NA, NA, NA, NA, NA, NA, NA),
+ 	PINGROUP(43,  NA, NA, NA, NA, NA, NA, NA),
+ 	PINGROUP(44,  NA, NA, NA, NA, NA, NA, NA),
+-	PINGROUP(45,  NA, blsp_uart8, NA, NA, NA, NA, NA),
+-	PINGROUP(46,  NA, blsp_uart8, NA, NA, NA, NA, NA),
+-	PINGROUP(47,  NA, NA, NA, NA, NA, NA, NA),
+-	PINGROUP(48,  NA, NA, NA, NA, NA, NA, NA),
++	PINGROUP(45,  blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
++	PINGROUP(46,  blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
++	PINGROUP(47,  blsp_spi8, NA, NA, NA, NA, NA, NA),
++	PINGROUP(48,  blsp_spi8, NA, NA, NA, NA, NA, NA),
+ 	PINGROUP(49,  NA, NA, NA, NA, NA, NA, NA),
+ 	PINGROUP(50,  NA, NA, NA, NA, NA, NA, NA),
+ 	PINGROUP(51,  NA, NA, NA, NA, NA, NA, NA),
+-- 
+1.7.10.4
+