ipq806x: update target to v3.18

Patches in the ipq806x/patches folder were out of tree in v3.14. The
newest patch at the time was from June, so we can safely assume that
either the patches have been merged, or they have been rejected for
a good reason. If patches are seen missing, we'll cherry-pick them
on a per-needed basis.

This new kernel have been tested on AP148, which seems to works fine.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 44386

1 files changed, 0 insertions, 205 deletions

diff --git a/target/linux/ipq806x/patches/0021-ARM-dts-qcom-Add-nodes-necessary-for-SMP-boot.patch b/target/linux/ipq806x/patches/0021-ARM-dts-qcom-Add-nodes-necessary-for-SMP-boot.patch
deleted file mode 100644
index 232f2efed9..0000000000
--- a/target/linux/ipq806x/patches/0021-ARM-dts-qcom-Add-nodes-necessary-for-SMP-boot.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From 5a054211d9380cef5a09da7c5e815c827f330a96 Mon Sep 17 00:00:00 2001
-From: Rohit Vaswani <rvaswani@codeaurora.org>
-Date: Fri, 1 Nov 2013 10:10:40 -0700
-Subject: [PATCH 021/182] ARM: dts: qcom: Add nodes necessary for SMP boot
-
-Add the necessary nodes to support SMP on MSM8660, MSM8960, and
-MSM8974/APQ8074. While we're here also add in the error
-interrupts for the Krait cache error detection.
-
-Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
-[sboyd: Split into separate patch, add error interrupts]
-Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-Signed-off-by: Kumar Gala <galak@codeaurora.org>
----
- arch/arm/boot/dts/qcom-msm8660.dtsi |   24 ++++++++++++
- arch/arm/boot/dts/qcom-msm8960.dtsi |   52 ++++++++++++++++++++++++++
- arch/arm/boot/dts/qcom-msm8974.dtsi |   69 +++++++++++++++++++++++++++++++++++
- 3 files changed, 145 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-msm8660.dtsi
-+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
-@@ -9,6 +9,30 @@
- 	compatible = "qcom,msm8660";
- 	interrupt-parent = <&intc>;
- 
-+	cpus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		compatible = "qcom,scorpion";
-+		enable-method = "qcom,gcc-msm8660";
-+
-+		cpu@0 {
-+			device_type = "cpu";
-+			reg = <0>;
-+			next-level-cache = <&L2>;
-+		};
-+
-+		cpu@1 {
-+			device_type = "cpu";
-+			reg = <1>;
-+			next-level-cache = <&L2>;
-+		};
-+
-+		L2: l2-cache {
-+			compatible = "cache";
-+			cache-level = <2>;
-+		};
-+	};
-+
- 	intc: interrupt-controller@2080000 {
- 		compatible = "qcom,msm-8660-qgic";
- 		interrupt-controller;
---- a/arch/arm/boot/dts/qcom-msm8960.dtsi
-+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
-@@ -9,6 +9,36 @@
- 	compatible = "qcom,msm8960";
- 	interrupt-parent = <&intc>;
- 
-+	cpus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		interrupts = <1 14 0x304>;
-+		compatible = "qcom,krait";
-+		enable-method = "qcom,kpss-acc-v1";
-+
-+		cpu@0 {
-+			device_type = "cpu";
-+			reg = <0>;
-+			next-level-cache = <&L2>;
-+			qcom,acc = <&acc0>;
-+			qcom,saw = <&saw0>;
-+		};
-+
-+		cpu@1 {
-+			device_type = "cpu";
-+			reg = <1>;
-+			next-level-cache = <&L2>;
-+			qcom,acc = <&acc1>;
-+			qcom,saw = <&saw1>;
-+		};
-+
-+		L2: l2-cache {
-+			compatible = "cache";
-+			cache-level = <2>;
-+			interrupts = <0 2 0x4>;
-+		};
-+	};
-+
- 	intc: interrupt-controller@2000000 {
- 		compatible = "qcom,msm-qgic2";
- 		interrupt-controller;
-@@ -53,6 +83,28 @@
- 		#reset-cells = <1>;
- 	};
- 
-+	acc0: clock-controller@2088000 {
-+		compatible = "qcom,kpss-acc-v1";
-+		reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
-+	};
-+
-+	acc1: clock-controller@2098000 {
-+		compatible = "qcom,kpss-acc-v1";
-+		reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
-+	};
-+
-+	saw0: regulator@2089000 {
-+		compatible = "qcom,saw2";
-+		reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-+		regulator;
-+	};
-+
-+	saw1: regulator@2099000 {
-+		compatible = "qcom,saw2";
-+		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
-+		regulator;
-+	};
-+
- 	serial@16440000 {
- 		compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- 		reg = <0x16440000 0x1000>,
---- a/arch/arm/boot/dts/qcom-msm8974.dtsi
-+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
-@@ -9,6 +9,49 @@
- 	compatible = "qcom,msm8974";
- 	interrupt-parent = <&intc>;
- 
-+	cpus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		interrupts = <1 9 0xf04>;
-+		compatible = "qcom,krait";
-+		enable-method = "qcom,kpss-acc-v2";
-+
-+		cpu@0 {
-+			device_type = "cpu";
-+			reg = <0>;
-+			next-level-cache = <&L2>;
-+			qcom,acc = <&acc0>;
-+		};
-+
-+		cpu@1 {
-+			device_type = "cpu";
-+			reg = <1>;
-+			next-level-cache = <&L2>;
-+			qcom,acc = <&acc1>;
-+		};
-+
-+		cpu@2 {
-+			device_type = "cpu";
-+			reg = <2>;
-+			next-level-cache = <&L2>;
-+			qcom,acc = <&acc2>;
-+		};
-+
-+		cpu@3 {
-+			device_type = "cpu";
-+			reg = <3>;
-+			next-level-cache = <&L2>;
-+			qcom,acc = <&acc3>;
-+		};
-+
-+		L2: l2-cache {
-+			compatible = "cache";
-+			cache-level = <2>;
-+			interrupts = <0 2 0x4>;
-+			qcom,saw = <&saw_l2>;
-+		};
-+	};
-+
- 	soc: soc {
- 		#address-cells = <1>;
- 		#size-cells = <1>;
-@@ -91,6 +134,32 @@
- 			};
- 		};
- 
-+		saw_l2: regulator@f9012000 {
-+			compatible = "qcom,saw2";
-+			reg = <0xf9012000 0x1000>;
-+			regulator;
-+		};
-+
-+		acc0: clock-controller@f9088000 {
-+			compatible = "qcom,kpss-acc-v2";
-+			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
-+		};
-+
-+		acc1: clock-controller@f9098000 {
-+			compatible = "qcom,kpss-acc-v2";
-+			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
-+		};
-+
-+		acc2: clock-controller@f90a8000 {
-+			compatible = "qcom,kpss-acc-v2";
-+			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
-+		};
-+
-+		acc3: clock-controller@f90b8000 {
-+			compatible = "qcom,kpss-acc-v2";
-+			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
-+		};
-+
- 		restart@fc4ab000 {
- 			compatible = "qcom,pshold";
- 			reg = <0xfc4ab000 0x4>;