ipq806x: replace patches with upstream version

Replace all the custom patches with the backported upstream version

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
[refresh patches]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>

8 files changed, 218 insertions, 166 deletions

diff --git a/target/linux/ipq806x/patches-5.4/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch b/target/linux/ipq806x/patches-5.4/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
deleted file mode 100644
index 53e81b7a78..0000000000
--- a/target/linux/ipq806x/patches-5.4/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001
-From: Ajay Kishore <akisho@codeaurora.org>
-Date: Tue, 24 Jan 2017 14:14:16 +0530
-Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
-
-For IPQ806x targets, TZ protects the registers that are used to
-configure the routing of interrupts to a target processor.
-To resolve this, this patch uses scm call to route GPIO interrupts
-to application processor. Also the scm call interface is changed.
-
-Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce
-Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
----
-
---- a/drivers/pinctrl/qcom/pinctrl-msm.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
-@@ -22,7 +22,8 @@
- #include <linux/reboot.h>
- #include <linux/pm.h>
- #include <linux/log2.h>
--
-+#include <linux/qcom_scm.h>
-+#include <linux/io.h>
- #include "../core.h"
- #include "../pinconf.h"
- #include "pinctrl-msm.h"
-@@ -706,6 +707,9 @@ static void msm_gpio_irq_mask(struct irq
- 	const struct msm_pingroup *g;
- 	unsigned long flags;
- 	u32 val;
-+	u32 addr;
-+	int ret;
-+	const __be32 *reg;
- 
- 	g = &pctrl->soc->groups[d->hwirq];
- 
-@@ -819,6 +823,7 @@ static int msm_gpio_irq_set_type(struct
- 	const struct msm_pingroup *g;
- 	unsigned long flags;
- 	u32 val;
-+	int ret;
- 
- 	g = &pctrl->soc->groups[d->hwirq];
- 
-@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
- 	else
- 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
- 
-+	ret = of_device_is_compatible(pctrl->dev->of_node,
-+					"qcom,ipq8064-pinctrl");
- 	/* Route interrupts to application cpu */
--	val = msm_readl_intr_target(pctrl, g);
--	val &= ~(7 << g->intr_target_bit);
--	val |= g->intr_target_kpss_val << g->intr_target_bit;
--	msm_writel_intr_target(val, pctrl, g);
-+	if (!ret) {
-+		val = msm_readl_intr_target(pctrl, g);
-+		val &= ~(7 << g->intr_target_bit);
-+		val |= g->intr_target_kpss_val << g->intr_target_bit;
-+		msm_writel_intr_target(val, pctrl, g);
-+	} else {
-+		const __be32 *reg = of_get_property(pctrl->dev->of_node, "reg", NULL);
-+		if (reg) {
-+			u32 addr = be32_to_cpup(reg) + g->intr_target_reg;
-+			qcom_scm_io_readl(addr, &val);
-+			__iormb();
-+
-+			val &= ~(7 << g->intr_target_bit);
-+			val |= g->intr_target_kpss_val << g->intr_target_bit;
-+
-+			__iowmb();
-+			ret = qcom_scm_io_writel(addr, val);
-+			if (ret)
-+				pr_err("\n Routing interrupts to Apps proc failed");
-+		}
-+	}
- 
- 	/* Update configuration for gpio.
- 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
diff --git a/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch b/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
new file mode 100644
index 0000000000..2b5171fc54
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
@@ -0,0 +1,104 @@
+From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
+From: Ajay Kishore <akisho@codeaurora.org>
+Date: Fri, 27 Mar 2020 23:32:08 +0100
+Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
+
+For IPQ806x targets, TZ protects the registers that are used to
+configure the routing of interrupts to a target processor.
+To resolve this, this patch uses scm call to route GPIO interrupts
+to application processor. Also the scm call interface is changed.
+
+Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
+ 1 file changed, 37 insertions(+), 6 deletions(-)
+
+(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
+
+--- a/drivers/pinctrl/qcom/pinctrl-msm.c
++++ b/drivers/pinctrl/qcom/pinctrl-msm.c
+@@ -22,6 +22,8 @@
+ #include <linux/reboot.h>
+ #include <linux/pm.h>
+ #include <linux/log2.h>
++#include <linux/qcom_scm.h>
++#include <linux/io.h>
+ 
+ #include "../core.h"
+ #include "../pinconf.h"
+@@ -57,6 +59,8 @@ struct msm_pinctrl {
+ 	struct irq_chip irq_chip;
+ 	int irq;
+ 
++	bool intr_target_use_scm;
++
+ 	raw_spinlock_t lock;
+ 
+ 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
+@@ -64,6 +68,7 @@ struct msm_pinctrl {
+ 
+ 	const struct msm_pinctrl_soc_data *soc;
+ 	void __iomem *regs[MAX_NR_TILES];
++	u32 phys_base[MAX_NR_TILES];
+ };
+ 
+ #define MSM_ACCESSOR(name) \
+@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
+ 	else
+ 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
+ 
+-	/* Route interrupts to application cpu */
+-	val = msm_readl_intr_target(pctrl, g);
+-	val &= ~(7 << g->intr_target_bit);
+-	val |= g->intr_target_kpss_val << g->intr_target_bit;
+-	msm_writel_intr_target(val, pctrl, g);
++	/* Route interrupts to application cpu.
++	 * With intr_target_use_scm interrupts are routed to
++	 * application cpu using scm calls.
++	 */
++	if (pctrl->intr_target_use_scm) {
++		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
++		int ret;
++
++		qcom_scm_io_readl(addr, &val);
++
++		val &= ~(7 << g->intr_target_bit);
++		val |= g->intr_target_kpss_val << g->intr_target_bit;
++
++		ret = qcom_scm_io_writel(addr, val);
++		if (ret)
++			dev_err(pctrl->dev,
++				"Failed routing %lu interrupt to Apps proc",
++				d->hwirq);
++	} else {
++		val = msm_readl_intr_target(pctrl, g);
++		val &= ~(7 << g->intr_target_bit);
++		val |= g->intr_target_kpss_val << g->intr_target_bit;
++		msm_writel_intr_target(val, pctrl, g);
++	}
+ 
+ 	/* Update configuration for gpio.
+ 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
+@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
+ 	pctrl->dev = &pdev->dev;
+ 	pctrl->soc = soc_data;
+ 	pctrl->chip = msm_gpio_template;
++	pctrl->intr_target_use_scm = of_device_is_compatible(
++					pctrl->dev->of_node,
++					"qcom,ipq8064-pinctrl");
+ 
+ 	raw_spin_lock_init(&pctrl->lock);
+ 
+@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
+ 		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
+ 		if (IS_ERR(pctrl->regs[0]))
+ 			return PTR_ERR(pctrl->regs[0]);
++
++		pctrl->phys_base[0] = res->start;
+ 	}
+ 
+ 	msm_pinctrl_setup_pm_reset(pctrl);
diff --git a/target/linux/ipq806x/patches-5.4/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch b/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
index a0ea8eba54..612c33cd0e 100644
--- a/target/linux/ipq806x/patches-5.4/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
+++ b/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
@@ -1,9 +1,15 @@
-From a3488aa9bed37c56e405967d44e821c484b5d6b9 Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Fri, 28 Sep 2018 15:19:50 +0530
-Subject: [PATCH] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
+From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 19 Feb 2020 18:59:39 +0100
+Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
+
+Add missing gpio definition for mdio and rgmii2.
 
 Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 ---
  drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
  1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/linux/ipq806x/patches-5.4/0076-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch b/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch
index cc60cd7a08..605eb7d07b 100644
--- a/target/linux/ipq806x/patches-5.4/0076-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch
+++ b/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch
@@ -1,7 +1,7 @@
-From 53ae145a7afa7686e03332d61eed90b7fa7c2529 Mon Sep 17 00:00:00 2001
+From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001
 From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 4 Feb 2020 19:38:06 +0100
-Subject: [PATCH v2] watchdog: qcom-wdt: disable pretimeout on timer platform
+Date: Tue, 4 Feb 2020 20:56:48 +0100
+Subject: watchdog: qcom-wdt: disable pretimeout on timer platform
 
 Some platform like ipq806x doesn't support pretimeout and define
 some interrupts used by qcom,msm-timer. Change the driver to check
@@ -9,6 +9,11 @@ and use pretimeout only on qcom,kpss-wdt as it's the only platform
 that actually supports it.
 
 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com
+[groeck: Conflict resolution]
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
 ---
  drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++--------
  1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/target/linux/ipq806x/patches-5.4/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch b/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch
index 0965a31d90..015a917e20 100644
--- a/target/linux/ipq806x/patches-5.4/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch
+++ b/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch
@@ -1,13 +1,16 @@
-From a16fcf911a020e46439a3bb3e702463fc3159831 Mon Sep 17 00:00:00 2001
+From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001
 From: Abhishek Sahu <absahu@codeaurora.org>
-Date: Wed, 18 Nov 2015 12:38:56 +0530
-Subject: [PATCH 62/69] ipq806x: gcc: Added the enable regs and mask for PRNG
+Date: Wed, 18 Mar 2020 14:16:56 +0100
+Subject: ipq806x: gcc: Added the enable regs and mask for PRNG
 
-kernel got hanged while reading from /dev/hwrng at the
+Kernel got hanged while reading from /dev/hwrng at the
 time of PRNG clock enable
 
-Change-Id: I89856c7e19e6639508e6a2774304583a3ec91172
+Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
  drivers/clk/qcom/gcc-ipq806x.c | 2 ++
  1 file changed, 2 insertions(+)
diff --git a/target/linux/ipq806x/patches-5.4/0064-clk-clk-rpm-fixes.patch b/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch
index e3a955b659..a28570974e 100644
--- a/target/linux/ipq806x/patches-5.4/0064-clk-clk-rpm-fixes.patch
+++ b/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch
@@ -1,9 +1,16 @@
-From d30840e2b1cf79d90392e6051b0c0b6006d29d8b Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Thu, 9 Mar 2017 09:32:40 +0100
-Subject: [PATCH 64/69] clk: clk-rpm fixes
+From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Tue, 10 Mar 2020 15:37:56 +0100
+Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x
+
+Add missing definition of rpm clk for ipq806x soc
 
 Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Acked-by: John Crispin <john@phrozen.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
  .../devicetree/bindings/clock/qcom,rpmcc.txt       |  1 +
  drivers/clk/qcom/clk-rpm.c                         | 35 ++++++++++++++++++++++
@@ -12,32 +19,19 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
 +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
-@@ -16,6 +16,7 @@ Required properties :
+@@ -15,6 +15,7 @@ Required properties :
+ 			"qcom,rpmcc-msm8916", "qcom,rpmcc"
  			"qcom,rpmcc-msm8974", "qcom,rpmcc"
  			"qcom,rpmcc-apq8064", "qcom,rpmcc"
- 			"qcom,rpmcc-msm8996", "qcom,rpmcc"
 +			"qcom,rpmcc-ipq806x", "qcom,rpmcc"
+ 			"qcom,rpmcc-msm8996", "qcom,rpmcc"
  			"qcom,rpmcc-msm8998", "qcom,rpmcc"
  			"qcom,rpmcc-qcs404", "qcom,rpmcc"
- 
---- a/include/dt-bindings/clock/qcom,rpmcc.h
-+++ b/include/dt-bindings/clock/qcom,rpmcc.h
-@@ -37,6 +37,10 @@
- #define RPM_XO_A0				27
- #define RPM_XO_A1				28
- #define RPM_XO_A2				29
-+#define RPM_NSS_FABRIC_0_CLK			30
-+#define RPM_NSS_FABRIC_0_A_CLK			31
-+#define RPM_NSS_FABRIC_1_CLK			32
-+#define RPM_NSS_FABRIC_1_A_CLK			33
- 
- /* SMD RPM clocks */
- #define RPM_SMD_XO_CLK_SRC				0
 --- a/drivers/clk/qcom/clk-rpm.c
 +++ b/drivers/clk/qcom/clk-rpm.c
-@@ -512,6 +512,16 @@ DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_
- DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24);
- DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28);
+@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk
+ 	.num_clks = ARRAY_SIZE(apq8064_clks),
+ };
  
 +/* ipq806x */
 +DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
@@ -49,13 +43,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
 +DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
 +
- static struct clk_rpm *apq8064_clks[] = {
- 	[RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
- 	[RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
-@@ -538,15 +548,40 @@ static struct clk_rpm *apq8064_clks[] =
- 	[RPM_XO_A2] = &apq8064_xo_a2_clk,
- };
- 
 +static struct clk_rpm *ipq806x_clks[] = {
 +	[RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
 +	[RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
@@ -75,11 +62,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +	[RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
 +};
 +
- static const struct rpm_clk_desc rpm_clk_apq8064 = {
- 	.clks = apq8064_clks,
- 	.num_clks = ARRAY_SIZE(apq8064_clks),
- };
- 
 +static const struct rpm_clk_desc rpm_clk_ipq806x = {
 +	.clks = ipq806x_clks,
 +	.num_clks = ARRAY_SIZE(ipq806x_clks),
@@ -93,3 +75,16 @@ Signed-off-by: John Crispin <john@phrozen.org>
  	{ }
  };
  MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
+--- a/include/dt-bindings/clock/qcom,rpmcc.h
++++ b/include/dt-bindings/clock/qcom,rpmcc.h
+@@ -37,6 +37,10 @@
+ #define RPM_XO_A0				27
+ #define RPM_XO_A1				28
+ #define RPM_XO_A2				29
++#define RPM_NSS_FABRIC_0_CLK			30
++#define RPM_NSS_FABRIC_0_A_CLK			31
++#define RPM_NSS_FABRIC_1_CLK			32
++#define RPM_NSS_FABRIC_1_A_CLK			33
+ 
+ /* SMD RPM clocks */
+ #define RPM_SMD_XO_CLK_SRC				0
diff --git a/target/linux/ipq806x/patches-5.4/0053-regulator-add-smb208-support.patch b/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch
index 058b303798..42a02865a3 100644
--- a/target/linux/ipq806x/patches-5.4/0053-regulator-add-smb208-support.patch
+++ b/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch
@@ -1,9 +1,17 @@
-From ef10381ca4d01848ebedb4afb2c78feb8052f103 Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 08:26:54 +0100
-Subject: [PATCH 53/69] regulator: add smb208 support
+From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 19 Feb 2020 17:37:11 +0100
+Subject: regulator: add smb208 support
 
+Smb208 regulators are used on some ipq806x soc.
+Add support for it to make it avaiable on some routers
+that use it.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
 Signed-off-by: Adrian Panella <ianchi74@outlook.com>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
  Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++
  drivers/regulator/qcom_rpm-regulator.c             | 9 +++++++++
diff --git a/target/linux/ipq806x/patches-5.4/700-net-mdio-add-ipq8064-mdio-driver.patch b/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch
index 8ed3e035fd..fb8c827d65 100644
--- a/target/linux/ipq806x/patches-5.4/700-net-mdio-add-ipq8064-mdio-driver.patch
+++ b/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch
@@ -1,14 +1,21 @@
-From 5de1da6c862de6a92ac9aed521f21fd5a180f22b Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 2 Feb 2019 02:48:35 +0100
-Subject: [PATCH] net: mdio: add ipq8064 mdio driver
+From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 4 Mar 2020 22:38:32 +0100
+Subject: net: mdio: add ipq8064 mdio driver
 
+Currently ipq806x soc use generic bitbang driver to
+comunicate with the gmac ethernet interface.
+Add a dedicated driver created by chunkeey to fix this.
+
+Co-developed-by: Christian Lamparter <chunkeey@gmail.com>
 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
  drivers/net/phy/Kconfig        |   8 ++
  drivers/net/phy/Makefile       |   1 +
- drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++
- 3 files changed, 172 insertions(+)
+ drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 175 insertions(+)
  create mode 100644 drivers/net/phy/mdio-ipq8064.c
 
 --- a/drivers/net/phy/Kconfig
@@ -40,12 +47,13 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  obj-$(CONFIG_MDIO_OCTEON)	+= mdio-octeon.o
 --- /dev/null
 +++ b/drivers/net/phy/mdio-ipq8064.c
-@@ -0,0 +1,163 @@
+@@ -0,0 +1,166 @@
 +// SPDX-License-Identifier: GPL-2.0
-+//
-+// Qualcomm IPQ8064 MDIO interface driver
-+//
-+// Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
++/* Qualcomm IPQ8064 MDIO interface driver
++ *
++ * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
++ * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
++ */
 +
 +#include <linux/delay.h>
 +#include <linux/kernel.h>
@@ -74,8 +82,8 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 +
 +#define MII_DATA_REG_ADDR                       0x14
 +
-+#define MII_MDIO_DELAY                          (1000)
-+#define MII_MDIO_RETRY                          (10)
++#define MII_MDIO_DELAY_USEC                     (1000)
++#define MII_MDIO_RETRY_MSEC                     (10)
 +
 +struct ipq8064_mdio {
 +	struct regmap *base; /* NSS_GMAC0_BASE */
@@ -84,34 +92,30 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 +static int
 +ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
 +{
-+	int i;
-+
-+	for (i = 0; i < MII_MDIO_RETRY; i++) {
-+		unsigned int busy;
-+
-+		regmap_read(priv->base, MII_ADDR_REG_ADDR, &busy);
-+		if (!(busy & MII_BUSY))
-+			return 0;
++	u32 busy;
 +
-+		udelay(MII_MDIO_DELAY);
-+	}
-+
-+	return -ETIMEDOUT;
++	return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
++					!(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
++					MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
 +}
 +
 +static int
 +ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
 +{
-+	struct ipq8064_mdio *priv = bus->priv;
 +	u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
++	struct ipq8064_mdio *priv = bus->priv;
 +	u32 ret_val;
 +	int err;
 +
++	/* Reject clause 45 */
++	if (reg_offset & MII_ADDR_C45)
++		return -EOPNOTSUPP;
++
 +	miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
 +		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
 +
 +	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
-+	udelay(10);
++	usleep_range(8, 10);
 +
 +	err = ipq8064_mdio_wait_busy(priv);
 +	if (err)
@@ -124,8 +128,12 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 +static int
 +ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
 +{
-+	struct ipq8064_mdio *priv = bus->priv;
 +	u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
++	struct ipq8064_mdio *priv = bus->priv;
++
++	/* Reject clause 45 */
++	if (reg_offset & MII_ADDR_C45)
++		return -EOPNOTSUPP;
 +
 +	regmap_write(priv->base, MII_DATA_REG_ADDR, data);
 +
@@ -133,7 +141,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 +		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
 +
 +	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
-+	udelay(10);
++	usleep_range(8, 10);
 +
 +	return ipq8064_mdio_wait_busy(priv);
 +}
@@ -157,13 +165,14 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 +	bus->parent = &pdev->dev;
 +
 +	priv = bus->priv;
-+	priv->base = syscon_node_to_regmap(np);
-+	if (IS_ERR_OR_NULL(priv->base)) {
-+		priv->base = syscon_regmap_lookup_by_phandle(np, "master");
-+		if (IS_ERR_OR_NULL(priv->base)) {
-+			pr_err("master phandle not found\n");
-+			return -EINVAL;
-+		}
++	priv->base = device_node_to_regmap(np);
++	if (IS_ERR(priv->base)) {
++		if (priv->base == ERR_PTR(-EPROBE_DEFER))
++			return -EPROBE_DEFER;
++
++		dev_err(&pdev->dev, "error getting device regmap, error=%pe\n",
++			priv->base);
++		return PTR_ERR(priv->base);
 +	}
 +
 +	ret = of_mdiobus_register(bus, np);
@@ -203,4 +212,5 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 +
 +MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
 +MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
++MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
 +MODULE_LICENSE("GPL");