ipq806x: replace pci patchset with upstream version

Changes:
- Update patches
- Update dts with new binding
    Tx term offset dropped and replaced with a new compatible

Removed:
- 0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x
    Pci init does the same exact thing (was needed in older kernel version)
- 0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B
    Rejected upstream, can't find any reason to have this. No regression with
    testing it on R7800.

Tested on R7800 (ipq8065), R7500 v2 ("ipq8064-v2")

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Paul Blazejowski <paulb@blazebox.homeip.net> [R7800]
[rebase and refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>

1 files changed, 0 insertions, 59 deletions

diff --git a/target/linux/ipq806x/patches-5.4/0071-6-PCI-qcom-Force-GEN1-support.patch b/target/linux/ipq806x/patches-5.4/0071-6-PCI-qcom-Force-GEN1-support.patch
deleted file mode 100644
index 275b7c0915..0000000000
--- a/target/linux/ipq806x/patches-5.4/0071-6-PCI-qcom-Force-GEN1-support.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001
-From: Sham Muthayyan <smuthayy@codeaurora.org>
-Date: Wed, 7 Sep 2016 16:44:28 +0530
-Subject: PCI: qcom: Force GEN1 support
-
-Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0
-Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
----
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -122,6 +122,8 @@
- #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
- #define SLV_ADDR_SPACE_SZ			0x10000000
- 
-+#define PCIE20_LNK_CONTROL2_LINK_STATUS2        0xA0
-+
- #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
- struct qcom_pcie_resources_2_1_0 {
- 	struct clk *iface_clk;
-@@ -212,6 +214,7 @@ struct qcom_pcie {
- 	struct phy *phy;
- 	struct gpio_desc *reset;
- 	const struct qcom_pcie_ops *ops;
-+	uint32_t force_gen1;
- };
- 
- #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
-@@ -504,6 +507,11 @@ static int qcom_pcie_init_2_1_0(struct q
- 
- 	/* wait for clock acquisition */
- 	usleep_range(1000, 1500);
-+	if (pcie->force_gen1) {
-+		writel_relaxed((readl_relaxed(
-+			pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
-+			pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
-+	}
- 
- 
- 	/* Set the Max TLP size to 2K, instead of using default of 4K */
-@@ -1340,6 +1348,8 @@ static int qcom_pcie_probe(struct platfo
- 	struct dw_pcie *pci;
- 	struct qcom_pcie *pcie;
- 	int ret;
-+	uint32_t force_gen1 = 0;
-+	struct device_node *np = pdev->dev.of_node;
- 
- 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
- 	if (!pcie)
-@@ -1370,6 +1380,9 @@ static int qcom_pcie_probe(struct platfo
- 		goto err_pm_runtime_put;
- 	}
- 
-+	of_property_read_u32(np, "force_gen1", &force_gen1);
-+	pcie->force_gen1 = force_gen1;
-+
- 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
- 	pcie->parf = devm_ioremap_resource(dev, res);
- 	if (IS_ERR(pcie->parf)) {