ipq806x: 5.15: replace dtsi patches with upstream version

Reorganize dtsi patches with upstream version and drop dtsi in 5.15
files.
Also add an additional upstream patch for hwspinlock support.
Refresh all the dts with needed changes.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

1 files changed, 0 insertions, 371 deletions

diff --git a/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch b/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch
deleted file mode 100644
index adc784fcfc..0000000000
--- a/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch
+++ /dev/null
@@ -1,371 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -10,6 +10,8 @@
- #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
- #include <dt-bindings/soc/qcom,gsbi.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/mfd/qcom-rpm.h>
-+#include <dt-bindings/clock/qcom,rpmcc.h>
- 
- / {
- 	#address-cells = <1>;
-@@ -30,6 +32,16 @@
- 			next-level-cache = <&L2>;
- 			qcom,acc = <&acc0>;
- 			qcom,saw = <&saw0>;
-+			clocks = <&kraitcc 0>, <&kraitcc 4>;
-+			clock-names = "cpu", "l2";
-+			clock-latency = <100000>;
-+			cpu-supply = <&smb208_s2a>;
-+			operating-points-v2 = <&opp_table0>;
-+			voltage-tolerance = <5>;
-+			cooling-min-state = <0>;
-+			cooling-max-state = <10>;
-+			#cooling-cells = <2>;
-+			cpu-idle-states = <&CPU_SPC>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -40,11 +52,125 @@
- 			next-level-cache = <&L2>;
- 			qcom,acc = <&acc1>;
- 			qcom,saw = <&saw1>;
-+			clocks = <&kraitcc 1>, <&kraitcc 4>;
-+			clock-names = "cpu", "l2";
-+			clock-latency = <100000>;
-+			cpu-supply = <&smb208_s2b>;
-+			operating-points-v2 = <&opp_table0>;
-+			voltage-tolerance = <5>;
-+			cooling-min-state = <0>;
-+			cooling-max-state = <10>;
-+			#cooling-cells = <2>;
-+			cpu-idle-states = <&CPU_SPC>;
-+ 		};
-+
-+		idle-states {
-+			CPU_SPC: spc {
-+				compatible = "qcom,idle-state-spc";
-+				status = "disabled";
-+				entry-latency-us = <400>;
-+				exit-latency-us = <900>;
-+				min-residency-us = <3000>;
-+			};
- 		};
-+	};
- 
--		L2: l2-cache {
--			compatible = "cache";
--			cache-level = <2>;
-+	opp_table_l2: opp_table_l2 {
-+		compatible = "operating-points-v2";
-+
-+		opp-384000000 {
-+			opp-hz = /bits/ 64 <384000000>;
-+			opp-microvolt = <1100000>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <0>;
-+		};
-+
-+		opp-1000000000 {
-+			opp-hz = /bits/ 64 <1000000000>;
-+			opp-microvolt = <1100000>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <1150000>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <2>;
-+		};
-+	};
-+
-+	opp_table0: opp_table0 {
-+		compatible = "operating-points-v2-kryo-cpu";
-+		nvmem-cells = <&speedbin_efuse>;
-+
-+		/*
-+		 * Voltage thresholds are <target min max>
-+		 */
-+		opp-384000000 {
-+			opp-hz = /bits/ 64 <384000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+			opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
-+			opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
-+			opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <0>;
-+		};
-+
-+		opp-600000000 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+			opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+			opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+			opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-800000000 {
-+			opp-hz = /bits/ 64 <800000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+			opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
-+			opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-1000000000 {
-+			opp-hz = /bits/ 64 <1000000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+			opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+			opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
-+			opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
-+			opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
-+			opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <2>;
-+		};
-+
-+		opp-1400000000 {
-+			opp-hz = /bits/ 64 <1400000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
-+			opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
-+			opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+			opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <2>;
- 		};
- 	};
- 
-@@ -317,6 +443,15 @@
- 		};
- 	};
- 
-+	fab-scaling {
-+		compatible = "qcom,fab-scaling";
-+		clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
-+		clock-names = "apps-fab-clk", "ddr-fab-clk";
-+		fab_freq_high = <533000000>;
-+		fab_freq_nominal = <400000000>;
-+		cpu_freq_threshold = <1000000000>;
-+	};
-+
- 	firmware {
- 		scm {
- 			compatible = "qcom,scm-ipq806x", "qcom,scm";
-@@ -384,6 +519,15 @@
- 				};
- 			};
- 
-+			i2c4_pins: i2c4_pinmux {
-+				mux {
-+					pins = "gpio12", "gpio13";
-+					function = "gsbi4";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
- 			spi_pins: spi_pins {
- 				mux {
- 					pins = "gpio18", "gpio19", "gpio21";
-@@ -437,6 +581,27 @@
- 					bias-bus-hold;
- 				};
- 			};
-+
-+			mdio0_pins: mdio0_pins {
-+				mux {
-+					pins = "gpio0", "gpio1";
-+					function = "mdio";
-+					drive-strength = <8>;
-+					bias-disable;
-+				};
-+			};
-+
-+			rgmii2_pins: rgmii2_pins {
-+				mux {
-+					pins = "gpio27", "gpio28", "gpio29",
-+					       "gpio30", "gpio31", "gpio32",
-+					       "gpio51", "gpio52", "gpio59",
-+					       "gpio60", "gpio61", "gpio62";
-+					function = "rgmii2";
-+					drive-strength = <8>;
-+					bias-disable;
-+				};
-+			};
- 		};
- 
- 		intc: interrupt-controller@2000000 {
-@@ -513,6 +678,17 @@
- 			regulator;
- 		};
- 
-+		saw_l2: regulator@02012000 {
-+			compatible = "qcom,saw2", "syscon";
-+			reg = <0x02012000 0x1000>;
-+			regulator;
-+		};
-+
-+		sic_non_secure: sic-non-secure@12100000 {
-+			compatible = "syscon";
-+			reg = <0x12100000 0x10000>;
-+		};
-+
- 		gsbi2: gsbi@12480000 {
- 			compatible = "qcom,gsbi-v1.0.0";
- 			cell-index = <2>;
-@@ -637,6 +813,33 @@
- 			};
- 		};
- 
-+		gsbi6: gsbi@16500000 {
-+			status = "disabled";
-+			compatible = "qcom,gsbi-v1.0.0";
-+			cell-index = <6>;
-+			reg = <0x16500000 0x100>;
-+			clocks = <&gcc GSBI6_H_CLK>;
-+			clock-names = "iface";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			ranges;
-+
-+			syscon-tcsr = <&tcsr>;
-+
-+			gsbi6_i2c: i2c@16580000 {
-+				compatible = "qcom,i2c-qup-v1.1.1";
-+				reg = <0x16580000 0x1000>;
-+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
-+
-+				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
-+				clock-names = "core", "iface";
-+				status = "disabled";
-+
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
-+		};
-+
- 		gsbi7: gsbi@16600000 {
- 			status = "disabled";
- 			compatible = "qcom,gsbi-v1.0.0";
-@@ -658,6 +861,19 @@
- 				clock-names = "core", "iface";
- 				status = "disabled";
- 			};
-+
-+			gsbi7_i2c: i2c@16680000 {
-+ 				compatible = "qcom,i2c-qup-v1.1.1";
-+ 				reg = <0x16680000 0x1000>;
-+				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
-+
-+ 				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
-+ 				clock-names = "core", "iface";
-+				status = "disabled";
-+
-+ 				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
- 		};
- 
- 		rng@1a500000 {
-@@ -761,6 +977,17 @@
- 			};
- 		};
- 
-+		L2: l2-cache {
-+			compatible = "qcom,krait-cache", "cache";
-+			cache-level = <2>;
-+			qcom,saw = <&saw_l2>;
-+
-+			clocks = <&kraitcc 4>;
-+			clock-names = "l2";
-+			l2-supply = <&smb208_s1a>;
-+			operating-points-v2 = <&opp_table_l2>;
-+		};
-+
- 		rpm: rpm@108000 {
- 			compatible = "qcom,rpm-ipq8064";
- 			reg = <0x108000 0x1000>;
-@@ -828,6 +1055,11 @@
- 			clock-output-names = "acpu_l2_aux";
- 		};
- 
-+		kraitcc: clock-controller {
-+			compatible = "qcom,krait-cc-v1";
-+			#clock-cells = <1>;
-+		};
-+
- 		lcc: clock-controller@28000000 {
- 			compatible = "qcom,lcc-ipq8064";
- 			reg = <0x28000000 0x1000>;
-@@ -835,6 +1067,11 @@
- 			#reset-cells = <1>;
- 		};
- 
-+		sfpb_mutex_block: syscon@1200600 {
-+			compatible = "syscon";
-+			reg = <0x01200600 0x100>;
-+		};
-+
- 		pcie0: pci@1b500000 {
- 			compatible = "qcom,pcie-ipq8064";
- 			reg = <0x1b500000 0x1000
-@@ -1184,6 +1421,21 @@
- 			};
- 		};
- 
-+
-+		mdio0: mdio@37000000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			compatible = "qcom,ipq8064-mdio", "syscon";
-+			reg = <0x37000000 0x200000>;
-+			resets = <&gcc GMAC_CORE1_RESET>;
-+			reset-names = "stmmaceth";
-+			clocks = <&gcc GMAC_CORE1_CLK>;
-+			clock-names = "stmmaceth";
-+
-+			status = "disabled";
-+		};
-+
- 		vsdcc_fixed: vsdcc-regulator {
- 			compatible = "regulator-fixed";
- 			regulator-name = "SDCC Power";
-@@ -1258,4 +1510,17 @@
- 			};
- 		};
- 	};
-+
-+	sfpb_mutex: sfpb-mutex {
-+		compatible = "qcom,sfpb-mutex";
-+		syscon = <&sfpb_mutex_block 4 4>;
-+
-+		#hwlock-cells = <1>;
-+	};
-+
-+	smem {
-+		compatible = "qcom,smem";
-+		memory-region = <&smem>;
-+		hwlocks = <&sfpb_mutex 3>;
-+	};
- };