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| author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-03-28 14:17:36 +0200 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2021-05-07 07:05:16 +0200 |
| commit | 1e25423be8acb38e979cd5a38abb1ca4cac2837e (patch) | |
| tree | 1b502fefc27746b49975670fa346c294a474cd2b /target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch | |
| parent | 62cc66fa6737de50d6aa57042f9508fccd476ed7 (diff) | |
| download | upstream-1e25423be8acb38e979cd5a38abb1ca4cac2837e.tar.gz upstream-1e25423be8acb38e979cd5a38abb1ca4cac2837e.tar.bz2 upstream-1e25423be8acb38e979cd5a38abb1ca4cac2837e.zip | |
ipq806x: refresh dtsi patches
- Add new tsens node
- Add new cpufreq required nodes
- Drop arm cpuidle compatible
- Fix duplicate node set upstream
- Add voltage tolerance value for cpu opp
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Diffstat (limited to 'target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch | 58 |
1 files changed, 55 insertions, 3 deletions
diff --git a/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch b/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch index 568ca5bb88..9c16ee4351 100644 --- a/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch +++ b/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -20,7 +20,7 @@ +@@ -20,9 +20,9 @@ #address-cells = <1>; #size-cells = <0>; @@ -9,7 +9,9 @@ compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; -@@ -30,7 +30,7 @@ + reg = <1>; + next-level-cache = <&L2>; +@@ -30,9 +30,9 @@ qcom,saw = <&saw0>; }; @@ -18,6 +20,8 @@ compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; @@ -67,7 +67,7 @@ no-map; }; @@ -27,6 +31,14 @@ reg = <0x41000000 0x200000>; no-map; }; +@@ -128,6 +128,7 @@ + gpio-ranges = <&qcom_pinmux 0 0 69>; + #gpio-cells = <2>; + interrupt-controller; ++ #address-cells = <0>; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + @@ -155,6 +155,7 @@ function = "pcie3_rst"; drive-strength = <12>; @@ -35,6 +47,14 @@ }; }; +@@ -190,6 +190,7 @@ + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; ++ #address-cells = <0>; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; @@ -219,21 +220,23 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; @@ -88,11 +108,43 @@ compatible = "qcom,ipq806x-ahci", "generic-ahci"; reg = <0x29000000 0x180>; -@@ -430,6 +433,7 @@ +@@ -430,6 +430,16 @@ qfprom: qfprom@700000 { + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ tsens_calib: calib@400 { ++ reg = <0x400 0xb>; ++ }; ++ tsens_backup: backup@410 { ++ reg = <0x410 0xb>; ++ }; ++ speedbin_efuse: speedbin@0c0 { ++ reg = <0x0c0 0x4>; ++ }; + }; + + gcc: clock-controller@900000 { +@@ -437,9 +447,21 @@ gcc: clock-controller@900000 { + + gcc: clock-controller@900000 { +- compatible = "qcom,gcc-ipq8064"; ++ compatible = "qcom,gcc-ipq8064", "syscon"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; ++ ++ tsens: thermal-sensor@900000 { ++ compatible = "qcom,ipq8064-tsens"; ++ ++ nvmem-cells = <&tsens_calib>, <&tsens_backup>; ++ nvmem-cell-names = "calib", "calib_backup"; ++ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "uplow"; ++ #thermal-sensor-cells = <1>; ++ #qcom,sensors = <11>; ++ }; }; tcsr: syscon@1a400000 { |