ipq806x: fix wireless regression

In current state there's huge regression on ipq806x target that causes the device to transmit broken/malformed frames that are not corrected/detected by error control mechanisms and other less severe issues.
https://bugs.lede-project.org/index.php?do=details&task_id=1197

This finally had been narrowed down to patch 0071-pcie-qcom-fixes.patch

Meanwhile QSDK contains a handful of commits that add support for ipq806x to upstream qcom pcie driver
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/log/drivers/pci/host/pcie-qcom.c?h=eggplant
Unfortunately qca developers do not bother to push it upstream.

Using those commits instead of lede 0071 patch fixes mentioned issue and probably many others as it seems that corrupted data has been originating within pcie misconfiguration.

Fixes: FS#1197 and probably others
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>

1 files changed, 61 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches-4.9/0071-6-PCI-qcom-Force-GEN1-support.patch b/target/linux/ipq806x/patches-4.9/0071-6-PCI-qcom-Force-GEN1-support.patch
new file mode 100644
index 0000000000..91891a5b21
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.9/0071-6-PCI-qcom-Force-GEN1-support.patch
@@ -0,0 +1,61 @@
+From 4910cfd150342ec7b038892262923c725a9c4001 Mon Sep 17 00:00:00 2001
+From: Sham Muthayyan <smuthayy@codeaurora.org>
+Date: Wed, 7 Sep 2016 16:44:28 +0530
+Subject: PCI: qcom: Force GEN1 support
+
+Change-Id: Ica54ddb737d7b851469deab1745f54bf431bd3f0
+Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+---
+ drivers/pci/host/pcie-qcom.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -90,6 +90,8 @@
+ #define PCIE20_PARF_CONFIG_BITS			0x50
+ #define PHY_RX0_EQ(x)				(x << 24)
+ 
++#define PCIE20_LNK_CONTROL2_LINK_STATUS2        0xA0
++
+ struct qcom_pcie_resources_v0 {
+ 	struct clk *iface_clk;
+ 	struct clk *core_clk;
+@@ -138,6 +140,7 @@ struct qcom_pcie {
+ 	struct phy *phy;
+ 	struct gpio_desc *reset;
+ 	struct qcom_pcie_ops *ops;
++	uint32_t force_gen1;
+ };
+ 
+ #define to_qcom_pcie(x)		container_of(x, struct qcom_pcie, pp)
+@@ -477,6 +480,11 @@ static int qcom_pcie_init_v0(struct qcom
+ 
+ 	/* wait for clock acquisition */
+ 	usleep_range(1000, 1500);
++	if (pcie->force_gen1) {
++		writel_relaxed((readl_relaxed(
++			pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
++			pcie->pp.dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
++	}
+ 
+ 	qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
+ 	qcom_pcie_prog_viewport_mem2_outbound(pcie);
+@@ -666,6 +674,8 @@ static int qcom_pcie_probe(struct platfo
+ 	struct qcom_pcie *pcie;
+ 	struct pcie_port *pp;
+ 	int ret;
++	uint32_t force_gen1 = 0;
++	struct device_node *np = pdev->dev.of_node;
+ 
+ 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ 	if (!pcie)
+@@ -678,6 +688,9 @@ static int qcom_pcie_probe(struct platfo
+ 	if (IS_ERR(pcie->reset))
+ 		return PTR_ERR(pcie->reset);
+ 
++	of_property_read_u32(np, "force_gen1", &force_gen1);
++	pcie->force_gen1 = force_gen1;
++
+ 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
+ 	pcie->parf = devm_ioremap_resource(dev, res);
+ 	if (IS_ERR(pcie->parf))