diff options
author | John Crispin <john@phrozen.org> | 2017-03-13 13:30:10 +0100 |
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committer | Felix Fietkau <nbd@nbd.name> | 2017-03-13 13:40:55 +0100 |
commit | 1adf51702e94063fb058ce13226ec5a04d15cfd4 (patch) | |
tree | 00fb0f446f516289abb93ff78f103294254545c3 /target/linux/ipq806x/patches-4.9/0068-spi-add-gpio-cs-support.patch | |
parent | 99b6aefd638c7934136ffcde271e6fc3f4f6c464 (diff) | |
download | upstream-1adf51702e94063fb058ce13226ec5a04d15cfd4.tar.gz upstream-1adf51702e94063fb058ce13226ec5a04d15cfd4.tar.bz2 upstream-1adf51702e94063fb058ce13226ec5a04d15cfd4.zip |
ipq806x: clean up patches, port missing patches from 4.4
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ipq806x/patches-4.9/0068-spi-add-gpio-cs-support.patch')
-rw-r--r-- | target/linux/ipq806x/patches-4.9/0068-spi-add-gpio-cs-support.patch | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-4.9/0068-spi-add-gpio-cs-support.patch b/target/linux/ipq806x/patches-4.9/0068-spi-add-gpio-cs-support.patch new file mode 100644 index 0000000000..0c03bc9f71 --- /dev/null +++ b/target/linux/ipq806x/patches-4.9/0068-spi-add-gpio-cs-support.patch @@ -0,0 +1,71 @@ +From b9c998eb7735df8000cf48d77f9271823e8e73da Mon Sep 17 00:00:00 2001 +From: Ram Chandra Jangir <rjangi@codeaurora.org> +Date: Thu, 9 Mar 2017 09:39:05 +0100 +Subject: [PATCH 68/69] spi: add gpio cs support + +Signed-off-by: John Crispin <john@phrozen.org> +--- + drivers/spi/spi-qup.c | 38 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/drivers/spi/spi-qup.c ++++ b/drivers/spi/spi-qup.c +@@ -24,6 +24,7 @@ + #include <linux/spi/spi.h> + #include <linux/dmaengine.h> + #include <linux/dma-mapping.h> ++#include <linux/gpio.h> + + #define QUP_CONFIG 0x0000 + #define QUP_STATE 0x0004 +@@ -1019,6 +1020,38 @@ err_tx: + return ret; + } + ++static void spi_qup_set_cs(struct spi_device *spi, bool val) ++{ ++ struct spi_qup *controller; ++ u32 spi_ioc; ++ u32 spi_ioc_orig; ++ ++ controller = spi_master_get_devdata(spi->master); ++ spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); ++ spi_ioc_orig = spi_ioc; ++ if (!val) ++ spi_ioc |= SPI_IO_C_FORCE_CS; ++ else ++ spi_ioc &= ~SPI_IO_C_FORCE_CS; ++ ++ if (spi_ioc != spi_ioc_orig) ++ writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); ++} ++ ++static int spi_qup_setup(struct spi_device *spi) ++{ ++ if (spi->cs_gpio >= 0) { ++ if (spi->mode & SPI_CS_HIGH) ++ gpio_set_value(spi->cs_gpio, 0); ++ else ++ gpio_set_value(spi->cs_gpio, 1); ++ ++ udelay(10); ++ } ++ ++ return 0; ++} ++ + static int spi_qup_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -1115,6 +1148,11 @@ static int spi_qup_probe(struct platform + if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1")) + controller->qup_v1 = 1; + ++ if (!controller->qup_v1) ++ master->set_cs = spi_qup_set_cs; ++ else ++ master->setup = spi_qup_setup; ++ + spin_lock_init(&controller->lock); + init_completion(&controller->done); + init_completion(&controller->dma_tx_done); |