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authorJohn Crispin <john@phrozen.org>2017-03-13 13:30:10 +0100
committerFelix Fietkau <nbd@nbd.name>2017-03-13 13:40:55 +0100
commit1adf51702e94063fb058ce13226ec5a04d15cfd4 (patch)
tree00fb0f446f516289abb93ff78f103294254545c3 /target/linux/ipq806x/patches-4.9/0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch
parent99b6aefd638c7934136ffcde271e6fc3f4f6c464 (diff)
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ipq806x: clean up patches, port missing patches from 4.4
Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ipq806x/patches-4.9/0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch')
-rw-r--r--target/linux/ipq806x/patches-4.9/0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch107
1 files changed, 107 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-4.9/0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch b/target/linux/ipq806x/patches-4.9/0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch
new file mode 100644
index 0000000000..f4a47c7ba3
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.9/0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch
@@ -0,0 +1,107 @@
+From 88e1d6d9c113fe50810d1b03eb1fdbf015e5d1bd Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <sboyd@codeaurora.org>
+Date: Fri, 20 Mar 2015 23:45:22 -0700
+Subject: [PATCH 36/69] clk: Avoid sending high rates to downstream clocks
+ during set_rate
+
+If a clock is on and we call clk_set_rate() on it we may get into
+a situation where the clock temporarily increases in rate
+dramatically while we walk the tree and call .set_rate() ops. For
+example, consider a case where a PLL feeds into a divider.
+Initially the divider is set to divide by 1 and the PLL is
+running fairly slow (100MHz). The downstream consumer of the
+divider output can only handle rates =< 400 MHz, but the divider
+can only choose between divisors of 1 and 4.
+
+ +-----+ +----------------+
+ | PLL |-->| div 1 or div 4 |---> consumer device
+ +-----+ +----------------+
+
+To achieve a rate of 400MHz on the output of the divider, we
+would have to set the rate of the PLL to 1.6 GHz and then divide
+it by 4. The current code would set the PLL to 1.6GHz first while
+the divider is still set to 1, thus causing the downstream
+consumer of the clock to receive a few clock cycles of 1.6GHz
+clock (far beyond it's maximum acceptable rate). We should be
+changing the divider first before increasing the PLL rate to
+avoid this problem.
+
+Therefore, set the rate of any child clocks that are increasing
+in rate from their current rate so that they can increase their
+dividers if necessary. We assume that there isn't such a thing as
+minimum rate requirements.
+
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+
+Conflicts:
+ drivers/clk/clk.c
+---
+ drivers/clk/clk.c | 22 +++++++++++++++-------
+ 1 file changed, 15 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -1466,12 +1466,12 @@ static struct clk_core *clk_propagate_ra
+ * walk down a subtree and set the new rates notifying the rate
+ * change on the way
+ */
+-static void clk_change_rate(struct clk_core *core)
++static void
++clk_change_rate(struct clk_core *core, unsigned long best_parent_rate)
+ {
+ struct clk_core *child;
+ struct hlist_node *tmp;
+ unsigned long old_rate;
+- unsigned long best_parent_rate = 0;
+ bool skip_set_rate = false;
+ struct clk_core *old_parent;
+ struct clk_core *parent = NULL;
+@@ -1523,6 +1523,7 @@ static void clk_change_rate(struct clk_c
+ trace_clk_set_rate_complete(core, core->new_rate);
+
+ core->rate = clk_recalc(core, best_parent_rate);
++ core->rate = core->new_rate;
+
+ if (core->flags & CLK_SET_RATE_UNGATE) {
+ unsigned long flags;
+@@ -1550,12 +1551,13 @@ static void clk_change_rate(struct clk_c
+ /* Skip children who will be reparented to another clock */
+ if (child->new_parent && child->new_parent != core)
+ continue;
+- clk_change_rate(child);
++ if (child->new_rate != child->rate)
++ clk_change_rate(child, core->new_rate);
+ }
+
+- /* handle the new child who might not be in core->children yet */
+- if (core->new_child)
+- clk_change_rate(core->new_child);
++ /* handle the new child who might not be in clk->children yet */
++ if (core->new_child && core->new_child->new_rate != core->new_child->rate)
++ clk_change_rate(core->new_child, core->new_rate);
+ }
+
+ static int clk_core_set_rate_nolock(struct clk_core *core,
+@@ -1563,6 +1565,7 @@ static int clk_core_set_rate_nolock(stru
+ {
+ struct clk_core *top, *fail_clk;
+ unsigned long rate = req_rate;
++ unsigned long parent_rate;
+
+ if (!core)
+ return 0;
+@@ -1588,8 +1591,13 @@ static int clk_core_set_rate_nolock(stru
+ return -EBUSY;
+ }
+
++ if (top->parent)
++ parent_rate = top->parent->rate;
++ else
++ parent_rate = 0;
++
+ /* change the rates */
+- clk_change_rate(top);
++ clk_change_rate(top, parent_rate);
+
+ core->req_rate = req_rate;
+