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author | Pavel Kubelun <be.dissent@gmail.com> | 2017-12-09 20:15:05 +0300 |
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committer | Felix Fietkau <nbd@nbd.name> | 2018-01-17 11:02:05 +0100 |
commit | 7903a9219c7eb5d14c62f79d4a70f5cab1c6294f (patch) | |
tree | d72252a2bc48c698d89a28b7b923da0b1b115827 /target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch | |
parent | 83499bef73cc67b9290360cf76c345a7b3c29f08 (diff) | |
download | upstream-7903a9219c7eb5d14c62f79d4a70f5cab1c6294f.tar.gz upstream-7903a9219c7eb5d14c62f79d4a70f5cab1c6294f.tar.bz2 upstream-7903a9219c7eb5d14c62f79d4a70f5cab1c6294f.zip |
ipq806x: update clk and cpufreq drivers
A newer clk and cpufreq drivers for ipq806x platform had been sent upstream.
A change that i have noticed is that now it's possible to set min, cur and max frequencies from sysfs (previously it was bugged and caused nothing).
Following patches are removed:
- 0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch - seems it was dropped from the patchset by current committer.
- 0044-clk-qcom-krait-Remove-CLK_IS_ROOT.patch - already applied to the driver itself in the corresponding patch.
- 0057-clk-qcom-Add-regmap-mux-div-clocks-support.patch - seem to be irrelevant to ipq806x.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Diffstat (limited to 'target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch')
-rw-r--r-- | target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch | 55 |
1 files changed, 29 insertions, 26 deletions
diff --git a/target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch b/target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch index 426cabd4e4..5a64e6c56e 100644 --- a/target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch +++ b/target/linux/ipq806x/patches-4.9/0035-clk-mux-Split-out-register-accessors-for-reuse.patch @@ -1,7 +1,19 @@ -From 9d381d65eae163d8f50d97a3ad9033bba176f62b Mon Sep 17 00:00:00 2001 +From patchwork Fri Dec 8 09:42:20 2017 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v4,02/12] clk: mux: Split out register accessors for reuse +From: Sricharan R <sricharan@codeaurora.org> +X-Patchwork-Id: 10102103 +Message-Id: <1512726150-7204-3-git-send-email-sricharan@codeaurora.org> +To: mturquette@baylibre.com, sboyd@codeaurora.org, + devicetree@vger.kernel.org, linux-pm@vger.kernel.org, + linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org +Cc: sricharan@codeaurora.org +Date: Fri, 8 Dec 2017 15:12:20 +0530 + From: Stephen Boyd <sboyd@codeaurora.org> -Date: Fri, 20 Mar 2015 23:45:21 -0700 -Subject: [PATCH 35/69] clk: mux: Split out register accessors for reuse We want to reuse the logic in clk-mux.c for other clock drivers that don't use readl as register accessors. Fortunately, there @@ -12,28 +24,25 @@ that operate on an optional table and some flags so that other drivers can use the same logic. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> -Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> --- - drivers/clk/clk-mux.c | 76 ++++++++++++++++++++++++++++---------------- - include/linux/clk-provider.h | 11 +++++-- - 2 files changed, 57 insertions(+), 30 deletions(-) + drivers/clk/clk-mux.c | 75 +++++++++++++++++++++++++++----------------- + include/linux/clk-provider.h | 9 ++++-- + 2 files changed, 54 insertions(+), 30 deletions(-) --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c -@@ -26,35 +26,27 @@ +@@ -26,35 +26,24 @@ * parent - parent is adjustable through clk_set_parent */ -static u8 clk_mux_get_parent(struct clk_hw *hw) -+#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) -+ +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val, + unsigned int *table, unsigned long flags) { - struct clk_mux *mux = to_clk_mux(hw); +- struct clk_mux *mux = to_clk_mux(hw); int num_parents = clk_hw_get_num_parents(hw); - u32 val; - +- - /* - * FIXME need a mux-specific flag to determine if val is bitwise or numeric - * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 @@ -43,7 +52,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> - */ - val = clk_readl(mux->reg) >> mux->shift; - val &= mux->mask; -- + - if (mux->table) { + if (table) { int i; @@ -64,7 +73,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> val--; if (val >= num_parents) -@@ -62,23 +54,53 @@ static u8 clk_mux_get_parent(struct clk_ +@@ -62,23 +51,53 @@ static u8 clk_mux_get_parent(struct clk_ return val; } @@ -80,9 +89,9 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> - if (mux->table) { - index = mux->table[index]; + /* -+ * FIXME need a mux-specific flag to determine if val is bitwise or numeric -+ * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 -+ * to 0x7 (index starts at one) ++ * FIXME need a mux-specific flag to determine if val is bitwise or ++ * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide, ++ * but ranges from 0x1 to 0x7 (index starts at one) + * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so + * val = 0x4 really means "bit 2, index starts at bit 0" + */ @@ -126,7 +135,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> if (mux->lock) spin_lock_irqsave(mux->lock, flags); else -@@ -102,14 +124,14 @@ static int clk_mux_set_parent(struct clk +@@ -102,14 +121,14 @@ static int clk_mux_set_parent(struct clk } const struct clk_ops clk_mux_ops = { @@ -143,7 +152,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> }; EXPORT_SYMBOL_GPL(clk_mux_ro_ops); -@@ -117,7 +139,7 @@ struct clk_hw *clk_hw_register_mux_table +@@ -117,7 +136,7 @@ struct clk_hw *clk_hw_register_mux_table const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, @@ -175,13 +184,7 @@ Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> struct clk *clk_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, -@@ -499,12 +504,12 @@ struct clk *clk_register_mux_table(struc - const char * const *parent_names, u8 num_parents, - unsigned long flags, - void __iomem *reg, u8 shift, u32 mask, -- u8 clk_mux_flags, u32 *table, spinlock_t *lock); -+ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock); - struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, +@@ -504,7 +509,7 @@ struct clk_hw *clk_hw_register_mux_table const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, |