ipq806x: Add support for linux-4.4

1)Changes

- Rebased the patches for linux-4.4.7
- Added patch to fix spi nor fifo and dma support
- Added patch to configure watchdog barktime

2)Testing

Tested on IPQ AP148 Board:
 a. NOR boot and NAND boot
 b. ethernet network and ath10k wifi
 c. ubi sysupgrade

UnTested
 dwc3 usb has not been validated on IPQ board(AP148)

3)Known Issues:
 Once we flash ubi image on AP148, and if we reset the board, uboot on
 first boot creates PEB and LEB for dynamic sized partitions, which is incorrect
 and not what linux expects which causes errors when trying to mount rootfs.
 In order to test this, we can use the below steps:
  a. Flash the ubi image on board and don't reset the board
  b. load the kernel fit image in RAM and boot from there.

Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>

1 files changed, 134 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches-4.4/709-spi-qup-Fix-fifo-and-dma-support-for-IPQ806x.patch b/target/linux/ipq806x/patches-4.4/709-spi-qup-Fix-fifo-and-dma-support-for-IPQ806x.patch
new file mode 100644
index 0000000000..8c4718e2a6
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.4/709-spi-qup-Fix-fifo-and-dma-support-for-IPQ806x.patch
@@ -0,0 +1,134 @@
+From 16d2871830ff3fe12a6bff582549a9264adff278 Mon Sep 17 00:00:00 2001
+From: Ram Chandra Jangir <rjangi@codeaurora.org>
+Date: Tue, 10 May 2016 20:19:31 +0530
+Subject: [PATCH] spi: qup: Fix fifo and dma support for IPQ806x
+
+Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
+---
+ drivers/spi/spi-qup.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 52 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
+index 810a7fa..0808017 100644
+--- a/drivers/spi/spi-qup.c
++++ b/drivers/spi/spi-qup.c
+@@ -24,6 +24,7 @@
+ #include <linux/spi/spi.h>
+ #include <linux/dmaengine.h>
+ #include <linux/dma-mapping.h>
++#include <linux/gpio.h>
+ 
+ #define QUP_CONFIG			0x0000
+ #define QUP_STATE			0x0004
+@@ -152,6 +153,7 @@ struct spi_qup {
+ 	int			use_dma;
+ 	struct dma_slave_config	rx_conf;
+ 	struct dma_slave_config	tx_conf;
++	int mode;
+ };
+ 
+ 
+@@ -370,7 +372,8 @@ static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
+ 		return ret;
+ 	}
+ 
+-	spi_qup_fifo_write(qup, xfer);
++	if (qup->mode == QUP_IO_M_MODE_FIFO)
++		spi_qup_fifo_write(qup, xfer);
+ 
+ 	return 0;
+ }
+@@ -448,6 +451,7 @@ spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
+ {
+ 	struct spi_qup *qup = spi_master_get_devdata(master);
+ 	u32 mode;
++	size_t dma_align = dma_get_cache_alignment();
+ 
+ 	qup->w_size = 4;
+ 
+@@ -458,6 +462,14 @@ spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
+ 
+ 	qup->n_words = xfer->len / qup->w_size;
+ 
++	if (!IS_ERR_OR_NULL(master->dma_rx) &&
++			IS_ALIGNED((size_t)xfer->tx_buf, dma_align) &&
++			IS_ALIGNED((size_t)xfer->rx_buf, dma_align) &&
++			!is_vmalloc_addr(xfer->tx_buf) &&
++			!is_vmalloc_addr(xfer->rx_buf) &&
++			(xfer->len > 3*qup->in_blk_sz))
++		qup->use_dma = 1;
++
+ 	if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
+ 		mode = QUP_IO_M_MODE_FIFO;
+ 	else
+@@ -491,7 +503,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
+ 		return -EIO;
+ 	}
+ 
+-	mode = spi_qup_get_mode(spi->master, xfer);
++	controller->mode = mode = spi_qup_get_mode(spi->master, xfer);
+ 	n_words = controller->n_words;
+ 
+ 	if (mode == QUP_IO_M_MODE_FIFO) {
+@@ -500,6 +512,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
+ 		/* must be zero for FIFO */
+ 		writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
+ 		writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
++		controller->use_dma = 0;
+ 	} else if (!controller->use_dma) {
+ 		writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
+ 		writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
+@@ -750,6 +763,38 @@ err_tx:
+ 	return ret;
+ }
+ 
++static void spi_qup_set_cs(struct spi_device *spi, bool val)
++{
++	struct spi_qup *controller;
++	u32 spi_ioc;
++	u32 spi_ioc_orig;
++
++	controller = spi_master_get_devdata(spi->master);
++	spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
++	spi_ioc_orig = spi_ioc;
++	if (!val)
++		spi_ioc |= SPI_IO_C_FORCE_CS;
++	else
++		spi_ioc &= ~SPI_IO_C_FORCE_CS;
++
++	if (spi_ioc != spi_ioc_orig)
++		writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
++}
++
++static int spi_qup_setup(struct spi_device *spi)
++{
++	if (spi->cs_gpio >= 0) {
++		if (spi->mode & SPI_CS_HIGH)
++			gpio_set_value(spi->cs_gpio, 0);
++		else
++			gpio_set_value(spi->cs_gpio, 1);
++
++		udelay(10);
++	}
++
++	return 0;
++}
++
+ static int spi_qup_probe(struct platform_device *pdev)
+ {
+ 	struct spi_master *master;
+@@ -846,6 +891,11 @@ static int spi_qup_probe(struct platform_device *pdev)
+ 	if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
+ 		controller->qup_v1 = 1;
+ 
++	if (!controller->qup_v1)
++		master->set_cs = spi_qup_set_cs;
++	else
++		master->setup = spi_qup_setup;
++
+ 	spin_lock_init(&controller->lock);
+ 	init_completion(&controller->done);
+ 
+-- 
+2.7.2
+