ipq806x: refresh 4.19 patches

Reworked:

 - 0034 patchset update

Added:

 - 080 Add support for pinctrl-msm framework

Removed:

 - 0074-ipq806x-usb-Control-USB-master-reset.patch
   (we now have a dedicated driver for qcom usb)

 - 0047-mtd-nand-Create-a-BBT-flag-to-access-bad-block-marke
   (merged upstream)

 - 310-msm-adhoc-bus-support
   (it looks like it was never actually used in any dts)

Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
[commit subject and description facelift, SoB fix]
Signed-off-by: Petr Štetiar <ynezz@true.cz>

1 files changed, 12 insertions, 14 deletions

diff --git a/target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch b/target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch
index 57ee082c83..dde8fbaa7b 100644
--- a/target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch
+++ b/target/linux/ipq806x/patches-4.19/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch
@@ -6,12 +6,10 @@ Subject: PCI: qcom: Fixed IPQ806x PCIE init changes
 Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e
 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
 ---
- drivers/pci/host/pcie-qcom.c | 62 +++++++++++++++++++++++++++++++++++++-------
- 1 file changed, 53 insertions(+), 9 deletions(-)
 
---- a/drivers/pci/dwc/pcie-qcom.c
-+++ b/drivers/pci/dwc/pcie-qcom.c
-@@ -52,7 +52,13 @@
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -45,7 +45,13 @@
  #define PCIE_CAP_CPL_TIMEOUT_DISABLE		0x10
  
  #define PCIE20_PARF_PHY_CTRL			0x40
@@ -25,7 +23,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  #define PCIE20_PARF_DBI_BASE_ADDR		0x168
  #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
  #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
-@@ -83,6 +89,18 @@
+@@ -76,6 +82,18 @@
  #define DBI_RO_WR_EN				1
  
  #define PERST_DELAY_US				1000
@@ -44,15 +42,15 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  
  #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
  #define SLV_ADDR_SPACE_SZ			0x10000000
-@@ -102,6 +120,7 @@ struct qcom_pcie_resources_2_1_0 {
- 	struct regulator *vdda;
- 	struct regulator *vdda_phy;
- 	struct regulator *vdda_refclk;
+@@ -94,6 +112,7 @@ struct qcom_pcie_resources_2_1_0 {
+ 	struct reset_control *phy_reset;
+ 	struct reset_control *ext_reset;
+ 	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
 +	uint8_t phy_tx0_term_offset;
  };
  
  struct qcom_pcie_resources_1_0_0 {
-@@ -179,6 +198,16 @@ struct qcom_pcie {
+@@ -173,6 +192,16 @@ struct qcom_pcie {
  
  #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
  
@@ -69,7 +67,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
  {
  	gpiod_set_value_cansleep(pcie->reset, 1);
-@@ -280,6 +309,10 @@ static int qcom_pcie_get_resources_2_1_0
+@@ -266,6 +295,10 @@ static int qcom_pcie_get_resources_2_1_0
  	if (IS_ERR(res->ext_reset))
  		return PTR_ERR(res->ext_reset);
  
@@ -80,7 +78,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
  	return PTR_ERR_OR_ZERO(res->phy_reset);
  }
-@@ -309,7 +342,6 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -293,7 +326,6 @@ static int qcom_pcie_init_2_1_0(struct q
  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
  	struct dw_pcie *pci = pcie->pci;
  	struct device *dev = pci->dev;
@@ -88,7 +86,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  	int ret;
  
  	ret = reset_control_assert(res->ahb_reset);
-@@ -378,15 +410,26 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -350,15 +382,26 @@ static int qcom_pcie_init_2_1_0(struct q
  		goto err_deassert_ahb;
  	}