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authorStijn Segers <foss@volatilesystems.org>2018-06-05 23:29:31 +0200
committerJohn Crispin <john@phrozen.org>2018-06-07 09:03:24 +0200
commit1199a91095269969ba5256702359fba97c6ada08 (patch)
treeb53399707c15dfc52d354a1e2757e3c81940fe79 /target/linux/ipq806x/patches-4.14/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch
parent6f8eb1b50fd8549524de3be3c540fe917b102393 (diff)
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kernel: bump 4.14 to 4.14.48 for 18.06
Refreshed patches. The following patches were upstreamed and have been deleted: * target/linux/lantiq/patches-4.14/0025-MIPS-lantiq-gphy-Remove-reboot-remove-reset-asserts.patch * target/linux/generic/pending-4.14/101-clocksource-mips-gic-timer-fix-clocksource-counter-w.patch * target/linux/generic/pending-4.14/103-MIPS-c-r4k-fix-data-corruption-related-to-cache-coherence.patch * target/linux/generic/pending-4.14/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch Compile-tested: ramips/mt7621, x86/64 Run-tested: ramips/mt7621 Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Diffstat (limited to 'target/linux/ipq806x/patches-4.14/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch')
-rw-r--r--target/linux/ipq806x/patches-4.14/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch18
1 files changed, 9 insertions, 9 deletions
diff --git a/target/linux/ipq806x/patches-4.14/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch b/target/linux/ipq806x/patches-4.14/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch
index c70cd0bf86..c7dfd53cb1 100644
--- a/target/linux/ipq806x/patches-4.14/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch
+++ b/target/linux/ipq806x/patches-4.14/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch
@@ -17,9 +17,9 @@ Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -131,6 +131,14 @@
-
+
#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
-
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1))
+#define PCIE20_DEV_CAS 0x78
@@ -29,12 +29,12 @@ Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
+#define PCIE20_MPS(x) __set(x, 7, 5)
+
struct qcom_pcie_resources_2_1_0 {
- struct clk *iface_clk;
- struct clk *core_clk;
-@@ -1472,6 +1480,35 @@
- return 0;
+ struct clk *iface_clk;
+ struct clk *core_clk;
+@@ -1472,6 +1480,35 @@ static int qcom_pcie_probe(struct platfo
+ return 0;
}
-
+
+static void qcom_pcie_fixup_final(struct pci_dev *dev)
+{
+ int cap, err;
@@ -65,5 +65,5 @@ Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final);
+
static const struct of_device_id qcom_pcie_match[] = {
- { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
- { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
+ { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },