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authorFelix Fietkau <nbd@openwrt.org>2015-08-04 23:10:03 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-08-04 23:10:03 +0000
commit0f7de49fa37859b46de8d4e25163cfebe3db3a96 (patch)
tree3ab73a7d7dfe50d4cff826d16619d16cd2f58062 /target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
parentf7651fdba51fae235bb9e43fcecc0478faf927d0 (diff)
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ipq806x: fix freeze in PCIe code when booting with an old u-boot
Old bootloader (same ones which have DT disabled) don't perform any PCIe initialization. The consequence is a freeze during PCIe bring-up on these old u-boot. Same kernel with a newer bootloaders works fine as they contain the corresponding PCIe init code. In this change, we'll add the missing init and make sure the kernel doesn't rely on some preexisting init to get PCIe to work. That includes the following changes: *GPIOs: set function & drive strength *Clocks: add init code for aux & ref clocks *PCIe driver: additional init of the hardware controller Tested 3.18 and 4.1 on an AP148 with bootloader branch 0.0.1 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46557
Diffstat (limited to 'target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch')
-rw-r--r--target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch23
1 files changed, 14 insertions, 9 deletions
diff --git a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index df96ad5878..fc2fe0a460 100644
--- a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -15,14 +15,15 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -35,6 +35,22 @@
+@@ -35,6 +35,24 @@
bias-disable;
};
+ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
-+ drive-strength = <2>;
++ function = "pcie1_rst";
++ drive-strength = <12>;
+ bias-disable;
+ };
+ };
@@ -30,7 +31,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
-+ drive-strength = <2>;
++ function = "pcie2_rst";
++ drive-strength = <12>;
+ bias-disable;
+ };
+ };
@@ -38,7 +40,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
-@@ -114,5 +130,19 @@
+@@ -114,5 +132,19 @@
sata@29000000 {
status = "ok";
};
@@ -60,14 +62,15 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -30,6 +30,30 @@
+@@ -30,6 +30,33 @@
bias-disable;
};
+ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
-+ drive-strength = <2>;
++ function = "pcie1_rst";
++ drive-strength = <12>;
+ bias-disable;
+ };
+ };
@@ -75,7 +78,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
-+ drive-strength = <2>;
++ function = "pcie2_rst";
++ drive-strength = <12>;
+ bias-disable;
+ };
+ };
@@ -83,7 +87,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie2_pins: pcie2_pinmux {
+ mux {
+ pins = "gpio63";
-+ drive-strength = <2>;
++ function = "pcie3_rst";
++ drive-strength = <12>;
+ bias-disable;
+ };
+ };
@@ -91,7 +96,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
-@@ -128,5 +152,26 @@
+@@ -128,5 +155,26 @@
usb30@1 {
status = "ok";
};