diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2015-08-07 08:36:31 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-08-07 08:36:31 +0000 |
| commit | d523866eb39d8957fa16e05ebabf04101bfb5f85 (patch) | |
| tree | f65a1d5f5f46c64ba2e4b3f4f7602e6b300fec7c /target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch | |
| parent | c7bf2accc94e081fab0c595c7e5ddd70cfe6b0c1 (diff) | |
| download | upstream-d523866eb39d8957fa16e05ebabf04101bfb5f85.tar.gz upstream-d523866eb39d8957fa16e05ebabf04101bfb5f85.tar.bz2 upstream-d523866eb39d8957fa16e05ebabf04101bfb5f85.zip | |
ipq806x: add NAND flash controller support
These patches add support for ipq806x NAND flash controller. Most of
these are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/8/3/16
This patch just modifies the kernel code, but doesn't change the config.
It should be harmless.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46568
Diffstat (limited to 'target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch b/target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch index d7d6b69d15..22d28ac638 100644 --- a/target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch +++ b/target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch @@ -86,7 +86,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, -@@ -2239,6 +2290,472 @@ static struct clk_branch usb_fs1_h_clk = +@@ -2269,6 +2320,472 @@ static struct clk_branch ebi2_aon_clk = }, }; @@ -559,7 +559,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, -@@ -2247,6 +2764,7 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2277,6 +2794,7 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL8_VOTE] = &pll8_vote, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, @@ -567,7 +567,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, -@@ -2344,6 +2862,18 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2376,6 +2894,18 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, @@ -586,7 +586,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -@@ -2462,6 +2992,48 @@ static const struct qcom_reset_map gcc_i +@@ -2494,6 +3024,48 @@ static const struct qcom_reset_map gcc_i [USB30_1_PHY_RESET] = { 0x3b58, 0 }, [NSSFB0_RESET] = { 0x3b60, 6 }, [NSSFB1_RESET] = { 0x3b60, 7 }, @@ -635,7 +635,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> }; static const struct regmap_config gcc_ipq806x_regmap_config = { -@@ -2490,6 +3062,8 @@ static int gcc_ipq806x_probe(struct plat +@@ -2522,6 +3094,8 @@ static int gcc_ipq806x_probe(struct plat { struct clk *clk; struct device *dev = &pdev->dev; @@ -644,7 +644,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> /* Temporary until RPM clocks supported */ clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); -@@ -2500,7 +3074,25 @@ static int gcc_ipq806x_probe(struct plat +@@ -2532,7 +3106,25 @@ static int gcc_ipq806x_probe(struct plat if (IS_ERR(clk)) return PTR_ERR(clk); @@ -673,12 +673,12 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> static int gcc_ipq806x_remove(struct platform_device *pdev) --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h -@@ -289,5 +289,7 @@ - #define UBI32_CORE2_CLK_SRC 278 +@@ -290,5 +290,7 @@ #define UBI32_CORE1_CLK 279 #define UBI32_CORE2_CLK 280 -+#define NSSTCM_CLK_SRC 281 -+#define NSSTCM_CLK 282 + #define EBI2_AON_CLK 281 ++#define NSSTCM_CLK_SRC 282 ++#define NSSTCM_CLK 283 #endif --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h |