diff options
| author | John Crispin <john@phrozen.org> | 2016-06-07 20:33:35 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-06-13 22:51:42 +0200 |
| commit | 46cecfd6d727f398b568080655a77ea07308053b (patch) | |
| tree | 09ec2303ba12556ce3276ae80534d5f9469f77c2 /target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch | |
| parent | 53147c2237231842b4d185f69c2bc0d79aff8b85 (diff) | |
| download | upstream-46cecfd6d727f398b568080655a77ea07308053b.tar.gz upstream-46cecfd6d727f398b568080655a77ea07308053b.tar.bz2 upstream-46cecfd6d727f398b568080655a77ea07308053b.zip | |
ipg806x: set v4.4 as default
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch | 80 |
1 files changed, 0 insertions, 80 deletions
diff --git a/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch deleted file mode 100644 index 9f32e8fbc2..0000000000 --- a/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch +++ /dev/null @@ -1,80 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -369,15 +369,21 @@ - - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, -- <&gcc PCIE_PHY_CLK>; -- clock-names = "core", "iface", "phy"; -+ <&gcc PCIE_PHY_CLK>, -+ <&gcc PCIE_AUX_CLK>, -+ <&gcc PCIE_ALT_REF_CLK>; -+ clock-names = "core", "iface", "phy", "aux", "ref"; -+ -+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; -+ assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, -- <&gcc PCIE_PHY_RESET>; -- reset-names = "axi", "ahb", "por", "pci", "phy"; -+ <&gcc PCIE_PHY_RESET>, -+ <&gcc PCIE_EXT_RESET>; -+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; -@@ -415,15 +421,21 @@ - - clocks = <&gcc PCIE_1_A_CLK>, - <&gcc PCIE_1_H_CLK>, -- <&gcc PCIE_1_PHY_CLK>; -- clock-names = "core", "iface", "phy"; -+ <&gcc PCIE_1_PHY_CLK>, -+ <&gcc PCIE_1_AUX_CLK>, -+ <&gcc PCIE_1_ALT_REF_CLK>; -+ clock-names = "core", "iface", "phy", "aux", "ref"; -+ -+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; -+ assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_1_ACLK_RESET>, - <&gcc PCIE_1_HCLK_RESET>, - <&gcc PCIE_1_POR_RESET>, - <&gcc PCIE_1_PCI_RESET>, -- <&gcc PCIE_1_PHY_RESET>; -- reset-names = "axi", "ahb", "por", "pci", "phy"; -+ <&gcc PCIE_1_PHY_RESET>, -+ <&gcc PCIE_1_EXT_RESET>; -+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; -@@ -461,15 +473,21 @@ - - clocks = <&gcc PCIE_2_A_CLK>, - <&gcc PCIE_2_H_CLK>, -- <&gcc PCIE_2_PHY_CLK>; -- clock-names = "core", "iface", "phy"; -+ <&gcc PCIE_2_PHY_CLK>, -+ <&gcc PCIE_2_AUX_CLK>, -+ <&gcc PCIE_2_ALT_REF_CLK>; -+ clock-names = "core", "iface", "phy", "aux", "ref"; -+ -+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; -+ assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_2_ACLK_RESET>, - <&gcc PCIE_2_HCLK_RESET>, - <&gcc PCIE_2_POR_RESET>, - <&gcc PCIE_2_PCI_RESET>, -- <&gcc PCIE_2_PHY_RESET>; -- reset-names = "axi", "ahb", "por", "pci", "phy"; -+ <&gcc PCIE_2_PHY_RESET>, -+ <&gcc PCIE_2_EXT_RESET>; -+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie2_pins>; - pinctrl-names = "default"; |