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| author | Chukun Pan <amadeus@jmu.edu.cn> | 2022-02-10 21:26:40 +0800 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2022-04-16 16:59:31 +0200 |
| commit | 45b3111b992377f0298e52e8787b1a730440b3bd (patch) | |
| tree | 5b469d16ae1212c655f51b1a0d4ff4280c65f6d6 /target/linux/ipq806x/files/arch | |
| parent | eee41e33eca2f860724bceda3f36ea2e30149ef0 (diff) | |
| download | upstream-45b3111b992377f0298e52e8787b1a730440b3bd.tar.gz upstream-45b3111b992377f0298e52e8787b1a730440b3bd.tar.bz2 upstream-45b3111b992377f0298e52e8787b1a730440b3bd.zip | |
ipq806x: RT4230W: utilize nvmem-cells for ath10k caldata
Converts extraction entries from 11-ath10k-caldata into
nvmem-cells in the individual board's device-tree file.
Same as commit 2047058 ("ipq806x: utilize nvmem-cells
for pre-calibration data")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Ansuel Smith <ansuelsmth@gmail.com>
Diffstat (limited to 'target/linux/ipq806x/files/arch')
| -rw-r--r-- | target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 77 |
1 files changed, 66 insertions, 11 deletions
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts index b07e7320a7..96163331f3 100644 --- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts +++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts @@ -151,100 +151,139 @@ reg = <0x0000000 0x0040000>; read-only; }; + partition@40000 { label = "0:MIBIB"; reg = <0x0040000 0x0140000>; read-only; }; + partition@180000 { label = "0:SBL2"; reg = <0x0180000 0x0140000>; read-only; }; + partition@2c0000 { label = "0:SBL3"; reg = <0x02c0000 0x0280000>; read-only; }; + partition@540000 { label = "0:DDRCONFIG"; reg = <0x0540000 0x0120000>; read-only; }; + partition@660000 { label = "0:SSD"; reg = <0x0660000 0x0120000>; read-only; }; + partition@780000 { label = "0:TZ"; reg = <0x0780000 0x0280000>; read-only; }; + partition@a00000 { label = "0:RPM"; reg = <0x0a00000 0x0280000>; read-only; }; + partition@c80000 { label = "0:APPSBL"; reg = <0x0c80000 0x0500000>; read-only; }; + partition@1180000 { label = "0:APPSBLENV"; reg = <0x1180000 0x0080000>; }; - ART: partition@1200000 { + + partition@1200000 { label = "0:ART"; reg = <0x1200000 0x0140000>; read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ART_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_ART_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; + partition@1340000 { label = "0:BOOTCONFIG"; reg = <0x1340000 0x0060000>; read-only; }; + partition@13a0000 { label = "0:SBL2_1"; reg = <0x13a0000 0x0140000>; read-only; }; + partition@14e0000 { label = "0:SBL3_1"; reg = <0x14e0000 0x0280000>; read-only; }; + partition@1760000 { label = "0:DDRCONFIG_1"; reg = <0x1760000 0x0120000>; read-only; }; + partition@1880000 { label = "0:SSD_1"; reg = <0x1880000 0x0120000>; read-only; }; + partition@19a0000 { label = "0:TZ_1"; reg = <0x19a0000 0x0280000>; read-only; }; + partition@1c20000 { label = "0:RPM_1"; reg = <0x1c20000 0x0280000>; read-only; }; + partition@1ea0000 { label = "0:BOOTCONFIG1"; reg = <0x1ea0000 0x0060000>; read-only; }; + partition@1f00000 { label = "0:APPSBL_1"; reg = <0x1f00000 0x0500000>; read-only; }; + partition@2400000 { label = "ubi"; reg = <0x2400000 0x1a000000>; @@ -323,6 +362,21 @@ reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&pcie0_pins>; pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_1000>; + nvmem-cell-names = "pre-calibration"; + }; + }; }; &pcie1 { @@ -331,18 +385,19 @@ pinctrl-0 = <&pcie1_pins>; pinctrl-names = "default"; max-link-speed = <1>; -}; -&ART { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; - macaddr_ART_0: macaddr@0 { - reg = <0x0 0x6>; - }; + wifi1: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; - macaddr_ART_6: macaddr@6 { - reg = <0x6 0x6>; + nvmem-cells = <&precal_ART_5000>; + nvmem-cell-names = "pre-calibration"; + }; }; }; |