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authorJohn Crispin <john@phrozen.org>2018-02-21 20:40:50 +0100
committerMathias Kresin <dev@kresin.me>2018-03-14 19:04:50 +0100
commit54b275c8ed3ad20c447fd46deec83384822ac79d (patch)
tree4198c9f77e467b316940cb78297d3030e67d67ea /target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch
parentb7f115f22a9d79bd45bfe27cfb8d491dac49feb4 (diff)
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ipq40xx: add target
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch')
-rw-r--r--target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch115
1 files changed, 115 insertions, 0 deletions
diff --git a/target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch b/target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch
new file mode 100644
index 0000000000..e9d262069f
--- /dev/null
+++ b/target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch
@@ -0,0 +1,115 @@
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+@@ -19,4 +19,112 @@
+ / {
+ model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
++ memory {
++ device_type = "memory";
++ reg = <0x80000000 0x10000000>;
++ };
++
++ reserved-memory {
++ #address-cells = <0x1>;
++ #size-cells = <0x1>;
++ ranges;
++
++ apps_bl@87000000 {
++ reg = <0x87000000 0x400000>;
++ no-map;
++ };
++
++ sbl@87400000 {
++ reg = <0x87400000 0x100000>;
++ no-map;
++ };
++
++ cnss_debug@87500000 {
++ reg = <0x87500000 0x600000>;
++ no-map;
++ };
++
++ cpu_context_dump@87b00000 {
++ reg = <0x87b00000 0x080000>;
++ no-map;
++ };
++
++ tz_apps@87b80000 {
++ reg = <0x87b80000 0x280000>;
++ no-map;
++ };
++
++ smem@87e00000 {
++ reg = <0x87e00000 0x080000>;
++ no-map;
++ };
++
++ tz@87e80000 {
++ reg = <0x87e80000 0x180000>;
++ no-map;
++ };
++ };
++};
++
++&spi_0 {
++ mx25l25635f@0 {
++ compatible = "mx25l25635f", "jedec,spi-nor";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0>;
++ spi-max-frequency = <24000000>;
++
++ SBL1@0 {
++ label = "SBL1";
++ reg = <0x0 0x40000>;
++ read-only;
++ };
++ MIBIB@40000 {
++ label = "MIBIB";
++ reg = <0x40000 0x20000>;
++ read-only;
++ };
++ QSEE@60000 {
++ label = "QSEE";
++ reg = <0x60000 0x60000>;
++ read-only;
++ };
++ CDT@c0000 {
++ label = "CDT";
++ reg = <0xc0000 0x10000>;
++ read-only;
++ };
++ DDRPARAMS@d0000 {
++ label = "DDRPARAMS";
++ reg = <0xd0000 0x10000>;
++ read-only;
++ };
++ APPSBLENV@e0000 {
++ label = "APPSBLENV";
++ reg = <0xe0000 0x10000>;
++ read-only;
++ };
++ APPSBL@f0000 {
++ label = "APPSBL";
++ reg = <0xf0000 0x80000>;
++ read-only;
++ };
++ ART@170000 {
++ label = "ART";
++ reg = <0x170000 0x10000>;
++ read-only;
++ };
++ kernel@180000 {
++ label = "kernel";
++ reg = <0x180000 0x400000>;
++ };
++ rootfs@580000 {
++ label = "rootfs";
++ reg = <0x580000 0x1600000>;
++ };
++ firmware@180000 {
++ label = "firmware";
++ reg = <0x180000 0x1a00000>;
++ };
++ };
+ };