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authorPavel Kubelun <be.dissent@gmail.com>2019-05-14 16:42:17 +0300
committerChristian Lamparter <chunkeey@gmail.com>2019-06-15 19:55:32 +0200
commit2ee98e8f6e67a2aecfa79e45a6c99d7d40b3d362 (patch)
tree92a279c11f02a99c0471572df304f7f9e8d7829e /target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
parent7193067edb76d80ab3f52a39c4b083b3839b0cda (diff)
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ipq40xx: directly define voltage per opp
This should align opp table with what it was before converting to OPP v2. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Diffstat (limited to 'target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch')
-rw-r--r--target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch20
1 files changed, 10 insertions, 10 deletions
diff --git a/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch b/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
index b761073c12..b1e0e352ad 100644
--- a/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
+++ b/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
@@ -41,7 +41,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
};
cpus {
-@@ -132,6 +134,12 @@
+@@ -136,6 +138,12 @@
};
};
@@ -54,7 +54,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
-@@ -177,13 +185,13 @@
+@@ -181,13 +189,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -70,7 +70,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
-@@ -191,7 +199,7 @@
+@@ -195,7 +203,7 @@
status = "disabled";
};
@@ -79,7 +79,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-@@ -200,10 +208,26 @@
+@@ -204,10 +212,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
@@ -107,7 +107,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-@@ -212,14 +236,29 @@
+@@ -216,14 +240,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
@@ -138,7 +138,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
-@@ -293,7 +332,7 @@
+@@ -297,7 +336,7 @@
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
@@ -147,7 +147,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
-@@ -305,7 +344,7 @@
+@@ -309,7 +348,7 @@
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
@@ -156,7 +156,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
-@@ -327,6 +366,101 @@
+@@ -331,6 +370,101 @@
reg = <0x4ab000 0x4>;
};
@@ -258,7 +258,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
-@@ -360,7 +494,7 @@
+@@ -364,7 +498,7 @@
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
@@ -267,7 +267,7 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org>
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
-@@ -402,7 +536,7 @@
+@@ -406,7 +540,7 @@
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,