ipq40xx: Add support for Teltonika RUTX10

This patch adds support for the Teltonika RUTX10.
This device is an industrial DIN-rail router with 4 ethernet ports,
2.4G/5G dualband WiFi, Bluetooth, a USB 2.0 port and two GPIOs.

The RUTX series devices are very similiar so common parts of the DTS
are kept in a DTSI file. They are based on the QCA AP-DK01.1-C1 dev
board.

See https://teltonika-networks.com/product/rutx10 for more info.

Hardware:
  SoC:                 Qualcomm IPQ4018
  RAM:                 256MB DDR3
  SPI Flash 1:         XTX XT25F128B (16MB, NOR)
  SPI Flash 2:         XTX XT26G02AWS (256MB, NAND)
  Ethernet:            Built-in IPQ4018 (SoC, QCA8075), 4x 10/100/1000 ports
  WiFi 1:              Qualcomm QCA4019 IEEE 802.11b/g/n
  Wifi 2:              Qualcomm QCA4019 IEEE 802.11a/n/ac
  USB Hub:             Genesys Logic GL852GT
  Bluetooth:           Qualcomm CSR8510 (A10U)
  LED/GPIO controller: STM32F030 with custom firmware
  Buttons:             Reset button
  Leds:                Power (green, cannot be controlled)
                       WiFi 2.4G activity (green)
                       WiFi 5G activity (green)

MACs Details verified with the stock firmware:
   eth0:             Partition 0:CONFIG Offset: 0x0
   eth1:             = eth0 + 1
   radio0 (2.4 GHz): = eth0 + 2
   radio1 (5.0 GHz): = eth0 + 3
Label MAC address is from eth0.

The LED/GPIO controller needs a separate kernel driver to function.
The driver was extracted from the Teltonika GPL sources and can be
found at following feed: https://github.com/0xFelix/teltonika-rutx-openwrt

USB detection of the bluetooth interface is sometimes a bit flaky. When
not detected power cycle the device. When the bluetooth interface was
detected properly it can be used with bluez / bluetoothctl.

Flash instructions via stock web interface (sysupgrade based):
  1. Set PC to fixed ip address 192.168.1.100
  2. Push reset button and power on the device
  3. Open u-boot HTTP recovery at http://192.168.1.1
  4. Upload latest stock firmware and wait until the device is rebooted
  5. Open stock web interface at http://192.168.1.1
  6. Set some password so the web interface is happy
  7. Go to firmware upgrade settings
  8. Choose
     openwrt-ipq40xx-generic-teltonika_rutx10-squashfs-nand-factory.ubi
  9. Set 'Keep settings' to off
  10. Click update, when warned that it is not a signed image proceed

Return to stock firmware:
  1. Set PC to fixed ip address 192.168.1.100
  2. Push reset button and power on the device
  3. Open u-boot HTTP recovery at http://192.168.1.1
  4. Upload latest stock firmware and wait until the device is rebooted

Note: The DTS expects OpenWrt to be running from the second rootfs
partition. u-boot on these devices hot-patches the DTS so running from the
first rootfs partition should also be possible. If you want to be save follow
the instructions above. u-boot HTTP recovery restores the device so that when
flashing OpenWrt from stock firmware it is flashed to the second rootfs
partition and the DTS matches.

Signed-off-by: Felix Matouschek <felix@matouschek.org>

2 files changed, 277 insertions, 0 deletions

diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi
new file mode 100644
index 0000000000..3673a13430
--- /dev/null
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	aliases {
+		label-mac-device = &gmac0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	soc {
+		pinctrl@1000000 {
+			mdio_pins: mdio_pinmux {
+				mux_1 {
+					pins = "gpio53";
+					function = "mdio";
+					bias-pull-up;
+				};
+				mux_2 {
+					pins = "gpio52";
+					function = "mdc";
+					bias-pull-up;
+				};
+			};
+
+			i2c_0_pins: i2c_0_pinmux {
+				mux {
+					pins = "gpio58", "gpio59";
+					function = "blsp_i2c0";
+					bias-disable;
+				};
+			};
+		};
+
+		keys {
+			compatible = "gpio-keys";
+
+			reset {
+				label = "reset";
+				gpios = <&tlmm 4 1>;
+				linux,code = <KEY_RESTART>;
+			};
+		};
+
+		gpio_export {
+			compatible = "gpio-export";
+			#size-cells = <0>;
+
+			gpio_out {
+				gpio-export,name = "gpio_out";
+				gpio-export,output = <0>;
+				gpio-export,direction_may_change = <0>;
+				gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>;
+			};
+
+			gpio_in {
+				gpio-export,name = "gpio_in";
+				gpio-export,input = <0>;
+				gpio-export,direction_may_change = <0>;
+				gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>;
+			};
+		};
+	};
+};
+
+&blsp1_i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+
+	stm32_io: stm32@74 {
+		compatible = "tlt,stm32v1";
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		gpio-controller;
+		interrupt-controller;
+		interrupt-parent = <&tlmm>;
+		interrupts = <5 2>;
+		reg = <0x74>;
+	};
+};
+
+&blsp1_spi1 {
+	cs-gpios = <&tlmm 54 0>, <&tlmm 63 0>;
+	num-cs = <2>;
+
+	xt25f128b@0 {
+		/*
+		 * Factory U-boot looks in 0:BOOTCONFIG partition for active
+		 * partitions settings and mangles the partition config so
+		 * 0:QSEE/0:QSEE_1, 0:CDT/0:CDT_1 and  0:APPSBL/0:APPSBL_1 pairs
+		 * can be swaped. It isn't a problem but we never can be sure where
+		 * OFW put factory images. "n25q128a11" is required for proper nor
+		 * recognition in u-boot.
+		 */
+		compatible = "jedec,spi-nor", "n25q128a11";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x0 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "0:MIBIB";
+				reg = <0x40000 0x20000>;
+				read-only;
+			};
+
+			partition@60000 {
+				label = "0:BOOTCONFIG";
+				reg = <0x60000 0x20000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "0:BOOTCONFIG1";
+				reg = <0x80000 0x20000>;
+				read-only;
+			};
+
+			partition@a0000 {
+				label = "0:QSEE";
+				reg = <0xa0000 0x60000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "0:QSEE_1";
+				reg = <0x100000 0x60000>;
+				read-only;
+			};
+
+			partition@160000 {
+				label = "0:CDT";
+				reg = <0x160000 0x10000>;
+				read-only;
+			};
+
+			partition@170000 {
+				label = "0:CDT_1";
+				reg = <0x170000 0x10000>;
+				read-only;
+			};
+
+			partition@180000 {
+				label = "0:DDRPARAMS";
+				reg = <0x180000 0x10000>;
+				read-only;
+			};
+
+			partition@190000 {
+				label = "0:APPSBLENV";
+				reg = <0x190000 0x10000>;
+				read-only;
+			};
+
+			partition@1a0000 {
+				label = "0:APPSBL";
+				reg = <0x1a0000 0xa0000>;
+				read-only;
+			};
+
+			partition@240000 {
+				label = "0:APPSBL_1";
+				reg = <0x240000 0xa0000>;
+				read-only;
+			};
+
+			partition@2e0000 {
+				label = "0:ART";
+				reg = <0x2e0000 0x10000>;
+				read-only;
+			};
+
+			config: partition@2f0000 {
+				label = "0:CONFIG";
+				reg = <0x2f0000 0x10000>;
+				read-only;
+			};
+
+			partition@300000 {
+				label = "0:CONFIG_RW";
+				reg = <0x300000 0x10000>;
+				read-only;
+			};
+
+			partition@310000 {
+				label = "0:EVENTSLOG";
+				reg = <0x310000 0x90000>;
+				read-only;
+			};
+		};
+	};
+
+	xt26g02a@1 {
+		/*
+		 * Factory U-boot looks in 0:BOOTCONFIG partition for active
+		 * partitions settings and mangles the partition config so
+		 * rootfs/rootfs_1 pairs can be swaped.
+		 * It isn't a problem but we never can be sure where OFW put
+		 * factory images. "spinand,mt29f" value is required for proper
+		 * nand recognition in u-boot.
+		 */
+		compatible = "spi-nand", "spinand,mt29f";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <1>;
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "rootfs_1";
+				reg = <0x00000000 0x08000000>;
+			};
+
+			partition@8000000 {
+				label = "rootfs";
+				reg = <0x08000000 0x08000000>;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	phy-reset-gpio = <&tlmm 62 0>;
+};
diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts
new file mode 100644
index 0000000000..d1d632568c
--- /dev/null
+++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4018-rutx.dtsi"
+
+/ {
+	model = "Teltonika RUTX10";
+	compatible = "teltonika,rutx10";
+
+	soc {
+		leds {
+			compatible = "gpio-leds";
+
+			wifi2g {
+				label = "green:wifi2g";
+				gpios = <&stm32_io 19 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "phy0tpt";
+			};
+
+			wifi5g {
+				label = "green:wifi5g";
+				gpios = <&stm32_io 18 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "phy1tpt";
+			};
+		};
+	};
+};