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authorJohn Crispin <john@phrozen.org>2020-01-14 17:15:57 +0100
committerKoen Vandeputte <koen.vandeputte@ncentric.com>2020-02-28 17:50:46 +0100
commit272e0a702a2bcfb383c59051f37c87dcdbe844f5 (patch)
tree1f8b47032764ae85be26374e8de4df2de724df1c /target/linux/ipq40xx/files-5.4
parent25d9df670b850a4e3702e084ff249baa1670ae3f (diff)
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ipq40xx: add v5.4 support
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ipq40xx/files-5.4')
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-a42.dts219
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts348
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts242
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts241
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts277
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts235
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-emd1.dts233
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts265
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts33
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts33
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi312
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts292
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts9
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi269
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts81
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts337
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts309
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts265
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-a62.dts243
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts21
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi181
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts80
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts115
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi266
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts399
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts303
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts267
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts264
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts311
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts79
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi224
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts375
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts270
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts419
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts421
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts280
-rw-r--r--target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-mr33.dts400
-rw-r--r--target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/Makefile9
-rw-r--r--target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.c2177
-rw-r--r--target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.h455
-rw-r--r--target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c1363
-rw-r--r--target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c377
-rw-r--r--target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/ess_edma.h389
43 files changed, 13688 insertions, 0 deletions
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-a42.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-a42.dts
new file mode 100644
index 0000000000..33c44a8097
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-a42.dts
@@ -0,0 +1,219 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "OpenMesh A42";
+ compatible = "openmesh,a42";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ red {
+ label = "a42:red:status";
+ gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ power: green {
+ label = "a42:green:status";
+ gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "a42:blue:status";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ watchdog {
+ compatible = "linux,wdt-gpio";
+ gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+ hw_algo = "toggle";
+ /* hw_margin_ms is actually 300s but driver limits it to 60s */
+ hw_margin_ms = <60000>;
+ always-running;
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ /* partitions are passed via bootloader */
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+ qcom,phy_mdio_addr = <3>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <1 0x10>;
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "OM-A42";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "OM-A42";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
new file mode 100644
index 0000000000..e21c40cae0
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "ALFA Network AP120C-AC";
+ compatible = "alfa-network,ap120c-ac";
+
+ aliases {
+ led-boot = &status;
+ led-failsafe = &status;
+ led-running = &status;
+ led-upgrade = &status;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status: status {
+ label = "ap120c-ac:blue:status";
+ gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+
+ wan {
+ label = "ap120c-ac:amber:wan";
+ gpios = <&qca8075 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan2g {
+ label = "ap120c-ac:green:wlan2g";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ wlan5g {
+ label = "ap120c-ac:red:wlan5g";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1tpt";
+ };
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ counter@4a1000 {
+ compatible = "qcom,qca-gcnt";
+ reg = <0x4a1000 0x4>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+
+ dwc3@8a00000 {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ qca8075: ess-switch@c000000 {
+ status = "okay";
+
+ switch_lan_bmp = <0x10>;
+ switch_wan_bmp = <0x20>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ tpm@29 {
+ compatible = "atmel,at97sc3204t";
+ reg = <0x29>;
+ };
+};
+
+&blsp1_spi1 {
+ status = "okay";
+
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
+ <&tlmm 4 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "APPSBLENV";
+ reg = <0x000e0000 0x00010000>;
+ };
+
+ partition@f0000 {
+ label = "APPSBL";
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+
+ partition@170000 {
+ label = "ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "priv_data1";
+ reg = <0x00180000 0x00010000>;
+ read-only;
+ };
+
+ partition@190000 {
+ label = "priv_data2";
+ reg = <0x00190000 0x00010000>;
+ read-only;
+ };
+ };
+ };
+
+ nand@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "rootfs1";
+ reg = <0x00000000 0x04000000>;
+ };
+
+ partition@4000000 {
+ label = "rootfs2";
+ reg = <0x04000000 0x04000000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ status = "okay";
+
+ pinctrl-0 = <&serial0_pins>;
+ pinctrl-names = "default";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,forced_duplex = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,phy_mdio_addr = <3>;
+ qcom,poll_required = <1>;
+ vlan_tag = <1 0x10>;
+};
+
+&gmac1 {
+ qcom,forced_duplex = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ vlan_tag = <2 0x20>;
+};
+
+&tlmm {
+ i2c0_pins: i2c0_pinmux {
+ mux_i2c {
+ function = "blsp_i2c0";
+ pins = "gpio58", "gpio59";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ mdio_pins: mdio_pinmux {
+ mux_mdio {
+ pins = "gpio53";
+ function = "mdio";
+ bias-pull-up;
+ };
+
+ mux_mdc {
+ pins = "gpio52";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial0_pins: serial0_pinmux {
+ mux_uart {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi0_pins: spi0_pinmux {
+ mux_spi {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ mux_cs {
+ function = "gpio";
+ pins = "gpio54", "gpio4";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts
new file mode 100644
index 0000000000..d8b9e7ef13
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "EZVIZ CS-W3-WD1200G EUP";
+ compatible = "ezviz,cs-w3-wd1200g-eup";
+
+ aliases {
+ led-boot = &led_status_green;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_blue;
+ led-upgrade = &led_status_green;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <5000>;
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_red: status_red {
+ label = "cs-w3-wd1200g-eup:red:status";
+ gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_green: status_green {
+ label = "cs-w3-wd1200g-eup:green:status";
+ gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_blue: status_blue {
+ label = "cs-w3-wd1200g-eup:blue:status";
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio53";
+ function = "mdio";
+ bias-pull-up;
+ };
+
+ mux_2 {
+ pins = "gpio52";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition0@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+
+ partition1@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+
+ partition2@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+
+ partition3@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+
+ partition4@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+
+ partition5@E0000 {
+ label = "APPSBLENV";
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+
+ partition6@F0000 {
+ label = "APPSBL";
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+
+ partition7@170000 {
+ label = "ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+
+ partition9@580000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x00180000 0x00e80000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts
new file mode 100644
index 0000000000..0fd4318527
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "D-Link DAP 2610";
+ compatible = "dlink,dap-2610";
+
+ aliases {
+ led-boot = &led_red;
+ led-failsafe = &led_red;
+ led-running = &led_green;
+ led-upgrade = &led_red;
+ };
+
+ soc {
+ edma@c080000 {
+ qcom,num_gmac = <1>;
+ status = "ok";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ rng@22000 {
+ status = "ok";
+ };
+
+ crypto@8e3a000 {
+ status = "ok";
+ };
+
+ watchdog@b017000 {
+ status = "ok";
+ };
+
+ ess-switch@c000000 {
+ status = "ok";
+ switch_lan_bmp = <0x20>;
+ switch_wan_bmp = <0x00>;
+ };
+
+ ess-psgmii@98000 {
+ status = "ok";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_red: red {
+ label = "dap-2610:red:power";
+ gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ };
+
+ led_green: green {
+ label = "dap-2610:green:power";
+ gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fixed-partitions";
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ partition@f0000 {
+ label = "APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ partition@170000 {
+ label = "ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ partition@180000 {
+ compatible = "wrg";
+ label = "firmware";
+ reg = <0x180000 0xdc0000>;
+ };
+ partition@fb0000 {
+ label = "rgbd";
+ reg = <0xfb0000 0x10000>;
+ read-only;
+ };
+ partition@fc0000 {
+ label = "bdcfg";
+ reg = <0xfc0000 0x10000>;
+ read-only;
+ };
+ partition@fd0000 {
+ label = "langpack";
+ reg = <0xfd0000 0x20000>;
+ read-only;
+ };
+ partition@ff0000 {
+ label = "certificate";
+ reg = <0xff0000 0x10000>;
+ read-only;
+ };
+ partition@f40000 {
+ label = "captival";
+ reg = <0xf40000 0x70000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp_dma {
+ status = "ok";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+};
+
+&cryptobam {
+ status = "ok";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <1 0x20>;
+};
+
+&mdio {
+ status = "ok";
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ mux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ mux_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&wifi0 {
+ status = "ok";
+ qcom,ath10k-calibration-variant = "dlink,dap-2610";
+};
+
+&wifi1 {
+ status = "ok";
+ qcom,ath10k-calibration-variant = "dlink,dap-2610";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts
new file mode 100644
index 0000000000..2f9a890485
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Linksys EA6350v3";
+ compatible = "linksys,ea6350v3";
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power: status {
+ label = "EA6350v3:green:status";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "linksys-ea6350v3";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "linksys-ea6350v3";
+};
+
+
+&blsp_dma {
+ status = "okay";
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ mux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ mux_cs {
+ function = "gpio";
+ pins = "gpio54", "gpio59";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
+ <&tlmm 59 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ SBL1@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ MBIB@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ QSEE@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ CDT@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ APPSBLENV@d0000 {
+ label = "APPSBLENV";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ APPSBL@e0000 {
+ label = "APPSBL"; /* uboot */
+ reg = <0x000e0000 0x00080000>;
+ read-only;
+ };
+ ART@160000 {
+ label = "ART";
+ reg = <0x00160000 0x00010000>;
+ read-only;
+ };
+ u_env@170000 {
+ label = "u_env";
+ reg = <0x00170000 0x00020000>;
+ };
+ s_env@190000 {
+ label = "s_env";
+ reg = <0x00190000 0x00020000>;
+ };
+ devinfo@1b0000 {
+ label = "devinfo";
+ reg = <0x001b0000 0x00010000>;
+ };
+ /* 0x001c0000 - 0x00200000 unused */
+ };
+ };
+
+ flash@1 {
+ status = "okay";
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ kernel@0 {
+ label = "kernel";
+ reg = <0x00000000 0x02800000>;
+ };
+ rootfs@300000 {
+ label = "rootfs";
+ reg = <0x00300000 0x02500000>;
+ };
+ alt_kernel@2800000 {
+ label = "alt_kernel";
+ reg = <0x02800000 0x02800000>;
+ };
+ alt_rootfs@2b00000 {
+ label = "alt_rootfs";
+ reg = <0x02b00000 0x02500000>;
+ };
+ sysdiag@5000000 {
+ label = "sysdiag";
+ reg = <0x05000000 0x00100000>;
+ };
+ syscfg@5100000 {
+ label = "syscfg";
+ reg = <0x05100000 0x02F00000>;
+ };
+ /* 0x00000000 - 0x08000000: 128 MiB */
+ };
+ };
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts
new file mode 100644
index 0000000000..32fded4c0e
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "EnGenius EAP1300";
+ compatible = "engenius,eap1300";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power: orange {
+ label = "eap1300:orange:power";
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+
+ lan {
+ label = "eap1300:blue:lan";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ mesh {
+ label = "eap1300:blue:mesh";
+ gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan2g {
+ label = "eap1300:blue:wlan2g";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan5g {
+ label = "eap1300:yellow:wlan5g";
+ gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio54", "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition1@40000 {
+ label = "0:MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ partition2@60000 {
+ label = "0:QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ partition3@c0000 {
+ label = "0:CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ partition4@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ partition5@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+ partition6@f0000 {
+ label = "0:APPSBL";
+ reg = <0x000f0000 0x00090000>;
+ read-only;
+ };
+ partition7@180000 {
+ label = "0:ART";
+ reg = <0x00180000 0x00010000>;
+ read-only;
+ };
+ partition8@190000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x190000 0x1dc0000>;
+ };
+ partition9@1f50000 {
+ label = "u-boot-env";
+ reg = <0x01f50000 0x00010000>;
+ };
+ partition10@1f60000 {
+ label = "userconfig";
+ reg = <0x01f60000 0x000a0000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+ vlan_tag = <1 0x10>;
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-emd1.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-emd1.dts
new file mode 100644
index 0000000000..cf4f793f21
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-emd1.dts
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "EnGenius EMD1";
+ compatible = "engenius,emd1";
+
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ switch_lan_bmp = <0x20>;
+ switch_wan_bmp = <0x00>;
+ };
+
+ edma@c080000 {
+ status = "okay";
+ qcom,num_gmac = <1>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: power {
+ label = "emd1:white:power";
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+
+ wlan2g {
+ label = "emd1:red:wlan2g";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ wlan5g {
+ label = "emd1:blue:wlan5g";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1tpt";
+ };
+
+ mesh {
+ label = "emd1:orange:mesh";
+ gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio54", "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition0@0 {
+ label = "0:SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition1@40000 {
+ label = "0:MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ partition2@60000 {
+ label = "0:QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ partition3@c0000 {
+ label = "0:CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ partition4@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ partition5@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+ partition6@f0000 {
+ label = "0:APPSBL";
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+ partition7@170000 {
+ label = "0:ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+ partition8@180000 {
+ label = "userconfig";
+ reg = <0x00180000 0x00080000>;
+ read-only;
+ };
+ partition9@200000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x200000 0x01e00000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <1 0x20>;
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "EnGenius-EMD1";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "EnGenius-EMD1";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts
new file mode 100644
index 0000000000..8636b18b2e
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "EnGenius ENS620EXT";
+ compatible = "engenius,ens620ext";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ /*
+ * Disable the broken restart as a workaround for the buggy
+ * 3.0.0/3.0.1 U-boots that ship with the device.
+ * Note: The watchdog is now used to restart this device.
+ */
+ restart@4ab000 {
+ status = "disabled";
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power: power {
+ label = "ens620ext:amber:power";
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+
+ lan1 {
+ label = "ens620ext:green:lan1";
+ gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
+ };
+
+ lan2 {
+ label = "ens620ext:green:lan2";
+ gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ };
+
+ wlan2G {
+ label = "ens620ext:green:wlan2G";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan5G {
+ label = "ens620ext:green:wlan5G";
+ gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ mux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ mux_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "APPSBLENV"; /* uboot env*/
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+ partition@f0000 {
+ label = "APPSBL"; /* uboot */
+ reg = <0x000f0000 0x00090000>;
+ read-only;
+ };
+ partition@180000 {
+ label = "ART";
+ reg = <0x00180000 0x00010000>;
+ read-only;
+ };
+ partition@190000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x00190000 0x14d0000>;
+ };
+ partition@1660000 {
+ label = "failsafe";
+ reg = <0x01660000 0x008F0000>;
+ read-only;
+ };
+ partition@1f50000 {
+ label = "u-boot-env";
+ reg = <0x01f50000 0x00010000>;
+ read-only;
+ };
+ partition@1f60000 {
+ label = "userconfig";
+ reg = <0x01f60000 0x000a0000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts
new file mode 100644
index 0000000000..2b93dcbb99
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts
@@ -0,0 +1,33 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4018-ex61x0v2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Netgear EX6100v2";
+ compatible = "netgear,ex6100v2";
+};
+
+&wifi0 {
+ qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
+};
+
+&wifi1 {
+ qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts
new file mode 100644
index 0000000000..f1c44c1ae8
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts
@@ -0,0 +1,33 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4018-ex61x0v2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Netgear EX6150v2";
+ compatible = "netgear,ex6150v2";
+};
+
+&wifi0 {
+ qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
+};
+
+&wifi1 {
+ qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi
new file mode 100644
index 0000000000..cc70080c92
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi
@@ -0,0 +1,312 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Netgear EX61X0v2";
+ compatible = "netgear,ex61x0v2";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ qcom,num_gmac = <1>;
+ };
+ };
+
+ aliases {
+ led-boot = &power_amber;
+ led-failsafe = &power_amber;
+ led-running = &power_green;
+ led-upgrade = &power_amber;
+ label-mac-device = &gmac0;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ led_spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+ num-chipselects = <0>;
+
+ led_gpio: led_gpio@0 {
+ compatible = "fairchild,74hc595";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ registers-number = <1>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power_amber: power_amber {
+ label = "ex61x0v2:amber:power";
+ gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ power_green: power_green {
+ label = "ex61x0v2:green:power";
+ gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
+ };
+
+ right {
+ label = "ex61x0v2:blue:right";
+ gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
+ };
+
+ left {
+ label = "ex61x0v2:blue:left";
+ gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
+ };
+
+ client_green {
+ label = "ex61x0v2:green:client";
+ gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
+ };
+
+ client_red {
+ label = "ex61x0v2:red:client";
+ gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
+ };
+
+ router_green {
+ label = "ex61x0v2:green:router";
+ gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ router_red {
+ label = "ex61x0v2:red:router";
+ gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "ex61x0v2:green:wps";
+ gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ mx25l12805d@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition0@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+
+ partition1@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+
+ partition2@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+
+ partition3@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+
+ partition4@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+
+ partition5@E0000 {
+ label = "APPSBLENV";
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+
+ partition6@F0000 {
+ label = "APPSBL";
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+
+ partition7@170000 {
+ label = "ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+
+ partition8@180000 {
+ label = "config";
+ reg = <0x00180000 0x00010000>;
+ read-only;
+ };
+
+ partition9@190000 {
+ label = "pot";
+ reg = <0x00190000 0x00010000>;
+ read-only;
+ };
+
+ partition10@1a0000 {
+ label = "dnidata";
+ reg = <0x001a0000 0x00010000>;
+ read-only;
+ };
+
+ partition11@1b0000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x001b0000 0x00e10000>;
+ };
+
+ partition12@fc0000 {
+ label = "language";
+ reg = <0x00fc0000 0x00040000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts
new file mode 100644
index 0000000000..b2a32946d9
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "AVM FRITZ!Box 4040";
+ compatible = "avm,fritzbox-4040";
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &flash;
+ led-running = &power;
+ led-upgrade = &flash;
+ label-mac-device = &gmac0;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ qca8075: ess-switch@c000000 {
+ status = "okay";
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ enable-usb-power {
+ gpio-hog;
+ line-name = "enable USB3 power";
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wlan {
+ label = "wlan";
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RFKILL>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ switch-leds {
+ compatible = "gpio-leds";
+
+ wlan {
+ label = "fritz4040:green:wlan";
+ gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ panic: info_red {
+ label = "fritz4040:red:info";
+ gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>;
+ panic-indicator;
+ };
+
+ wan {
+ label = "fritz4040:green:wan";
+ gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ power: power {
+ label = "fritz4040:green:power";
+ gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ lan {
+ label = "fritz4040:green:lan";
+ gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ flash: info_amber {
+ label = "fritz4040:amber:info";
+ gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ mux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ mux_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ status = "okay";
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition0@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition1@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ partition2@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ partition3@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ partition4@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ partition5@e0000 {
+ label = "APPSBLENV"; /* uboot env - empty */
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+ partition6@f0000 {
+ label = "urlader"; /* APPSBL */
+ reg = <0x000f0000 0x0002dc000>;
+ read-only;
+ };
+ partition7@11dc00 {
+ /* make a backup of this partition! */
+ label = "urlader_config";
+ reg = <0x0011dc00 0x00002400>;
+ read-only;
+ };
+ partition8@120000 {
+ label = "tffs1";
+ reg = <0x00120000 0x00080000>;
+ read-only;
+ };
+ partition9@1a0000 {
+ label = "tffs2";
+ reg = <0x001a0000 0x00080000>;
+ read-only;
+ };
+ partition10@220000 {
+ label = "uboot";
+ reg = <0x00220000 0x00080000>;
+ read-only;
+ };
+ partition11@2A0000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x002a0000 0x01c60000>;
+ };
+ partition12@1f00000 {
+ label = "jffs2";
+ reg = <0x01f00000 0x00100000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts
new file mode 100644
index 0000000000..988b86b68d
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
+
+#include "qcom-ipq4018-jalapeno.dtsi"
+
+/ {
+ model = "8devices Jalapeno";
+ compatible = "8dev,jalapeno";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi
new file mode 100644
index 0000000000..3af6de1f60
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ counter@4a1000 {
+ compatible = "qcom,qca-gcnt";
+ reg = <0x4a1000 0x4>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ status = "okay";
+
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+
+ switch_lan_bmp = <0x10>; /* lan port bitmap */
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio_pinmux {
+ pinmux_1 {
+ pins = "gpio53";
+ function = "mdio";
+ };
+
+ pinmux_2 {
+ pins = "gpio52";
+ function = "mdc";
+ };
+
+ pinconf {
+ pins = "gpio52", "gpio53";
+ bias-pull-up;
+ };
+ };
+
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54", "gpio59";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ status = "okay";
+
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ status = "okay";
+
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "APPSBLENV"; /* uboot env*/
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+
+ partition@f0000 {
+ label = "APPSBL"; /* uboot */
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+
+ partition@170000 {
+ label = "ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+ };
+ };
+
+ spi-nand@1 {
+ status = "okay";
+
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ubi";
+ reg = <0x00000000 0x08000000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ status = "okay";
+
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,poll_required = <1>;
+ qcom,poll_required_dynamic = <1>;
+ qcom,phy_mdio_addr = <3>;
+ vlan_tag = <1 0x10>;
+};
+
+&gmac1 {
+ qcom,poll_required = <1>;
+ qcom,poll_required_dynamic = <1>;
+ qcom,phy_mdio_addr = <4>;
+ vlan_tag = <2 0x20>;
+};
+
+&wifi0 {
+ status = "okay";
+
+ qcom,ath10k-calibration-variant = "8devices-Jalapeno";
+};
+
+&wifi1 {
+ status = "okay";
+
+ qcom,ath10k-calibration-variant = "8devices-Jalapeno";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts
new file mode 100644
index 0000000000..2e21b55325
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2019, CRISIS INNOVATION LAB d.o.o.
+ * Author: Robert Marko <robert@meshpoint.me>
+ */
+
+#include "qcom-ipq4018-jalapeno.dtsi"
+
+/ {
+ model = "Crisis Innovation Lab MeshPoint.One";
+ compatible = "cilab,meshpoint-one";
+
+ aliases {
+ led-boot = &led_status;
+ led-failsafe = &led_status;
+ led-running = &led_status;
+ led-upgrade = &led_status;
+ };
+
+ soc {
+ i2c-gpio {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "i2c-gpio";
+ gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */
+ &tlmm 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */
+ >;
+
+ bme280@76 {
+ status = "okay";
+
+ compatible = "bosch,bme280";
+ reg = <0x76>;
+ };
+
+ pcf2129@51 {
+ status = "okay";
+
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+
+ ina230@40 {
+ status = "okay";
+
+ compatible = "ti,ina230";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+
+ ina230@44 {
+ status = "okay";
+
+ compatible = "ti,ina230";
+ reg = <0x44>;
+ shunt-resistor = <2000>;
+ };
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART >;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status: status {
+ label = "meshpoint-one:blue:status";
+ gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts
new file mode 100644
index 0000000000..a8c144f928
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "ZyXEL NBG6617";
+ compatible = "zyxel,nbg6617";
+
+ chosen {
+ /*
+ * the vendor u-boot adds root and mtdparts cmdline parameters
+ * which we don't want... but we have to overwrite them or else
+ * the kernel will take them at face value.
+ */
+ bootargs-append = " mtdparts= root=31:13";
+ };
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+
+ dwc3@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+
+ dwc3@8a00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wlan {
+ label = "wlan";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_RFKILL>;
+ linux,input-type = <EV_SW>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&led_pins>;
+ pinctrl-names = "default";
+
+ power: power {
+ label = "nbg6617:green:power";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb {
+ label = "nbg6617:green:usb";
+ gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ wlan2G {
+ label = "nbg6617:green:wlan2G";
+ gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan5G {
+ label = "nbg6617:green:wlan5G";
+ gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ wps {
+ label = "nbg6617:green:wps";
+ gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+ spi_0_pins: spi_0_pinmux {
+ mux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ mux_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+ led_pins: led_pinmux {
+ mux {
+ pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
+ drive-strength = <0x8>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ mx25l25635f@0 {
+ compatible = "mx25l25635f", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ status = "okay";
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition0@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition1@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ partition2@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ partition3@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ partition4@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ partition5@e0000 {
+ label = "APPSBL"; /* u-boot */
+ reg = <0x000e0000 0x00080000>;
+ /* U-Boot Standalone App "zloader" is located at 0x64000 */
+ read-only;
+ };
+ partition6@160000 {
+ label = "APPSBLENV"; /* u-boot env */
+ reg = <0x00160000 0x00010000>;
+ };
+ partition7@170000 {
+ /* make a backup of this partition! */
+ label = "ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+ partition8@180000 {
+ label = "kernel";
+ reg = <0x00180000 0x00400000>;
+ };
+ partition9@580000 {
+ label = "dualflag";
+ reg = <0x00580000 0x00010000>;
+ read-only;
+ };
+ partition10@590000 {
+ label = "header";
+ reg = <0x00590000 0x00010000>;
+ };
+ partition11@5a0000 {
+ label = "romd";
+ reg = <0x005a0000 0x00100000>;
+ read-only;
+ };
+ partition12@6a0000 {
+ label = "not_root_data";
+ /*
+ * for some strange reason, someone at ZyXEL
+ * had the "great" idea to put the rootfs_data
+ * in front of rootfs... Don't do that!
+ * As a result this one, full MebiByte remains
+ * unused.
+ */
+ reg = <0x006a0000 0x00100000>;
+ };
+ partition13@7a0000 {
+ label = "rootfs";
+ reg = <0x007a0000 0x01860000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts
new file mode 100644
index 0000000000..a0030f77ce
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "ASUS RT-AC58U";
+ compatible = "asus,rt-ac58u";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x8000000>;
+ };
+
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ chosen {
+ bootargs-append = " ubi.mtd=UBI_DEV";
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+
+ dwc3@8a00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: status {
+ label = "rt-ac58u:blue:status";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ wan {
+ label = "rt-ac58u:blue:wan";
+ gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan2G {
+ label = "rt-ac58u:blue:wlan2G";
+ gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ wlan5G {
+ label = "rt-ac58u:blue:wlan5G";
+ gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1tpt";
+ };
+
+ usb {
+ label = "rt-ac58u:blue:usb";
+ gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&usb3_port1>, <&usb3_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ lan {
+ label = "rt-ac58u:blue:lan";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ mux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ mux_cs {
+ function = "gpio";
+ pins = "gpio54", "gpio59";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
+ <&tlmm 59 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ /*
+ * U-boot looks for "n25q128a11" node,
+ * if we don't have it, it will spit out the following warning:
+ * "ipq: fdt fixup unable to find compatible node".
+ */
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
+ spi-max-frequency = <30000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "APPSBLENV"; /* uboot env*/
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+ partition@f0000 {
+ label = "APPSBL"; /* uboot */
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+ partition@170000 {
+ label = "ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+ /* 0x00180000 - 0x00200000 unused */
+ };
+ };
+
+ spi-nand@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <30000000>;
+
+ /*
+ * U-boot looks for "spinand,mt29f" node,
+ * if we don't have it, it will spit out the following warning:
+ * "ipq: fdt fixup unable to find compatible node".
+ */
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ /*
+ * TODO: change to label = "ubi" once we drop 4.14.
+ * also drop the bootargs-append and all the
+ * userspace CI_UBIPART="UBI_DEV" remains.
+ */
+ label = "UBI_DEV";
+ reg = <0x00000000 0x08000000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "RT-AC58U";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "RT-AC58U";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts
new file mode 100644
index 0000000000..5932638da0
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts
@@ -0,0 +1,265 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "ZyXEL WRE6606";
+ compatible = "zyxel,wre6606";
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ chosen {
+ bootargs-append = " mtdparts=";
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ qcom,num_gmac = <1>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ wps {
+ label = "wre6606:green:wps";
+ gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan5g_green {
+ label = "wre6606:green:wlan5g";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ power: power {
+ label = "wre6606:green:power";
+ gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan5g_red {
+ label = "wre6606:red:wlan5g";
+ gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan2g_red {
+ label = "wre6606:red:wlan2g";
+ gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan2g_green {
+ label = "wre6606:green:wlan2g";
+ gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ mx25l12805d@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition0@0 {
+ label = "SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+
+ partition1@40000 {
+ label = "MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+
+ partition2@60000 {
+ label = "QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+
+ partition3@c0000 {
+ label = "CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+
+ partition4@d0000 {
+ label = "DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+
+ partition5@E0000 {
+ label = "APPSBLENV";
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+
+ partition6@F0000 {
+ label = "APPSBL";
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+
+ partition7@170000 {
+ label = "ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+
+ partition8@180000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x00180000 0x00ce0000>;
+ };
+
+ partition9@e60000 {
+ label = "manufacture";
+ reg = <0x00e60000 0x00050000>;
+ read-only;
+ };
+
+ partition10@eb0000 {
+ label = "storage";
+ reg = <0x00eb0000 0x00150000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-a62.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-a62.dts
new file mode 100644
index 0000000000..25bbd6b332
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-a62.dts
@@ -0,0 +1,243 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "OpenMesh A62";
+ compatible = "openmesh,a62";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ switch_lan_bmp = <0x10>;
+ switch_wan_bmp = <0x20>;
+
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART >;
+ };
+ };
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ red {
+ label = "a62:red:status";
+ gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ power: green {
+ label = "a62:green:status";
+ gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "a62:blue:status";
+ gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+ };
+
+ watchdog {
+ compatible = "linux,wdt-gpio";
+ gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+ hw_algo = "toggle";
+ /* hw_margin_ms is actually 300s but driver limits it to 60s */
+ hw_margin_ms = <60000>;
+ always-running;
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ enable-usb-power {
+ gpio-hog;
+ gpios = <58 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "enable USB2 power";
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ /* partitions are passed via bootloader */
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <3>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <1 0x10>;
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+ perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi2: wifi@1,0 {
+ compatible = "qcom,ath10k";
+ status = "okay";
+ reg = <0x00010000 0 0 0 0>;
+ qcom,ath10k-calibration-variant = "OM-A62";
+ ieee80211-freq-limit = <5170000 5350000>;
+ };
+ };
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "OM-A62";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "OM-A62";
+ ieee80211-freq-limit = <5470000 5875000>;
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 0000000000..47202d28fe
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,21 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 0000000000..9801354625
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,181 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+ compatible = "qcom,ipq4019";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ pinctrl@1000000 {
+ serial_0_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ };
+ pinconf {
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ pinmux {
+ function = "blsp_i2c0";
+ pins = "gpio10", "gpio11";
+ };
+ pinconf {
+ pins = "gpio10", "gpio11";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58",
+ "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+ };
+
+ blsp_dma: dma@7884000 {
+ status = "okay";
+ };
+
+ spi0: spi@78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+
+ mx25l25635e@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "mx25l25635e";
+ spi-max-frequency = <24000000>;
+ };
+ };
+
+ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ cryptobam: dma@8e04000 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ qpic_bam: dma@7984000 {
+ status = "okay";
+ };
+
+ nand: qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts
new file mode 100644
index 0000000000..df1df2529a
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+ *
+ * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
+ *
+ */
+
+#include "qcom-ipq4019-e2600ac.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Qxwlan E2600AC c1";
+ compatible = "qxwlan,e2600ac-c1";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ partition@f0000 {
+ label = "0:APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ partition@170000 {
+ label = "0:ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ partition@180000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x180000 0x1e80000>;
+ };
+ };
+ };
+};
+
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts
new file mode 100644
index 0000000000..9348ef4eec
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+ *
+ * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
+ *
+ */
+
+#include "qcom-ipq4019-e2600ac.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Qxwlan E2600AC c2";
+ compatible = "qxwlan,e2600ac-c2";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ partition@f0000 {
+ label = "0:APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ partition@170000 {
+ label = "0:ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ubi";
+ reg = <0x00000000 0x04000000>;
+ };
+ };
+ };
+};
+
+&tlmm {
+ nand_pins: nand-pins {
+
+ pullups {
+ pins = "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+};
+
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi
new file mode 100644
index 0000000000..f4af2ba25f
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+ *
+ * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+
+ model = "Qxwlan E2600AC";
+ compatible = "qcom,ipq4019";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+
+ dwc3@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+
+ dwc3@8a00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "e2600ac:green:wlan0";
+ gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+ };
+
+ led2 {
+ label = "e2600ac:green:wlan1";
+ gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
+ };
+
+ led3 {
+ label = "e2600ac:green:usb";
+ gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ led4 {
+ label = "e2600ac:green:ctrl1";
+ gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
+ };
+
+ led5 {
+ label = "e2600ac:green:ctrl2";
+ gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ };
+
+ led6 {
+ label = "e2600ac:green:ctrl3";
+ gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&tlmm {
+ i2c_0_pins: i2c-0-pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+ };
+
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial_0_pins: serial0-pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts
new file mode 100644
index 0000000000..cfc3037fb2
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/*
+ * Device Tree Source for Linksys EA8300 (Dallas)
+ *
+ * Copyright (C) 2019 Jeff Kletsky
+ *
+ */
+
+/dts-v1/;
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Linksys EA8300 (Dallas)";
+ compatible = "linksys,ea8300", "qcom,ipq4019";
+
+
+ aliases {
+ led-boot = &led_wps_amber;
+ led-failsafe = &led_wps;
+ led-running = &led_linksys;
+ led-upgrade = &led_world;
+ serial0 = &blsp1_uart1;
+ };
+
+
+ leds {
+ compatible = "gpio-leds";
+
+ // Retain node names from running OEM on EA8300
+
+ // Front panel LEDs, top to bottom
+
+ led_plug: diag {
+ label = "ea8300:amber:plug";
+ gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_world: internet {
+ label = "ea8300:amber:world";
+ gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_wps: wps {
+ label = "ea8300:white:wps";
+ gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_wps_amber: wps_amber {
+ label = "ea8300:amber:wps";
+ gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ panic-indicator;
+ };
+
+ led_linksys: pwr {
+ label = "ea8300:white:linksys";
+ gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+ };
+
+ // On back panel, above USB socket
+
+ led_usb: usb {
+ label = "ea8300:green:usb";
+ gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&usb3_port1>, <&usb3_port2>,
+ <&usb2_port1>;
+ linux,default-trigger = "usbport";
+ };
+ };
+
+
+ keys {
+ compatible = "gpio-keys";
+
+ button@0 {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+ };
+
+ button@1 {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+
+ //
+ // OEM U-Boot provides either
+ // init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
+ // root=ubi0:ubifs rootwait rw
+ // or the same with ubi.mtd=13,2048
+ //
+
+ chosen {
+ bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
+ };
+
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+
+ dwc3@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+
+ dwc3@8a00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+};
+
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ status = "okay";
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "sbl1";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "qsee";
+ reg = <0x200000 0x100000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "cdt";
+ reg = <0x300000 0x80000>;
+ read-only;
+ };
+
+ partition@380000 {
+ label = "appsblenv";
+ reg = <0x380000 0x80000>;
+ read-only;
+ };
+
+ partition@400000 {
+ label = "ART";
+ reg = <0x400000 0x80000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "appsbl";
+ reg = <0x480000 0x200000>;
+ read-only;
+ };
+
+ partition@680000 {
+ label = "u_env";
+ reg = <0x680000 0x80000>;
+ // writable -- U-Boot environment
+ };
+
+ partition@700000 {
+ label = "s_env";
+ reg = <0x700000 0x40000>;
+ // writable -- Boot counter records
+ };
+
+ partition@740000 {
+ label = "devinfo";
+ reg = <0x740000 0x40000>;
+ read-only;
+ };
+
+ partition@780000 {
+ label = "kernel";
+ reg = <0x780000 0x5800000>;
+ };
+
+ partition@a80000 {
+ label = "rootfs";
+ reg = <0xa80000 0x5500000>;
+ };
+
+ partition@5f80000 {
+ label = "alt_kernel";
+ reg = <0x5f80000 0x5800000>;
+ };
+
+ partition@6280000 {
+ label = "alt_rootfs";
+ reg = <0x6280000 0x5500000>;
+ };
+
+ partition@b780000 {
+ label = "sysdiag";
+ reg = <0xb780000 0x100000>;
+ read-only;
+ };
+
+ partition@b880000 {
+ label = "syscfg";
+ reg = <0xb880000 0x4680000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi2: wifi@1,0 {
+ compatible = "qcom,ath10k";
+ reg = <0x00010000 0 0 0 0>;
+ };
+ };
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&tlmm {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ // gpio61 controls led_usb
+
+ pulldowns {
+ pins = "gpio55", "gpio56", "gpio57",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
+};
+
+&wifi1 {
+ status = "okay";
+ ieee80211-freq-limit = <5170000 5330000>;
+ qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
+};
+
+&wifi2 {
+ status = "okay";
+ ieee80211-freq-limit = <5490000 5835000>;
+ qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts
new file mode 100644
index 0000000000..b04a61dc04
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "AVM FRITZ!Box 7530";
+ compatible = "avm,fritzbox-7530";
+
+ aliases {
+ led-boot = &power_green;
+ led-failsafe = &info_red;
+ led-running = &power_green;
+ led-upgrade = &info_green;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ qcom,num_gmac = <1>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wlan {
+ label = "wlan";
+ gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RFKILL>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ dect {
+ label = "dect";
+ gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PHONE>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ info_red: info_red {
+ label = "fritzbox-7530:red:info";
+ gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ };
+
+ info_green: info {
+ label = "fritzbox-7530:green:info";
+ gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+ };
+
+ wlan {
+ label = "fritzbox-7530:green:wlan";
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ };
+
+ fon {
+ label = "fritzbox-7530:green:fon";
+ gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ };
+
+ power_green: power {
+ label = "fritzbox-7530:green:power";
+ gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "fritzbox-7530:green:wps";
+ gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&tlmm {
+ serial_0_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+
+ usb-power {
+ line-name = "enable USB3 power";
+ gpios = <49 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ output-high;
+ };
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x000000 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "MIBIB";
+ reg = <0x080000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "QSEE";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "CDT";
+ reg = <0x180000 0x40000>;
+ read-only;
+ };
+
+ partition@1c0000 {
+ label = "QSEE_B";
+ reg = <0x1c0000 0x80000>;
+ read-only;
+ };
+
+ partition@240000 {
+ label = "urlader0";
+ reg = <0x240000 0x40000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "urlader1";
+ reg = <0x280000 0x40000>;
+ read-only;
+ };
+
+ partition@2c0000 {
+ label = "nand-tffs";
+ reg = <0x2c0000 0x840000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ /* 'kernel1' in AVM firmware */
+ label = "uboot0";
+ reg = <0xb00000 0x400000>;
+ };
+
+ partition@f00000 {
+ /* 'kernel2' in AVM firmware */
+ label = "uboot1";
+ reg = <0xf00000 0x400000>;
+ };
+
+ partition@1300000 {
+ label = "ubi";
+ reg = <0x1300000 0x6d00000>;
+ };
+ };
+ };
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ dsl@1,0 {
+ compatible = "intel,vrx518";
+ status = "okay";
+ reg = <0x00010000 0 0 0 0>;
+ };
+ };
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts
new file mode 100644
index 0000000000..e9b96b996a
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "AVM FRITZ!Repeater 1200";
+ compatible = "avm,fritzrepeater-1200";
+
+ aliases {
+ led-boot = &power_green;
+ led-failsafe = &power_red;
+ led-running = &power_green;
+ led-upgrade = &power_red;
+ label-mac-device = &wifi0;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
+ switch_lan_bmp = <0x0>; /* lan port bitmap */
+ switch_wan_bmp = <0x10>; /* wan port bitmap */
+ };
+
+ edma@c080000 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ qcom,num_gmac = <1>;
+ qcom,single-phy;
+ };
+ };
+
+ key {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "WPS button";
+ gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power_red: power_red {
+ label = "fritzwlan-1200:red:power";
+ gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+ };
+
+ power_green: power_green {
+ label = "fritzwlan-1200:green:power";
+ gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_yellow {
+ label = "fritzwlan-1200:yellow:power";
+ gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&tlmm {
+ serial_0_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ phy-reset {
+ line-name = "PHY-reset";
+ gpios = <19 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ output-high;
+ };
+
+ phy-reset-2 {
+ line-name = "PHY-reset-2";
+ gpios = <47 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ output-high;
+ };
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "MIBIB";
+ reg = <0x80000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "QSEE";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "CDT";
+ reg = <0x180000 0x40000>;
+ read-only;
+ };
+
+ partition@1c0000 {
+ label = "QSEE_B";
+ reg = <0x1c0000 0x80000>;
+ read-only;
+ };
+
+ partition@240000 {
+ label = "urlader0";
+ reg = <0x240000 0x40000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "urlader1";
+ reg = <0x280000 0x40000>;
+ read-only;
+ };
+
+ partition@2c0000 {
+ label = "nand-tffs";
+ reg = <0x2c0000 0x840000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ /* 'kernel1' in AVM firmware */
+ label = "uboot0";
+ reg = <0xb00000 0x400000>;
+ };
+
+ partition@f00000 {
+ /* 'kernel2' in AVM firmware */
+ label = "uboot1";
+ reg = <0xf00000 0x400000>;
+ };
+
+ partition@1300000 {
+ label = "ubi";
+ reg = <0x1300000 0x6d00000>;
+ };
+ };
+ };
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <0>;
+ qcom,poll_required = <1>;
+ vlan_tag = <0 0x20>;
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts
new file mode 100644
index 0000000000..6914917eb3
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "AVM FRITZ!Repeater 3000";
+ compatible = "avm,fritzrepeater-3000";
+
+ aliases {
+ led-boot = &power_led;
+ led-failsafe = &power_led;
+ led-running = &power_led;
+ led-upgrade = &power_led;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+
+ switch_lan_bmp = <0x10>;
+ switch_wan_bmp = <0x20>;
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ key {
+ compatible = "gpio-keys";
+
+ connect {
+ label = "Connect";
+ gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ connect_red {
+ label = "fritzwlan-3000:red:connect";
+ gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ };
+
+ connect_green {
+ label = "fritzwlan-3000:green:connect";
+ gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+ };
+
+ connect_blue {
+ label = "fritzwlan-3000:blue:connect";
+ gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ };
+
+ power_led: power {
+ label = "fritzwlan-3000:green:power";
+ gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&tlmm {
+ serial_0_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x000000 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "MIBIB";
+ reg = <0x080000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "QSEE";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "CDT";
+ reg = <0x180000 0x40000>;
+ read-only;
+ };
+
+ partition@1c0000 {
+ label = "QSEE_B";
+ reg = <0x1c0000 0x80000>;
+ read-only;
+ };
+
+ partition@240000 {
+ label = "urlader0";
+ reg = <0x240000 0x40000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "urlader1";
+ reg = <0x280000 0x40000>;
+ read-only;
+ };
+
+ partition@2c0000 {
+ label = "nand-tffs";
+ reg = <0x2c0000 0x840000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ /* 'kernel1' in AVM firmware */
+ label = "uboot0";
+ reg = <0xb00000 0x400000>;
+ };
+
+ partition@f00000 {
+ /* 'kernel2' in AVM firmware */
+ label = "uboot1";
+ reg = <0xf00000 0x400000>;
+ };
+
+ partition@1300000 {
+ label = "ubi";
+ reg = <0x1300000 0x6d00000>;
+ };
+ };
+ };
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ /* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
+ qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
+};
+
+&wifi1 {
+ status = "okay";
+ ieee80211-freq-limit = <5170000 5350000>;
+ /* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
+ qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ /* QCA9984 */
+ compatible = "qcom,ath10k";
+ status = "okay";
+ reg = <0x00010000 0 0 0 0>;
+ ieee80211-freq-limit = <5470000 5875000>;
+ /* Uses the reference BDF */
+ };
+ };
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts
new file mode 100644
index 0000000000..a063f8e952
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/dts-v1/;
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "ASUS Lyra MAP-AC2200";
+ compatible = "asus,map-ac2200";
+
+ aliases {
+ led-boot = &led_blue0;
+ led-failsafe = &led_red0;
+ led-running = &led_blue0;
+ led-upgrade = &led_red0;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SBL1";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "MIBIB";
+ reg = <0x80000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "QSEE";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "CDT";
+ reg = <0x200000 0x80000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "APPSBL";
+ reg = <0x280000 0x140000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "APPSBLENV";
+ reg = <0x3c0000 0x40000>;
+ read-only;
+ };
+
+ partition@400000 {
+ label = "ubi";
+ reg = <0x400000 0x7c00000>;
+ };
+ };
+ };
+};
+
+&tlmm {
+ i2c_0_pins: i2c_0_pinmux {
+ pinmux {
+ function = "blsp_i2c0";
+ pins = "gpio20", "gpio21";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58",
+ "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
+ ieee80211-freq-limit = <5470000 5875000>;
+};
+
+&pcie0 {
+ status = "okay";
+ perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi2: wifi@1,0 {
+ compatible = "qcom,ath10k";
+ status = "okay";
+ reg = <0x00010000 0 0 0 0>;
+ qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
+ ieee80211-freq-limit = <5170000 5350000>;
+ };
+ };
+};
+
+&usb2_hs_phy {
+ /* Bluetooth module attached via USB */
+ status = "okay";
+};
+
+&blsp1_i2c3 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ led-controller@32 {
+ /* 9-channel RGB LED controller */
+ compatible = "national,lp5523";
+ reg = <0x32>;
+ clock-mode = [01];
+
+ led_blue0: blue0 {
+ chan-name = "blue0";
+ label = "map-ac2200:blue:chan0";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ blue1 {
+ chan-name = "blue1";
+ label = "map-ac2200:blue:chan1";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ blue2 {
+ chan-name = "blue2";
+ label = "map-ac2200:blue:chan2";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ led_green0: green0 {
+ chan-name = "green0";
+ label = "map-ac2200:green:chan0";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ green1 {
+ chan-name = "green1";
+ label = "map-ac2200:green:chan1";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ green2 {
+ chan-name = "green2";
+ label = "map-ac2200:green:chan2";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ led_red0: red0 {
+ chan-name = "red0";
+ label = "map-ac2200:red:chan0";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ red1 {
+ chan-name = "red1";
+ label = "map-ac2200:red:chan1";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+
+ red2 {
+ chan-name = "red2";
+ label = "map-ac2200:red:chan2";
+ led-cur = [fa];
+ max-cur = [ff];
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts
new file mode 100644
index 0000000000..63fbfb65c1
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "qcom-ipq4019-u4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Unielec U4019 (32M)";
+ compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <24000000>;
+ broken-flash-reset;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ partition@f0000 {
+ label = "0:APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ partition@170000 {
+ label = "0:ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ partition@180000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x180000 0x1e80000>;
+ };
+ };
+ };
+};
+
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi
new file mode 100644
index 0000000000..c768e25ca0
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ compatible = "unielec,u4019","qcom,ipq4019";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+
+ dwc3@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+
+ dwc3@8a00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ aliases {
+ led-boot = &led_status;
+ led-failsafe = &led_status;
+ led-running = &led_status;
+ led-upgrade = &led_status;
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&led_pins>;
+ pinctrl-names = "default";
+
+ led_status: led2 {
+ label = "u4019:green:led2";
+ gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&tlmm {
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial_0_pins: serial0-pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ led_pins: led_pinmux {
+ mux {
+ function = "gpio";
+ pins = "gpio68";
+ bias-disabled;
+ output-low;
+ };
+ };
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts
new file mode 100644
index 0000000000..6cf9d46767
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts
@@ -0,0 +1,375 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Compex WPJ419";
+ compatible = "compex,wpj419", "qcom,ipq4019";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ reserved-memory {
+ ranges;
+ rsvd1@87000000 {
+ /* Reserved for other subsystem */
+ reg = <0x87000000 0x500000>;
+ no-map;
+ };
+ wifi_dump@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ rsvd2@87B00000 {
+ /* Reserved for other subsystem */
+ reg = <0x87B00000 0x500000>;
+ no-map;
+ };
+ };
+
+ chosen {
+ bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1 clk_ignore_unused";
+ };
+
+ soc {
+ pinctrl@1000000 {
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial_0_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+
+ led_0_pins: led0_pinmux {
+ mux_1 {
+ pins = "gpio36";
+ function = "led0";
+ bias-pull-down;
+ };
+ mux_2 {
+ pins = "gpio40";
+ function = "led4";
+ bias-pull-down;
+ };
+ };
+ };
+
+ blsp_dma: dma@7884000 {
+ status = "okay";
+ };
+
+ spi_0: spi@78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
+ num-cs = <2>;
+
+ flash0@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <24000000>;
+ broken-flash-reset;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x000000 0x040000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x040000 0x020000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x060000 0x060000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0x0c0000 0x010000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0x0d0000 0x010000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0x0e0000 0x010000>;
+ };
+
+ partition@f0000 {
+ label = "u-boot";
+ reg = <0x0f0000 0x080000>;
+ read-only;
+ };
+
+ partition@170000 {
+ label = "0:ART";
+ reg = <0x170000 0x010000>;
+ read-only;
+ };
+ };
+ };
+
+ nand@1 {
+ reg = <1>;
+ status = "okay";
+ compatible = "spi-nand";
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* The device has 128MB, but we can only address
+ * 64MB because of the bootloader's default settings.
+ * This is due to the old mt29f driver,
+ * which detected the deivce with only 64MB
+ */
+ partition@0 {
+ label = "ubi";
+ reg = <0x0000000 0x4000000>;
+ };
+ };
+ };
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <5000>;
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ i2c_0: i2c@78b7000 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ cryptobam: dma@8e04000 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ switch_lan_bmp = <0x1e>;
+ switch_wan_bmp = <0x20>;
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ qpic_bam: dma@7984000 {
+ status = "okay";
+ };
+
+ pcie0: pci@40000000 {
+ status = "okay";
+ perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+ };
+
+ nand: qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+ qcom,phy_mdio_addr = <3>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <1 0x10>;
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts
new file mode 100644
index 0000000000..cf8540c101
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts
@@ -0,0 +1,270 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
+ * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Compex WPJ428";
+ compatible = "compex,wpj428";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ switch_lan_bmp = <0x10>;
+ switch_wan_bmp = <0x20>;
+
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ aliases {
+ led-boot = &status;
+ led-failsafe = &status;
+ led-upgrade = &status;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status: rss4 {
+ label = "wpj428:green:rss4";
+ gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ rss3 {
+ label = "wpj428:green:rss3";
+ gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ beeper: beeper {
+ compatible = "gpio-beeper";
+ gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition0@0 {
+ label = "0:SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition1@40000 {
+ label = "0:MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+ partition2@60000 {
+ label = "0:QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+ partition3@c0000 {
+ label = "0:CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+ partition4@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+ partition5@e0000 {
+ label = "0:APPSBLENV"; /* uboot env*/
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+ partition5@f0000 {
+ label = "0:APPSBL"; /* uboot */
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+ partition5@170000 {
+ label = "0:ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+ };
+ partition6@180000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x00180000 0x01e80000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+ qcom,phy_mdio_addr = <3>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <1 0x10>;
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts
new file mode 100644
index 0000000000..24e5dc2809
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Aruba AP-303";
+ compatible = "aruba,ap-303";
+
+ aliases {
+ led-boot = &led_system_green;
+ led-failsafe = &led_system_red;
+ led-running = &led_system_green;
+ led-upgrade = &led_system_red;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ /delete-node/ ethernet-phy@0;
+ /delete-node/ ethernet-phy@2;
+ /delete-node/ ethernet-phy@3;
+ /delete-node/ ethernet-phy@4;
+
+ ethernet-phy@5 {
+ reg = <0x5>;
+ };
+ };
+
+ counter@4a1000 {
+ compatible = "qcom,qca-gcnt";
+ reg = <0x4a1000 0x4>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
+ switch_lan_bmp = <0x0>; /* lan port bitmap */
+ switch_wan_bmp = <0x10>; /* wan port bitmap */
+ };
+
+ edma@c080000 {
+ qcom,single-phy;
+ qcom,num_gmac = <1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+ };
+
+ i2c_0: i2c@78b7000 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+
+ tpm@29 {
+ /* No Driver */
+ compatible = "atmel,at97sc3203";
+ reg = <0x29>;
+ read-only;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ wifi_green {
+ label = "ap-303:green:wifi";
+ gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ wifi_amber {
+ label = "ap-303:amber:wifi";
+ gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1tpt";
+ };
+
+ led_system_red: system_red {
+ label = "ap-303:red:system";
+ gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_green: system_green {
+ label = "ap-303:green:system";
+ gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "Reset button";
+ gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ /* Texas Instruments CC2540T BLE radio */
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <5>;
+ qcom,poll_required = <1>;
+ vlan_tag = <0 0x20>;
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&tlmm {
+ /*
+ * In addition to the Pins listed below,
+ * the following GPIOs have "features":
+ * 54 - out - active low to force HW reset
+ * 41 - out - active low to reset TPM
+ * 43 - out - active low to reset BLE radio
+ * 19 - in - active high when DC powered
+ */
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c0";
+ drive-strength = <4>;
+ bias-disable;
+ };
+ };
+
+ serial_0_pins: serial_0_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial_1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ phy-reset {
+ line-name = "PHY-reset";
+ gpios = <42 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ output-high;
+ };
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ /* 'aos0' in Aruba firmware */
+ label = "aos0";
+ reg = <0x0 0x2000000>;
+ read-only;
+ };
+
+ partition@2000000 {
+ /* 'aos1' in AVM firmware */
+ label = "ubi";
+ reg = <0x2000000 0x2000000>;
+ };
+
+ partition@4000000 {
+ label = "aruba-ubifs";
+ reg = <0x4000000 0x4000000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * There is no partition map for the NOR flash
+ * in the stock firmware.
+ *
+ * All partitions here are based on offsets
+ * found in the U-Boot GPL code and information
+ * from smem.
+ */
+
+ partition@0 {
+ label = "sbl1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "mibib";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "qsee";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "cdt";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "ddrparams";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "ART";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+
+ partition@f0000 {
+ label = "appsbl";
+ reg = <0xf0000 0xf0000>;
+ read-only;
+ };
+
+ partition@1e0000 {
+ label = "mfginfo";
+ reg = <0x1e0000 0x10000>;
+ read-only;
+ };
+
+ partition@1f0000 {
+ label = "apcd";
+ reg = <0x1f0000 0x10000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "osss";
+ reg = <0x200000 0x180000>;
+ read-only;
+ };
+
+ partition@380000 {
+ /* This is empty */
+ label = "appsblenv";
+ reg = <0x380000 0x10000>;
+ read-only;
+ };
+
+ partition@390000 {
+ label = "pds";
+ reg = <0x390000 0x10000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "fcache";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ /* Called osss1 in smem */
+ label = "u-boot-env-bak";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3f0000 {
+ label = "u-boot-env";
+ reg = <0x3f0000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Aruba-AP-303";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Aruba-AP-303";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts
new file mode 100644
index 0000000000..0859f97c9e
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Aruba AP-303H";
+ compatible = "aruba,ap-303h";
+
+ aliases {
+ led-boot = &led_system_green;
+ led-failsafe = &led_system_red;
+ led-running = &led_system_green;
+ led-upgrade = &led_system_amber;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+ };
+
+ counter@4a1000 {
+ compatible = "qcom,qca-gcnt";
+ reg = <0x4a1000 0x4>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ i2c_0: i2c@78b7000 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+
+ tpm@29 {
+ /* No Driver */
+ compatible = "atmel,at97sc3203";
+ reg = <0x29>;
+ read-only;
+ };
+
+ power-monitor@40 {
+ /* No driver */
+ compatible = "isl,isl28022";
+ reg = <0x40>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ wifi_green {
+ label = "ap-303h:green:wifi";
+ gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ wifi_amber {
+ label = "ap-303h:amber:wifi";
+ gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1tpt";
+ };
+
+ pse {
+ label = "ap-303h:green:pse";
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_red: system_red {
+ label = "ap-303h:red:system";
+ gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_green: system_green {
+ label = "ap-303h:green:system";
+ gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_amber: system_amber {
+ label = "ap-303h:amber:system";
+ gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "Reset button";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart2 {
+ /* Texas Instruments CC2540T BLE radio */
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&tlmm {
+ /*
+ * In addition to the Pins listed below,
+ * the following GPIOs have "features":
+ * 39 - out - active low to force HW reset
+ * 32 - out - active low to reset TPM
+ * 43 - out - active low to reset BLE radio
+ * 41 - out - pulse to set warm reset status
+ * 34 - out - active low to enable PSE port
+ * 22 - in - active low when 802.3at powered
+ * 29 - in - active high when DC powered
+ * 40 - in - active low when reset due to cold HW reset
+ * 30 - in - active low when USB overcurrent detected
+ * 35 - in - interrupt line for power monitor chip
+ * 31 - in - active low when PSE port active
+ */
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pin {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pin_cs {
+ function = "gpio";
+ pins = "gpio12", "gpio59";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ drive-strength = <4>;
+ bias-disable;
+ };
+ };
+
+ serial_0_pins: serial_0_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial_1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ usb-power {
+ line-name = "USB-power";
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ output-high;
+ };
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * There is no partition map for the NOR flash
+ * in the stock firmware.
+ *
+ * All partitions here are based on offsets
+ * found in the U-Boot GPL code and information
+ * from smem.
+ */
+
+ partition@0 {
+ label = "sbl1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "mibib";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "qsee";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "cdt";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "ddrparams";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "appsblenv";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+
+ partition@f0000 {
+ label = "appsbl";
+ reg = <0xf0000 0x100000>;
+ read-only;
+ };
+
+ partition@1e0000 {
+ label = "ART";
+ reg = <0x1f0000 0x10000>;
+ read-only;
+ };
+
+ partition@1f0000 {
+ label = "osss";
+ reg = <0x200000 0x170000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "pds";
+ reg = <0x370000 0x10000>;
+ read-only;
+ };
+
+ partition@380000 {
+ label = "apcd";
+ reg = <0x380000 0x10000>;
+ read-only;
+ };
+
+ partition@390000 {
+ label = "mfginfo";
+ reg = <0x390000 0x10000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "fcache";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ /* Called osss1 in smem */
+ label = "u-boot-env-bak";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3f0000 {
+ label = "u-boot-env";
+ reg = <0x3c0000 0x40000>;
+ read-only;
+ };
+ };
+ };
+
+ flash@1 {
+ status = "okay";
+
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ /* 'aos0' in Aruba firmware */
+ label = "aos0";
+ reg = <0x0 0x2000000>;
+ read-only;
+ };
+
+ partition@2000000 {
+ /* 'aos1' in Aruba firmware */
+ label = "ubi";
+ reg = <0x2000000 0x2000000>;
+ };
+
+ partition@4000000 {
+ label = "aruba-ubifs";
+ reg = <0x4000000 0x4000000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Aruba-AP-303";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Aruba-AP-303";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts
new file mode 100644
index 0000000000..b32eb29f8c
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts
@@ -0,0 +1,280 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "GL.iNet GL-B1300";
+ compatible = "glinet,gl-b1300";
+
+ aliases {
+ led-boot = &power;
+ led-failsafe = &power;
+ led-running = &power;
+ led-upgrade = &power;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ switch_lan_bmp = <0x18>;
+ switch_wan_bmp = <0x20>;
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power: power {
+ label = "gl-b1300:green:power";
+ gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ mesh {
+ label = "gl-b1300:green:mesh";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan {
+ label = "gl-b1300:green:wlan";
+ gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ mx25l25635f@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ SBL1@0 {
+ label = "SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ MIBIB@40000 {
+ label = "MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+
+ QSEE@60000 {
+ label = "QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+
+ CDT@c0000 {
+ label = "CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+
+ DDRPARAMS@d0000 {
+ label = "DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+
+ APPSBLENV@e0000 {
+ label = "APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+
+ APPSBL@f0000 {
+ label = "APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+
+ ART@170000 {
+ label = "ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+
+ firmware@180000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x180000 0x1e80000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio54";
+ };
+ pinconf {
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "GL-B1300";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "GL-B1300";
+};
diff --git a/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-mr33.dts b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-mr33.dts
new file mode 100644
index 0000000000..5003572420
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4029-mr33.dts
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Meraki MR33 (Stinkbug)
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Meraki MR33 Access Point";
+ compatible = "meraki,mr33";
+
+ aliases {
+ led-boot = &status_green;
+ led-failsafe = &status_red;
+ led-running = &status_green;
+ led-upgrade = &power_orange;
+ };
+
+ /* Do we really need this defined? */
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ };
+
+ /* It is a 56-bit counter that supplies the count to the ARM arch
+ timers and without upstream driver */
+ counter@4a1000 {
+ compatible = "qcom,qca-gcnt";
+ reg = <0x4a1000 0x4>;
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "ti,cc2650";
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
+ switch_lan_bmp = <0x0>; /* lan port bitmap */
+ switch_wan_bmp = <0x10>; /* wan port bitmap */
+ };
+
+ edma@c080000 {
+ qcom,single-phy;
+ qcom,num_gmac = <1>;
+ phy-mode = "rgmii-rxid";
+ status = "okay";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power_orange: power {
+ label = "mr33:orange:power";
+ gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
+ panic-indicator;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&gmac0 {
+ qcom,phy_mdio_addr = <1>;
+ qcom,poll_required = <1>;
+ vlan_tag = <0 0x20>;
+};
+
+&blsp1_i2c3 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ at24@50 {
+ compatible = "atmel,24c64";
+ pagesize = <32>;
+ reg = <0x50>;
+ read-only; /* This holds our MAC & Meraki board-data */
+ };
+};
+
+&blsp1_i2c4 {
+ pinctrl-0 = <&i2c_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ led-controller@30 {
+ compatible = "ti,lp5562";
+ reg = <0x30>;
+ clock-mode = /bits/8 <2>;
+ enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+ /* RGB led */
+ status_red: chan0 {
+ chan-name = "mr33:red:status";
+ led-cur = /bits/ 8 <0x20>;
+ max-cur = /bits/ 8 <0x60>;
+ };
+
+ status_green: chan1 {
+ chan-name = "mr33:green:status";
+ led-cur = /bits/ 8 <0x20>;
+ max-cur = /bits/ 8 <0x60>;
+ };
+
+ chan2 {
+ chan-name = "mr33:blue:status";
+ led-cur = /bits/ 8 <0x20>;
+ max-cur = /bits/ 8 <0x60>;
+ };
+
+ chan3 {
+ chan-name = "mr33:white:status";
+ led-cur = /bits/ 8 <0x20>;
+ max-cur = /bits/ 8 <0x60>;
+ };
+ };
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "sbl1";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition@100000 {
+ label = "mibib";
+ reg = <0x00100000 0x00100000>;
+ read-only;
+ };
+ partition@200000 {
+ label = "bootconfig";
+ reg = <0x00200000 0x00100000>;
+ read-only;
+ };
+ partition@300000 {
+ label = "qsee";
+ reg = <0x00300000 0x00100000>;
+ read-only;
+ };
+ partition@400000 {
+ label = "qsee_alt";
+ reg = <0x00400000 0x00100000>;
+ read-only;
+ };
+ partition@500000 {
+ label = "cdt";
+ reg = <0x00500000 0x00080000>;
+ read-only;
+ };
+ partition@580000 {
+ label = "cdt_alt";
+ reg = <0x00580000 0x00080000>;
+ read-only;
+ };
+ partition@600000 {
+ label = "ddrparams";
+ reg = <0x00600000 0x00080000>;
+ read-only;
+ };
+ partition@700000 {
+ label = "u-boot";
+ reg = <0x00700000 0x00200000>;
+ read-only;
+ };
+ partition@900000 {
+ label = "u-boot-backup";
+ reg = <0x00900000 0x00200000>;
+ read-only;
+ };
+ partition@b00000 {
+ label = "ART";
+ reg = <0x00b00000 0x00080000>;
+ read-only;
+ };
+ partition@c00000 {
+ label = "ubi";
+ reg = <0x00c00000 0x07000000>;
+ /*
+ * Do not try to allocate the remaining
+ * 4 MiB to this ubi partition. It will
+ * confuse the u-boot and it might not
+ * find the kernel partition anymore.
+ */
+ };
+ };
+ };
+};
+
+&pcie0 {
+ status = "okay";
+ perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi2: wifi@1,0 {
+ compatible = "qcom,ath10k";
+ status = "okay";
+ reg = <0x00010000 0 0 0 0>;
+ };
+ };
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&tlmm {
+ /*
+ * GPIO43 should be 0/1 whenever the unit is
+ * powered through PoE or AC-Adapter.
+ * That said, playing with this seems to
+ * reset the AP.
+ */
+
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial_0_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial1_pinmux {
+ mux {
+ /* We use the i2c-0 pins for serial_1 */
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ pinmux {
+ function = "blsp_i2c0";
+ pins = "gpio20", "gpio21";
+ };
+ pinconf {
+ pins = "gpio20", "gpio21";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ i2c_1_pins: i2c_1_pinmux {
+ pinmux {
+ function = "blsp_i2c1";
+ pins = "gpio34", "gpio35";
+ };
+ pinconf {
+ pins = "gpio34", "gpio35";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ /*
+ * There are 18 pins. 15 pins are common between LCD and NAND.
+ * The QPIC controller arbitrates between LCD and NAND. Of the
+ * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
+ *
+ * The meraki source hints that the bluetooth module claims
+ * pin 52 as well. But sadly, there's no data whenever this
+ * is a NAND or LCD exclusive pin or not.
+ */
+
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58",
+ "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+};
+
+&wifi0 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Meraki-MR33";
+};
+
+&wifi1 {
+ status = "okay";
+ qcom,ath10k-calibration-variant = "Meraki-MR33";
+};
diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/Makefile b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/Makefile
new file mode 100644
index 0000000000..4e6cd6505e
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/Makefile
@@ -0,0 +1,9 @@
+#
+## Makefile for the Qualcomm Atheros ethernet edma driver
+#
+
+
+obj-$(CONFIG_ESSEDMA) += essedma.o
+
+essedma-objs := edma_axi.o edma.o edma_ethtool.o
+
diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.c b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.c
new file mode 100644
index 0000000000..5561cc23ea
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.c
@@ -0,0 +1,2177 @@
+/*
+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/if_vlan.h>
+#include "ess_edma.h"
+#include "edma.h"
+
+extern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
+bool edma_stp_rstp;
+u16 edma_ath_eth_type;
+
+/* edma_skb_priority_offset()
+ * get edma skb priority
+ */
+static unsigned int edma_skb_priority_offset(struct sk_buff *skb)
+{
+ return (skb->priority >> 2) & 1;
+}
+
+/* edma_alloc_tx_ring()
+ * Allocate Tx descriptors ring
+ */
+static int edma_alloc_tx_ring(struct edma_common_info *edma_cinfo,
+ struct edma_tx_desc_ring *etdr)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+
+ /* Initialize ring */
+ etdr->size = sizeof(struct edma_sw_desc) * etdr->count;
+ etdr->sw_next_to_fill = 0;
+ etdr->sw_next_to_clean = 0;
+
+ /* Allocate SW descriptors */
+ etdr->sw_desc = vzalloc(etdr->size);
+ if (!etdr->sw_desc) {
+ dev_err(&pdev->dev, "buffer alloc of tx ring failed=%p", etdr);
+ return -ENOMEM;
+ }
+
+ /* Allocate HW descriptors */
+ etdr->hw_desc = dma_alloc_coherent(&pdev->dev, etdr->size, &etdr->dma,
+ GFP_KERNEL);
+ if (!etdr->hw_desc) {
+ dev_err(&pdev->dev, "descriptor allocation for tx ring failed");
+ vfree(etdr->sw_desc);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/* edma_free_tx_ring()
+ * Free tx rings allocated by edma_alloc_tx_rings
+ */
+static void edma_free_tx_ring(struct edma_common_info *edma_cinfo,
+ struct edma_tx_desc_ring *etdr)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+
+ if (likely(etdr->dma))
+ dma_free_coherent(&pdev->dev, etdr->size, etdr->hw_desc,
+ etdr->dma);
+
+ vfree(etdr->sw_desc);
+ etdr->sw_desc = NULL;
+}
+
+/* edma_alloc_rx_ring()
+ * allocate rx descriptor ring
+ */
+static int edma_alloc_rx_ring(struct edma_common_info *edma_cinfo,
+ struct edma_rfd_desc_ring *erxd)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+
+ erxd->size = sizeof(struct edma_sw_desc) * erxd->count;
+ erxd->sw_next_to_fill = 0;
+ erxd->sw_next_to_clean = 0;
+
+ /* Allocate SW descriptors */
+ erxd->sw_desc = vzalloc(erxd->size);
+ if (!erxd->sw_desc)
+ return -ENOMEM;
+
+ /* Alloc HW descriptors */
+ erxd->hw_desc = dma_alloc_coherent(&pdev->dev, erxd->size, &erxd->dma,
+ GFP_KERNEL);
+ if (!erxd->hw_desc) {
+ vfree(erxd->sw_desc);
+ return -ENOMEM;
+ }
+
+ /* Initialize pending_fill */
+ erxd->pending_fill = 0;
+
+ return 0;
+}
+
+/* edma_free_rx_ring()
+ * Free rx ring allocated by alloc_rx_ring
+ */
+static void edma_free_rx_ring(struct edma_common_info *edma_cinfo,
+ struct edma_rfd_desc_ring *rxdr)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+
+ if (likely(rxdr->dma))
+ dma_free_coherent(&pdev->dev, rxdr->size, rxdr->hw_desc,
+ rxdr->dma);
+
+ vfree(rxdr->sw_desc);
+ rxdr->sw_desc = NULL;
+}
+
+/* edma_configure_tx()
+ * Configure transmission control data
+ */
+static void edma_configure_tx(struct edma_common_info *edma_cinfo)
+{
+ u32 txq_ctrl_data;
+
+ txq_ctrl_data = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT);
+ txq_ctrl_data |= EDMA_TXQ_CTRL_TPD_BURST_EN;
+ txq_ctrl_data |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT);
+ edma_write_reg(EDMA_REG_TXQ_CTRL, txq_ctrl_data);
+}
+
+
+/* edma_configure_rx()
+ * configure reception control data
+ */
+static void edma_configure_rx(struct edma_common_info *edma_cinfo)
+{
+ struct edma_hw *hw = &edma_cinfo->hw;
+ u32 rss_type, rx_desc1, rxq_ctrl_data;
+
+ /* Set RSS type */
+ rss_type = hw->rss_type;
+ edma_write_reg(EDMA_REG_RSS_TYPE, rss_type);
+
+ /* Set RFD burst number */
+ rx_desc1 = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT);
+
+ /* Set RFD prefetch threshold */
+ rx_desc1 |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT);
+
+ /* Set RFD in host ring low threshold to generte interrupt */
+ rx_desc1 |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT);
+ edma_write_reg(EDMA_REG_RX_DESC1, rx_desc1);
+
+ /* Set Rx FIFO threshold to start to DMA data to host */
+ rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE;
+
+ if (!edma_cinfo->is_single_phy) {
+ /* Set RX remove vlan bit */
+ rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN;
+ }
+
+ edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data);
+}
+
+/* edma_alloc_rx_buf()
+ * does skb allocation for the received packets.
+ */
+static int edma_alloc_rx_buf(struct edma_common_info
+ *edma_cinfo,
+ struct edma_rfd_desc_ring *erdr,
+ int cleaned_count, int queue_id)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+ struct edma_rx_free_desc *rx_desc;
+ struct edma_sw_desc *sw_desc;
+ struct sk_buff *skb;
+ unsigned int i;
+ u16 prod_idx, length;
+ u32 reg_data;
+
+ if (cleaned_count > erdr->count)
+ cleaned_count = erdr->count - 1;
+
+ i = erdr->sw_next_to_fill;
+
+ while (cleaned_count) {
+ sw_desc = &erdr->sw_desc[i];
+ length = edma_cinfo->rx_head_buffer_len;
+
+ if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_REUSE) {
+ skb = sw_desc->skb;
+
+ /* Clear REUSE Flag */
+ sw_desc->flags &= ~EDMA_SW_DESC_FLAG_SKB_REUSE;
+ } else {
+ /* alloc skb */
+ skb = netdev_alloc_skb_ip_align(edma_netdev[0], length);
+ if (!skb) {
+ /* Better luck next round */
+ break;
+ }
+ }
+
+ if (edma_cinfo->page_mode) {
+ struct page *pg = alloc_page(GFP_ATOMIC);
+
+ if (!pg) {
+ dev_kfree_skb_any(skb);
+ break;
+ }
+
+ sw_desc->dma = dma_map_page(&pdev->dev, pg, 0,
+ edma_cinfo->rx_page_buffer_len,
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(&pdev->dev,
+ sw_desc->dma)) {
+ __free_page(pg);
+ dev_kfree_skb_any(skb);
+ break;
+ }
+
+ skb_fill_page_desc(skb, 0, pg, 0,
+ edma_cinfo->rx_page_buffer_len);
+ sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_FRAG;
+ sw_desc->length = edma_cinfo->rx_page_buffer_len;
+ } else {
+ sw_desc->dma = dma_map_single(&pdev->dev, skb->data,
+ length, DMA_FROM_DEVICE);
+ if (dma_mapping_error(&pdev->dev,
+ sw_desc->dma)) {
+ dev_kfree_skb_any(skb);
+ break;
+ }
+
+ sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_HEAD;
+ sw_desc->length = length;
+ }
+
+ /* Update the buffer info */
+ sw_desc->skb = skb;
+ rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[i]);
+ rx_desc->buffer_addr = cpu_to_le64(sw_desc->dma);
+ if (++i == erdr->count)
+ i = 0;
+ cleaned_count--;
+ }
+
+ erdr->sw_next_to_fill = i;
+
+ if (i == 0)
+ prod_idx = erdr->count - 1;
+ else
+ prod_idx = i - 1;
+
+ /* Update the producer index */
+ edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &reg_data);
+ reg_data &= ~EDMA_RFD_PROD_IDX_BITS;
+ reg_data |= prod_idx;
+ edma_write_reg(EDMA_REG_RFD_IDX_Q(queue_id), reg_data);
+
+ /* If we couldn't allocate all the buffers
+ * we increment the alloc failure counters
+ */
+ if (cleaned_count)
+ edma_cinfo->edma_ethstats.rx_alloc_fail_ctr++;
+
+ return cleaned_count;
+}
+
+/* edma_init_desc()
+ * update descriptor ring size, buffer and producer/consumer index
+ */
+static void edma_init_desc(struct edma_common_info *edma_cinfo)
+{
+ struct edma_rfd_desc_ring *rfd_ring;
+ struct edma_tx_desc_ring *etdr;
+ int i = 0, j = 0;
+ u32 data = 0;
+ u16 hw_cons_idx = 0;
+
+ /* Set the base address of every TPD ring. */
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
+ etdr = edma_cinfo->tpd_ring[i];
+
+ /* Update descriptor ring base address */
+ edma_write_reg(EDMA_REG_TPD_BASE_ADDR_Q(i), (u32)etdr->dma);
+ edma_read_reg(EDMA_REG_TPD_IDX_Q(i), &data);
+
+ /* Calculate hardware consumer index */
+ hw_cons_idx = (data >> EDMA_TPD_CONS_IDX_SHIFT) & 0xffff;
+ etdr->sw_next_to_fill = hw_cons_idx;
+ etdr->sw_next_to_clean = hw_cons_idx;
+ data &= ~(EDMA_TPD_PROD_IDX_MASK << EDMA_TPD_PROD_IDX_SHIFT);
+ data |= hw_cons_idx;
+
+ /* update producer index */
+ edma_write_reg(EDMA_REG_TPD_IDX_Q(i), data);
+
+ /* update SW consumer index register */
+ edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(i), hw_cons_idx);
+
+ /* Set TPD ring size */
+ edma_write_reg(EDMA_REG_TPD_RING_SIZE,
+ edma_cinfo->tx_ring_count &
+ EDMA_TPD_RING_SIZE_MASK);
+ }
+
+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
+ rfd_ring = edma_cinfo->rfd_ring[j];
+ /* Update Receive Free descriptor ring base address */
+ edma_write_reg(EDMA_REG_RFD_BASE_ADDR_Q(j),
+ (u32)(rfd_ring->dma));
+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+ }
+
+ data = edma_cinfo->rx_head_buffer_len;
+ if (edma_cinfo->page_mode)
+ data = edma_cinfo->rx_page_buffer_len;
+
+ data &= EDMA_RX_BUF_SIZE_MASK;
+ data <<= EDMA_RX_BUF_SIZE_SHIFT;
+
+ /* Update RFD ring size and RX buffer size */
+ data |= (edma_cinfo->rx_ring_count & EDMA_RFD_RING_SIZE_MASK)
+ << EDMA_RFD_RING_SIZE_SHIFT;
+
+ edma_write_reg(EDMA_REG_RX_DESC0, data);
+
+ /* Disable TX FIFO low watermark and high watermark */
+ edma_write_reg(EDMA_REG_TXF_WATER_MARK, 0);
+
+ /* Load all of base address above */
+ edma_read_reg(EDMA_REG_TX_SRAM_PART, &data);
+ data |= 1 << EDMA_LOAD_PTR_SHIFT;
+ edma_write_reg(EDMA_REG_TX_SRAM_PART, data);
+}
+
+/* edma_receive_checksum
+ * Api to check checksum on receive packets
+ */
+static void edma_receive_checksum(struct edma_rx_return_desc *rd,
+ struct sk_buff *skb)
+{
+ skb_checksum_none_assert(skb);
+
+ /* check the RRD IP/L4 checksum bit to see if
+ * its set, which in turn indicates checksum
+ * failure.
+ */
+ if (rd->rrd6 & EDMA_RRD_CSUM_FAIL_MASK)
+ return;
+
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+}
+
+/* edma_clean_rfd()
+ * clean up rx resourcers on error
+ */
+static void edma_clean_rfd(struct edma_rfd_desc_ring *erdr, u16 index)
+{
+ struct edma_rx_free_desc *rx_desc;
+ struct edma_sw_desc *sw_desc;
+
+ rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[index]);
+ sw_desc = &erdr->sw_desc[index];
+ if (sw_desc->skb) {
+ dev_kfree_skb_any(sw_desc->skb);
+ sw_desc->skb = NULL;
+ }
+
+ memset(rx_desc, 0, sizeof(struct edma_rx_free_desc));
+}
+
+/* edma_rx_complete_fraglist()
+ * Complete Rx processing for fraglist skbs
+ */
+static void edma_rx_complete_stp_rstp(struct sk_buff *skb, int port_id, struct edma_rx_return_desc *rd)
+{
+ int i;
+ u32 priority;
+ u16 port_type;
+ u8 mac_addr[EDMA_ETH_HDR_LEN];
+
+ port_type = (rd->rrd1 >> EDMA_RRD_PORT_TYPE_SHIFT)
+ & EDMA_RRD_PORT_TYPE_MASK;
+ /* if port type is 0x4, then only proceed with
+ * other stp/rstp calculation
+ */
+ if (port_type == EDMA_RX_ATH_HDR_RSTP_PORT_TYPE) {
+ u8 bpdu_mac[6] = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x00};
+
+ /* calculate the frame priority */
+ priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)
+ & EDMA_RRD_PRIORITY_MASK;
+
+ for (i = 0; i < EDMA_ETH_HDR_LEN; i++)
+ mac_addr[i] = skb->data[i];
+
+ /* Check if destination mac addr is bpdu addr */
+ if (!memcmp(mac_addr, bpdu_mac, 6)) {
+ /* destination mac address is BPDU
+ * destination mac address, then add
+ * atheros header to the packet.
+ */
+ u16 athr_hdr = (EDMA_RX_ATH_HDR_VERSION << EDMA_RX_ATH_HDR_VERSION_SHIFT) |
+ (priority << EDMA_RX_ATH_HDR_PRIORITY_SHIFT) |
+ (EDMA_RX_ATH_HDR_RSTP_PORT_TYPE << EDMA_RX_ATH_PORT_TYPE_SHIFT) | port_id;
+ skb_push(skb, 4);
+ memcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN);
+ *(uint16_t *)&skb->data[12] = htons(edma_ath_eth_type);
+ *(uint16_t *)&skb->data[14] = htons(athr_hdr);
+ }
+ }
+}
+
+/*
+ * edma_rx_complete_fraglist()
+ * Complete Rx processing for fraglist skbs
+ */
+static int edma_rx_complete_fraglist(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,
+ u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+ struct edma_hw *hw = &edma_cinfo->hw;
+ struct sk_buff *skb_temp;
+ struct edma_sw_desc *sw_desc;
+ int i;
+ u16 size_remaining;
+
+ skb->data_len = 0;
+ skb->tail += (hw->rx_head_buff_size - 16);
+ skb->len = skb->truesize = length;
+ size_remaining = length - (hw->rx_head_buff_size - 16);
+
+ /* clean-up all related sw_descs */
+ for (i = 1; i < num_rfds; i++) {
+ struct sk_buff *skb_prev;
+ sw_desc = &erdr->sw_desc[sw_next_to_clean];
+ skb_temp = sw_desc->skb;
+
+ dma_unmap_single(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_FROM_DEVICE);
+
+ if (size_remaining < hw->rx_head_buff_size)
+ skb_put(skb_temp, size_remaining);
+ else
+ skb_put(skb_temp, hw->rx_head_buff_size);
+
+ /*
+ * If we are processing the first rfd, we link
+ * skb->frag_list to the skb corresponding to the
+ * first RFD
+ */
+ if (i == 1)
+ skb_shinfo(skb)->frag_list = skb_temp;
+ else
+ skb_prev->next = skb_temp;
+ skb_prev = skb_temp;
+ skb_temp->next = NULL;
+
+ skb->data_len += skb_temp->len;
+ size_remaining -= skb_temp->len;
+
+ /* Increment SW index */
+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
+ (*cleaned_count)++;
+ }
+
+ return sw_next_to_clean;
+}
+
+/* edma_rx_complete_paged()
+ * Complete Rx processing for paged skbs
+ */
+static int edma_rx_complete_paged(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,
+ u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+ struct sk_buff *skb_temp;
+ struct edma_sw_desc *sw_desc;
+ int i;
+ u16 size_remaining;
+
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
+
+ /* Setup skbuff fields */
+ skb->len = length;
+
+ if (likely(num_rfds <= 1)) {
+ skb->data_len = length;
+ skb->truesize += edma_cinfo->rx_page_buffer_len;
+ skb_fill_page_desc(skb, 0, skb_frag_page(frag),
+ 16, length);
+ } else {
+ skb_frag_size_sub(frag, 16);
+ skb->data_len = skb_frag_size(frag);
+ skb->truesize += edma_cinfo->rx_page_buffer_len;
+ size_remaining = length - skb_frag_size(frag);
+
+ skb_fill_page_desc(skb, 0, skb_frag_page(frag),
+ 16, skb_frag_size(frag));
+
+ /* clean-up all related sw_descs */
+ for (i = 1; i < num_rfds; i++) {
+ sw_desc = &erdr->sw_desc[sw_next_to_clean];
+ skb_temp = sw_desc->skb;
+ frag = &skb_shinfo(skb_temp)->frags[0];
+ dma_unmap_page(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_FROM_DEVICE);
+
+ if (size_remaining < edma_cinfo->rx_page_buffer_len)
+ skb_frag_size_set(frag, size_remaining);
+
+ skb_fill_page_desc(skb, i, skb_frag_page(frag),
+ 0, skb_frag_size(frag));
+
+ skb_shinfo(skb_temp)->nr_frags = 0;
+ dev_kfree_skb_any(skb_temp);
+
+ skb->data_len += skb_frag_size(frag);
+ skb->truesize += edma_cinfo->rx_page_buffer_len;
+ size_remaining -= skb_frag_size(frag);
+
+ /* Increment SW index */
+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
+ (*cleaned_count)++;
+ }
+ }
+
+ return sw_next_to_clean;
+}
+
+/*
+ * edma_rx_complete()
+ * Main api called from the poll function to process rx packets.
+ */
+static u16 edma_rx_complete(struct edma_common_info *edma_cinfo,
+ int *work_done, int work_to_do, int queue_id,
+ struct napi_struct *napi)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+ struct edma_rfd_desc_ring *erdr = edma_cinfo->rfd_ring[queue_id];
+ struct net_device *netdev;
+ struct edma_adapter *adapter;
+ struct edma_sw_desc *sw_desc;
+ struct sk_buff *skb;
+ struct edma_rx_return_desc *rd;
+ u16 hash_type, rrd[8], cleaned_count = 0, length = 0, num_rfds = 1,
+ sw_next_to_clean, hw_next_to_clean = 0, vlan = 0, ret_count = 0;
+ u32 data = 0;
+ u8 *vaddr;
+ int port_id, i, drop_count = 0;
+ u32 priority;
+ u16 count = erdr->count, rfd_avail;
+ u8 queue_to_rxid[8] = {0, 0, 1, 1, 2, 2, 3, 3};
+
+ cleaned_count = erdr->pending_fill;
+ sw_next_to_clean = erdr->sw_next_to_clean;
+
+ edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);
+ hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &
+ EDMA_RFD_CONS_IDX_MASK;
+
+ do {
+ while (sw_next_to_clean != hw_next_to_clean) {
+ if (!work_to_do)
+ break;
+
+ sw_desc = &erdr->sw_desc[sw_next_to_clean];
+ skb = sw_desc->skb;
+
+ /* Unmap the allocated buffer */
+ if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD))
+ dma_unmap_single(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_FROM_DEVICE);
+ else
+ dma_unmap_page(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_FROM_DEVICE);
+
+ /* Get RRD */
+ if (edma_cinfo->page_mode) {
+ vaddr = kmap_atomic(skb_frag_page(&skb_shinfo(skb)->frags[0]));
+ memcpy((uint8_t *)&rrd[0], vaddr, 16);
+ rd = (struct edma_rx_return_desc *)rrd;
+ kunmap_atomic(vaddr);
+ } else {
+ rd = (struct edma_rx_return_desc *)skb->data;
+ }
+
+ /* Check if RRD is valid */
+ if (!(rd->rrd7 & EDMA_RRD_DESC_VALID)) {
+ edma_clean_rfd(erdr, sw_next_to_clean);
+ sw_next_to_clean = (sw_next_to_clean + 1) &
+ (erdr->count - 1);
+ cleaned_count++;
+ continue;
+ }
+
+ /* Get the number of RFDs from RRD */
+ num_rfds = rd->rrd1 & EDMA_RRD_NUM_RFD_MASK;
+
+ /* Get Rx port ID from switch */
+ port_id = (rd->rrd1 >> EDMA_PORT_ID_SHIFT) & EDMA_PORT_ID_MASK;
+ if ((!port_id) || (port_id > EDMA_MAX_PORTID_SUPPORTED)) {
+ dev_err(&pdev->dev, "Invalid RRD source port bit set");
+ for (i = 0; i < num_rfds; i++) {
+ edma_clean_rfd(erdr, sw_next_to_clean);
+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
+ cleaned_count++;
+ }
+ continue;
+ }
+
+ /* check if we have a sink for the data we receive.
+ * If the interface isn't setup, we have to drop the
+ * incoming data for now.
+ */
+ netdev = edma_cinfo->portid_netdev_lookup_tbl[port_id];
+ if (!netdev) {
+ edma_clean_rfd(erdr, sw_next_to_clean);
+ sw_next_to_clean = (sw_next_to_clean + 1) &
+ (erdr->count - 1);
+ cleaned_count++;
+ continue;
+ }
+ adapter = netdev_priv(netdev);
+
+ /* This code is added to handle a usecase where high
+ * priority stream and a low priority stream are
+ * received simultaneously on DUT. The problem occurs
+ * if one of the Rx rings is full and the corresponding
+ * core is busy with other stuff. This causes ESS CPU
+ * port to backpressure all incoming traffic including
+ * high priority one. We monitor free descriptor count
+ * on each CPU and whenever it reaches threshold (< 80),
+ * we drop all low priority traffic and let only high
+ * priotiy traffic pass through. We can hence avoid
+ * ESS CPU port to send backpressure on high priroity
+ * stream.
+ */
+ priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)
+ & EDMA_RRD_PRIORITY_MASK;
+ if (likely(!priority && !edma_cinfo->page_mode && (num_rfds <= 1))) {
+ rfd_avail = (count + sw_next_to_clean - hw_next_to_clean - 1) & (count - 1);
+ if (rfd_avail < EDMA_RFD_AVAIL_THR) {
+ sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_REUSE;
+ sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
+ adapter->stats.rx_dropped++;
+ cleaned_count++;
+ drop_count++;
+ if (drop_count == 3) {
+ work_to_do--;
+ (*work_done)++;
+ drop_count = 0;
+ }
+ if (cleaned_count >= EDMA_RX_BUFFER_WRITE) {
+ /* If buffer clean count reaches 16, we replenish HW buffers. */
+ ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
+ edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
+ sw_next_to_clean);
+ cleaned_count = ret_count;
+ erdr->pending_fill = ret_count;
+ }
+ continue;
+ }
+ }
+
+ work_to_do--;
+ (*work_done)++;
+
+ /* Increment SW index */
+ sw_next_to_clean = (sw_next_to_clean + 1) &
+ (erdr->count - 1);
+
+ cleaned_count++;
+
+ /* Get the packet size and allocate buffer */
+ length = rd->rrd6 & EDMA_RRD_PKT_SIZE_MASK;
+
+ if (edma_cinfo->page_mode) {
+ /* paged skb */
+ sw_next_to_clean = edma_rx_complete_paged(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);
+ if (!pskb_may_pull(skb, ETH_HLEN)) {
+ dev_kfree_skb_any(skb);
+ continue;
+ }
+ } else {
+ /* single or fraglist skb */
+
+ /* Addition of 16 bytes is required, as in the packet
+ * first 16 bytes are rrd descriptors, so actual data
+ * starts from an offset of 16.
+ */
+ skb_reserve(skb, 16);
+ if (likely((num_rfds <= 1) || !edma_cinfo->fraglist_mode)) {
+ skb_put(skb, length);
+ } else {
+ sw_next_to_clean = edma_rx_complete_fraglist(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);
+ }
+ }
+
+ if (edma_stp_rstp) {
+ edma_rx_complete_stp_rstp(skb, port_id, rd);
+ }
+
+ skb->protocol = eth_type_trans(skb, netdev);
+
+ /* Record Rx queue for RFS/RPS and fill flow hash from HW */
+ skb_record_rx_queue(skb, queue_to_rxid[queue_id]);
+ if (netdev->features & NETIF_F_RXHASH) {
+ hash_type = (rd->rrd5 >> EDMA_HASH_TYPE_SHIFT);
+ if ((hash_type > EDMA_HASH_TYPE_START) && (hash_type < EDMA_HASH_TYPE_END))
+ skb_set_hash(skb, rd->rrd2, PKT_HASH_TYPE_L4);
+ }
+
+#ifdef CONFIG_NF_FLOW_COOKIE
+ skb->flow_cookie = rd->rrd3 & EDMA_RRD_FLOW_COOKIE_MASK;
+#endif
+ edma_receive_checksum(rd, skb);
+
+ /* Process VLAN HW acceleration indication provided by HW */
+ if (unlikely(adapter->default_vlan_tag != rd->rrd4)) {
+ vlan = rd->rrd4;
+ if (likely(rd->rrd7 & EDMA_RRD_CVLAN))
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
+ else if (rd->rrd1 & EDMA_RRD_SVLAN)
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);
+ }
+
+ /* Update rx statistics */
+ adapter->stats.rx_packets++;
+ adapter->stats.rx_bytes += length;
+
+ /* Check if we reached refill threshold */
+ if (cleaned_count >= EDMA_RX_BUFFER_WRITE) {
+ ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
+ edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
+ sw_next_to_clean);
+ cleaned_count = ret_count;
+ erdr->pending_fill = ret_count;
+ }
+
+ /* At this point skb should go to stack */
+ napi_gro_receive(napi, skb);
+ }
+
+ /* Check if we still have NAPI budget */
+ if (!work_to_do)
+ break;
+
+ /* Read index once again since we still have NAPI budget */
+ edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);
+ hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &
+ EDMA_RFD_CONS_IDX_MASK;
+ } while (hw_next_to_clean != sw_next_to_clean);
+
+ erdr->sw_next_to_clean = sw_next_to_clean;
+
+ /* Refill here in case refill threshold wasn't reached */
+ if (likely(cleaned_count)) {
+ ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
+ erdr->pending_fill = ret_count;
+ if (ret_count) {
+ if (net_ratelimit())
+ dev_dbg(&pdev->dev, "Not all buffers was reallocated");
+ }
+
+ edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
+ erdr->sw_next_to_clean);
+ }
+
+ return erdr->pending_fill;
+}
+
+/* edma_delete_rfs_filter()
+ * Remove RFS filter from switch
+ */
+static int edma_delete_rfs_filter(struct edma_adapter *adapter,
+ struct edma_rfs_filter_node *filter_node)
+{
+ int res = -1;
+
+ struct flow_keys *keys = &filter_node->keys;
+
+ if (likely(adapter->set_rfs_rule))
+ res = (*adapter->set_rfs_rule)(adapter->netdev,
+ flow_get_u32_src(keys), flow_get_u32_dst(keys),
+ keys->ports.src, keys->ports.dst,
+ keys->basic.ip_proto, filter_node->rq_id, 0);
+
+ return res;
+}
+
+/* edma_add_rfs_filter()
+ * Add RFS filter to switch
+ */
+static int edma_add_rfs_filter(struct edma_adapter *adapter,
+ struct flow_keys *keys, u16 rq,
+ struct edma_rfs_filter_node *filter_node)
+{
+ int res = -1;
+
+ struct flow_keys *dest_keys = &filter_node->keys;
+
+ memcpy(dest_keys, &filter_node->keys, sizeof(*dest_keys));
+/*
+ dest_keys->control = keys->control;
+ dest_keys->basic = keys->basic;
+ dest_keys->addrs = keys->addrs;
+ dest_keys->ports = keys->ports;
+ dest_keys.ip_proto = keys->ip_proto;
+*/
+ /* Call callback registered by ESS driver */
+ if (likely(adapter->set_rfs_rule))
+ res = (*adapter->set_rfs_rule)(adapter->netdev, flow_get_u32_src(keys),
+ flow_get_u32_dst(keys), keys->ports.src, keys->ports.dst,
+ keys->basic.ip_proto, rq, 1);
+
+ return res;
+}
+
+/* edma_rfs_key_search()
+ * Look for existing RFS entry
+ */
+static struct edma_rfs_filter_node *edma_rfs_key_search(struct hlist_head *h,
+ struct flow_keys *key)
+{
+ struct edma_rfs_filter_node *p;
+
+ hlist_for_each_entry(p, h, node)
+ if (flow_get_u32_src(&p->keys) == flow_get_u32_src(key) &&
+ flow_get_u32_dst(&p->keys) == flow_get_u32_dst(key) &&
+ p->keys.ports.src == key->ports.src &&
+ p->keys.ports.dst == key->ports.dst &&
+ p->keys.basic.ip_proto == key->basic.ip_proto)
+ return p;
+ return NULL;
+}
+
+/* edma_initialise_rfs_flow_table()
+ * Initialise EDMA RFS flow table
+ */
+static void edma_initialise_rfs_flow_table(struct edma_adapter *adapter)
+{
+ int i;
+
+ spin_lock_init(&adapter->rfs.rfs_ftab_lock);
+
+ /* Initialize EDMA flow hash table */
+ for (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++)
+ INIT_HLIST_HEAD(&adapter->rfs.hlist_head[i]);
+
+ adapter->rfs.max_num_filter = EDMA_RFS_FLOW_ENTRIES;
+ adapter->rfs.filter_available = adapter->rfs.max_num_filter;
+ adapter->rfs.hashtoclean = 0;
+
+ /* Add timer to get periodic RFS updates from OS */
+ timer_setup(&adapter->rfs.expire_rfs, edma_flow_may_expire, 0);
+ mod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4);
+}
+
+/* edma_free_rfs_flow_table()
+ * Free EDMA RFS flow table
+ */
+static void edma_free_rfs_flow_table(struct edma_adapter *adapter)
+{
+ int i;
+
+ /* Remove sync timer */
+ del_timer_sync(&adapter->rfs.expire_rfs);
+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
+
+ /* Free EDMA RFS table entries */
+ adapter->rfs.filter_available = 0;
+
+ /* Clean-up EDMA flow hash table */
+ for (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++) {
+ struct hlist_head *hhead;
+ struct hlist_node *tmp;
+ struct edma_rfs_filter_node *filter_node;
+ int res;
+
+ hhead = &adapter->rfs.hlist_head[i];
+ hlist_for_each_entry_safe(filter_node, tmp, hhead, node) {
+ res = edma_delete_rfs_filter(adapter, filter_node);
+ if (res < 0)
+ dev_warn(&adapter->netdev->dev,
+ "EDMA going down but RFS entry %d not allowed to be flushed by Switch",
+ filter_node->flow_id);
+ hlist_del(&filter_node->node);
+ kfree(filter_node);
+ }
+ }
+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
+}
+
+/* edma_tx_unmap_and_free()
+ * clean TX buffer
+ */
+static inline void edma_tx_unmap_and_free(struct platform_device *pdev,
+ struct edma_sw_desc *sw_desc)
+{
+ struct sk_buff *skb = sw_desc->skb;
+
+ if (likely((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD) ||
+ (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAGLIST)))
+ /* unmap_single for skb head area */
+ dma_unmap_single(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_TO_DEVICE);
+ else if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG)
+ /* unmap page for paged fragments */
+ dma_unmap_page(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_TO_DEVICE);
+
+ if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_LAST))
+ dev_kfree_skb_any(skb);
+
+ sw_desc->flags = 0;
+}
+
+/* edma_tx_complete()
+ * Used to clean tx queues and update hardware and consumer index
+ */
+static void edma_tx_complete(struct edma_common_info *edma_cinfo, int queue_id)
+{
+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
+ struct edma_sw_desc *sw_desc;
+ struct platform_device *pdev = edma_cinfo->pdev;
+ int i;
+
+ u16 sw_next_to_clean = etdr->sw_next_to_clean;
+ u16 hw_next_to_clean;
+ u32 data = 0;
+
+ edma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &data);
+ hw_next_to_clean = (data >> EDMA_TPD_CONS_IDX_SHIFT) & EDMA_TPD_CONS_IDX_MASK;
+
+ /* clean the buffer here */
+ while (sw_next_to_clean != hw_next_to_clean) {
+ sw_desc = &etdr->sw_desc[sw_next_to_clean];
+ edma_tx_unmap_and_free(pdev, sw_desc);
+ sw_next_to_clean = (sw_next_to_clean + 1) & (etdr->count - 1);
+ }
+
+ etdr->sw_next_to_clean = sw_next_to_clean;
+
+ /* update the TPD consumer index register */
+ edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(queue_id), sw_next_to_clean);
+
+ /* Wake the queue if queue is stopped and netdev link is up */
+ for (i = 0; i < EDMA_MAX_NETDEV_PER_QUEUE && etdr->nq[i] ; i++) {
+ if (netif_tx_queue_stopped(etdr->nq[i])) {
+ if ((etdr->netdev[i]) && netif_carrier_ok(etdr->netdev[i]))
+ netif_tx_wake_queue(etdr->nq[i]);
+ }
+ }
+}
+
+/* edma_get_tx_buffer()
+ * Get sw_desc corresponding to the TPD
+ */
+static struct edma_sw_desc *edma_get_tx_buffer(struct edma_common_info *edma_cinfo,
+ struct edma_tx_desc *tpd, int queue_id)
+{
+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
+ return &etdr->sw_desc[tpd - (struct edma_tx_desc *)etdr->hw_desc];
+}
+
+/* edma_get_next_tpd()
+ * Return a TPD descriptor for transfer
+ */
+static struct edma_tx_desc *edma_get_next_tpd(struct edma_common_info *edma_cinfo,
+ int queue_id)
+{
+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
+ u16 sw_next_to_fill = etdr->sw_next_to_fill;
+ struct edma_tx_desc *tpd_desc =
+ (&((struct edma_tx_desc *)(etdr->hw_desc))[sw_next_to_fill]);
+
+ etdr->sw_next_to_fill = (etdr->sw_next_to_fill + 1) & (etdr->count - 1);
+
+ return tpd_desc;
+}
+
+/* edma_tpd_available()
+ * Check number of free TPDs
+ */
+static inline u16 edma_tpd_available(struct edma_common_info *edma_cinfo,
+ int queue_id)
+{
+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
+
+ u16 sw_next_to_fill;
+ u16 sw_next_to_clean;
+ u16 count = 0;
+
+ sw_next_to_clean = etdr->sw_next_to_clean;
+ sw_next_to_fill = etdr->sw_next_to_fill;
+
+ if (likely(sw_next_to_clean <= sw_next_to_fill))
+ count = etdr->count;
+
+ return count + sw_next_to_clean - sw_next_to_fill - 1;
+}
+
+/* edma_tx_queue_get()
+ * Get the starting number of the queue
+ */
+static inline int edma_tx_queue_get(struct edma_adapter *adapter,
+ struct sk_buff *skb, int txq_id)
+{
+ /* skb->priority is used as an index to skb priority table
+ * and based on packet priority, correspong queue is assigned.
+ */
+ return adapter->tx_start_offset[txq_id] + edma_skb_priority_offset(skb);
+}
+
+/* edma_tx_update_hw_idx()
+ * update the producer index for the ring transmitted
+ */
+static void edma_tx_update_hw_idx(struct edma_common_info *edma_cinfo,
+ struct sk_buff *skb, int queue_id)
+{
+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
+ u32 tpd_idx_data;
+
+ /* Read and update the producer index */
+ edma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &tpd_idx_data);
+ tpd_idx_data &= ~EDMA_TPD_PROD_IDX_BITS;
+ tpd_idx_data |= (etdr->sw_next_to_fill & EDMA_TPD_PROD_IDX_MASK)
+ << EDMA_TPD_PROD_IDX_SHIFT;
+
+ edma_write_reg(EDMA_REG_TPD_IDX_Q(queue_id), tpd_idx_data);
+}
+
+/* edma_rollback_tx()
+ * Function to retrieve tx resources in case of error
+ */
+static void edma_rollback_tx(struct edma_adapter *adapter,
+ struct edma_tx_desc *start_tpd, int queue_id)
+{
+ struct edma_tx_desc_ring *etdr = adapter->edma_cinfo->tpd_ring[queue_id];
+ struct edma_sw_desc *sw_desc;
+ struct edma_tx_desc *tpd = NULL;
+ u16 start_index, index;
+
+ start_index = start_tpd - (struct edma_tx_desc *)(etdr->hw_desc);
+
+ index = start_index;
+ while (index != etdr->sw_next_to_fill) {
+ tpd = (&((struct edma_tx_desc *)(etdr->hw_desc))[index]);
+ sw_desc = &etdr->sw_desc[index];
+ edma_tx_unmap_and_free(adapter->pdev, sw_desc);
+ memset(tpd, 0, sizeof(struct edma_tx_desc));
+ if (++index == etdr->count)
+ index = 0;
+ }
+ etdr->sw_next_to_fill = start_index;
+}
+
+/* edma_tx_map_and_fill()
+ * gets called from edma_xmit_frame
+ *
+ * This is where the dma of the buffer to be transmitted
+ * gets mapped
+ */
+static int edma_tx_map_and_fill(struct edma_common_info *edma_cinfo,
+ struct edma_adapter *adapter, struct sk_buff *skb, int queue_id,
+ unsigned int flags_transmit, u16 from_cpu, u16 dp_bitmap,
+ bool packet_is_rstp, int nr_frags)
+{
+ struct edma_sw_desc *sw_desc = NULL;
+ struct platform_device *pdev = edma_cinfo->pdev;
+ struct edma_tx_desc *tpd = NULL, *start_tpd = NULL;
+ struct sk_buff *iter_skb;
+ int i = 0;
+ u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0;
+ u16 buf_len, lso_desc_len = 0;
+
+ /* It should either be a nr_frags skb or fraglist skb but not both */
+ BUG_ON(nr_frags && skb_has_frag_list(skb));
+
+ if (skb_is_gso(skb)) {
+ /* TODO: What additional checks need to be performed here */
+ if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
+ lso_word1 |= EDMA_TPD_IPV4_EN;
+ ip_hdr(skb)->check = 0;
+ tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
+ ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
+ } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
+ lso_word1 |= EDMA_TPD_LSO_V2_EN;
+ ipv6_hdr(skb)->payload_len = 0;
+ tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
+ &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
+ } else
+ return -EINVAL;
+
+ lso_word1 |= EDMA_TPD_LSO_EN | ((skb_shinfo(skb)->gso_size & EDMA_TPD_MSS_MASK) << EDMA_TPD_MSS_SHIFT) |
+ (skb_transport_offset(skb) << EDMA_TPD_HDR_SHIFT);
+ } else if (flags_transmit & EDMA_HW_CHECKSUM) {
+ u8 css, cso;
+ cso = skb_checksum_start_offset(skb);
+ css = cso + skb->csum_offset;
+
+ word1 |= (EDMA_TPD_CUSTOM_CSUM_EN);
+ word1 |= (cso >> 1) << EDMA_TPD_HDR_SHIFT;
+ word1 |= ((css >> 1) << EDMA_TPD_CUSTOM_CSUM_SHIFT);
+ }
+
+ if (skb->protocol == htons(ETH_P_PPP_SES))
+ word1 |= EDMA_TPD_PPPOE_EN;
+
+ if (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_FLAG) {
+ switch(skb->vlan_proto) {
+ case htons(ETH_P_8021Q):
+ word3 |= (1 << EDMA_TX_INS_CVLAN);
+ word3 |= skb_vlan_tag_get(skb) << EDMA_TX_CVLAN_TAG_SHIFT;
+ break;
+ case htons(ETH_P_8021AD):
+ word1 |= (1 << EDMA_TX_INS_SVLAN);
+ svlan_tag = skb_vlan_tag_get(skb) << EDMA_TX_SVLAN_TAG_SHIFT;
+ break;
+ default:
+ dev_err(&pdev->dev, "no ctag or stag present\n");
+ goto vlan_tag_error;
+ }
+ } else if (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG) {
+ word3 |= (1 << EDMA_TX_INS_CVLAN);
+ word3 |= (adapter->default_vlan_tag) << EDMA_TX_CVLAN_TAG_SHIFT;
+ }
+
+ if (packet_is_rstp) {
+ word3 |= dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT;
+ word3 |= from_cpu << EDMA_TPD_FROM_CPU_SHIFT;
+ } else {
+ word3 |= adapter->dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT;
+ }
+
+ buf_len = skb_headlen(skb);
+
+ if (lso_word1) {
+ if (lso_word1 & EDMA_TPD_LSO_V2_EN) {
+
+ /* IPv6 LSOv2 descriptor */
+ start_tpd = tpd = edma_get_next_tpd(edma_cinfo, queue_id);
+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_NONE;
+
+ /* LSOv2 descriptor overrides addr field to pass length */
+ tpd->addr = cpu_to_le16(skb->len);
+ tpd->svlan_tag = svlan_tag;
+ tpd->word1 = word1 | lso_word1;
+ tpd->word3 = word3;
+ }
+
+ tpd = edma_get_next_tpd(edma_cinfo, queue_id);
+ if (!start_tpd)
+ start_tpd = tpd;
+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
+
+ /* The last buffer info contain the skb address,
+ * so skb will be freed after unmap
+ */
+ sw_desc->length = lso_desc_len;
+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;
+
+ sw_desc->dma = dma_map_single(&adapter->pdev->dev,
+ skb->data, buf_len, DMA_TO_DEVICE);
+ if (dma_mapping_error(&pdev->dev, sw_desc->dma))
+ goto dma_error;
+
+ tpd->addr = cpu_to_le32(sw_desc->dma);
+ tpd->len = cpu_to_le16(buf_len);
+
+ tpd->svlan_tag = svlan_tag;
+ tpd->word1 = word1 | lso_word1;
+ tpd->word3 = word3;
+
+ /* The last buffer info contain the skb address,
+ * so it will be freed after unmap
+ */
+ sw_desc->length = lso_desc_len;
+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;
+
+ buf_len = 0;
+ }
+
+ if (likely(buf_len)) {
+
+ /* TODO Do not dequeue descriptor if there is a potential error */
+ tpd = edma_get_next_tpd(edma_cinfo, queue_id);
+
+ if (!start_tpd)
+ start_tpd = tpd;
+
+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
+
+ /* The last buffer info contain the skb address,
+ * so it will be free after unmap
+ */
+ sw_desc->length = buf_len;
+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;
+ sw_desc->dma = dma_map_single(&adapter->pdev->dev,
+ skb->data, buf_len, DMA_TO_DEVICE);
+ if (dma_mapping_error(&pdev->dev, sw_desc->dma))
+ goto dma_error;
+
+ tpd->addr = cpu_to_le32(sw_desc->dma);
+ tpd->len = cpu_to_le16(buf_len);
+
+ tpd->svlan_tag = svlan_tag;
+ tpd->word1 = word1 | lso_word1;
+ tpd->word3 = word3;
+ }
+
+ /* Walk through all paged fragments */
+ while (nr_frags--) {
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+ buf_len = skb_frag_size(frag);
+ tpd = edma_get_next_tpd(edma_cinfo, queue_id);
+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
+ sw_desc->length = buf_len;
+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAG;
+
+ sw_desc->dma = skb_frag_dma_map(&pdev->dev, frag, 0, buf_len, DMA_TO_DEVICE);
+
+ if (dma_mapping_error(NULL, sw_desc->dma))
+ goto dma_error;
+
+ tpd->addr = cpu_to_le32(sw_desc->dma);
+ tpd->len = cpu_to_le16(buf_len);
+
+ tpd->svlan_tag = svlan_tag;
+ tpd->word1 = word1 | lso_word1;
+ tpd->word3 = word3;
+ i++;
+ }
+
+ /* Walk through all fraglist skbs */
+ skb_walk_frags(skb, iter_skb) {
+ buf_len = iter_skb->len;
+ tpd = edma_get_next_tpd(edma_cinfo, queue_id);
+ sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
+ sw_desc->length = buf_len;
+ sw_desc->dma = dma_map_single(&adapter->pdev->dev,
+ iter_skb->data, buf_len, DMA_TO_DEVICE);
+
+ if (dma_mapping_error(NULL, sw_desc->dma))
+ goto dma_error;
+
+ tpd->addr = cpu_to_le32(sw_desc->dma);
+ tpd->len = cpu_to_le16(buf_len);
+ tpd->svlan_tag = svlan_tag;
+ tpd->word1 = word1 | lso_word1;
+ tpd->word3 = word3;
+ sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAGLIST;
+ }
+
+ if (tpd)
+ tpd->word1 |= 1 << EDMA_TPD_EOP_SHIFT;
+
+ sw_desc->skb = skb;
+ sw_desc->flags |= EDMA_SW_DESC_FLAG_LAST;
+
+ return 0;
+
+dma_error:
+ edma_rollback_tx(adapter, start_tpd, queue_id);
+ dev_err(&pdev->dev, "TX DMA map failed\n");
+vlan_tag_error:
+ return -ENOMEM;
+}
+
+/* edma_check_link()
+ * check Link status
+ */
+static int edma_check_link(struct edma_adapter *adapter)
+{
+ struct phy_device *phydev = adapter->phydev;
+
+ if (!(adapter->poll_required))
+ return __EDMA_LINKUP;
+
+ if (phydev->link)
+ return __EDMA_LINKUP;
+
+ return __EDMA_LINKDOWN;
+}
+
+/* edma_adjust_link()
+ * check for edma link status
+ */
+void edma_adjust_link(struct net_device *netdev)
+{
+ int status;
+ struct edma_adapter *adapter = netdev_priv(netdev);
+ struct phy_device *phydev = adapter->phydev;
+
+ if (!test_bit(__EDMA_UP, &adapter->state_flags))
+ return;
+
+ status = edma_check_link(adapter);
+
+ if (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) {
+ dev_info(&adapter->pdev->dev, "%s: GMAC Link is up with phy_speed=%d\n", netdev->name, phydev->speed);
+ adapter->link_state = __EDMA_LINKUP;
+ if (adapter->edma_cinfo->is_single_phy) {
+ ess_set_port_status_speed(adapter->edma_cinfo, phydev,
+ ffs(adapter->dp_bitmap) - 1);
+ }
+ netif_carrier_on(netdev);
+ if (netif_running(netdev))
+ netif_tx_wake_all_queues(netdev);
+ } else if (status == __EDMA_LINKDOWN && adapter->link_state == __EDMA_LINKUP) {
+ dev_info(&adapter->pdev->dev, "%s: GMAC Link is down\n", netdev->name);
+ adapter->link_state = __EDMA_LINKDOWN;
+ netif_carrier_off(netdev);
+ netif_tx_stop_all_queues(netdev);
+ }
+}
+
+/* edma_get_stats()
+ * Statistics api used to retreive the tx/rx statistics
+ */
+struct net_device_stats *edma_get_stats(struct net_device *netdev)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+
+ return &adapter->stats;
+}
+
+/* edma_xmit()
+ * Main api to be called by the core for packet transmission
+ */
+netdev_tx_t edma_xmit(struct sk_buff *skb,
+ struct net_device *net_dev)
+{
+ struct edma_adapter *adapter = netdev_priv(net_dev);
+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
+ struct edma_tx_desc_ring *etdr;
+ u16 from_cpu, dp_bitmap, txq_id;
+ int ret, nr_frags = 0, num_tpds_needed = 1, queue_id;
+ unsigned int flags_transmit = 0;
+ bool packet_is_rstp = false;
+ struct netdev_queue *nq = NULL;
+
+ if (skb_shinfo(skb)->nr_frags) {
+ nr_frags = skb_shinfo(skb)->nr_frags;
+ num_tpds_needed += nr_frags;
+ } else if (skb_has_frag_list(skb)) {
+ struct sk_buff *iter_skb;
+
+ skb_walk_frags(skb, iter_skb)
+ num_tpds_needed++;
+ }
+
+ if (num_tpds_needed > EDMA_MAX_SKB_FRAGS) {
+ dev_err(&net_dev->dev,
+ "skb received with fragments %d which is more than %lu",
+ num_tpds_needed, EDMA_MAX_SKB_FRAGS);
+ dev_kfree_skb_any(skb);
+ adapter->stats.tx_errors++;
+ return NETDEV_TX_OK;
+ }
+
+ if (edma_stp_rstp) {
+ u16 ath_hdr, ath_eth_type;
+ u8 mac_addr[EDMA_ETH_HDR_LEN];
+ ath_eth_type = ntohs(*(uint16_t *)&skb->data[12]);
+ if (ath_eth_type == edma_ath_eth_type) {
+ packet_is_rstp = true;
+ ath_hdr = htons(*(uint16_t *)&skb->data[14]);
+ dp_bitmap = ath_hdr & EDMA_TX_ATH_HDR_PORT_BITMAP_MASK;
+ from_cpu = (ath_hdr & EDMA_TX_ATH_HDR_FROM_CPU_MASK) >> EDMA_TX_ATH_HDR_FROM_CPU_SHIFT;
+ memcpy(mac_addr, skb->data, EDMA_ETH_HDR_LEN);
+
+ skb_pull(skb, 4);
+
+ memcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN);
+ }
+ }
+
+ /* this will be one of the 4 TX queues exposed to linux kernel */
+ txq_id = skb_get_queue_mapping(skb);
+ queue_id = edma_tx_queue_get(adapter, skb, txq_id);
+ etdr = edma_cinfo->tpd_ring[queue_id];
+ nq = netdev_get_tx_queue(net_dev, txq_id);
+
+ local_bh_disable();
+ /* Tx is not handled in bottom half context. Hence, we need to protect
+ * Tx from tasks and bottom half
+ */
+
+ if (num_tpds_needed > edma_tpd_available(edma_cinfo, queue_id)) {
+ /* not enough descriptor, just stop queue */
+ netif_tx_stop_queue(nq);
+ local_bh_enable();
+ dev_dbg(&net_dev->dev, "Not enough descriptors available");
+ edma_cinfo->edma_ethstats.tx_desc_error++;
+ return NETDEV_TX_BUSY;
+ }
+
+ /* Check and mark VLAN tag offload */
+ if (!adapter->edma_cinfo->is_single_phy) {
+ if (unlikely(skb_vlan_tag_present(skb)))
+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
+ else if (adapter->default_vlan_tag)
+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
+ }
+
+ /* Check and mark checksum offload */
+ if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
+ flags_transmit |= EDMA_HW_CHECKSUM;
+
+ /* Map and fill descriptor for Tx */
+ ret = edma_tx_map_and_fill(edma_cinfo, adapter, skb, queue_id,
+ flags_transmit, from_cpu, dp_bitmap, packet_is_rstp, nr_frags);
+ if (ret) {
+ dev_kfree_skb_any(skb);
+ adapter->stats.tx_errors++;
+ goto netdev_okay;
+ }
+
+ /* Update SW producer index */
+ edma_tx_update_hw_idx(edma_cinfo, skb, queue_id);
+
+ /* update tx statistics */
+ adapter->stats.tx_packets++;
+ adapter->stats.tx_bytes += skb->len;
+
+netdev_okay:
+ local_bh_enable();
+ return NETDEV_TX_OK;
+}
+
+/*
+ * edma_flow_may_expire()
+ * Timer function called periodically to delete the node
+ */
+void edma_flow_may_expire(struct timer_list *t)
+{
+ struct edma_rfs_flow_table *table = from_timer(table, t, expire_rfs);
+ struct edma_adapter *adapter =
+ container_of(table, typeof(*adapter), rfs);
+ int j;
+
+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
+ for (j = 0; j < EDMA_RFS_EXPIRE_COUNT_PER_CALL; j++) {
+ struct hlist_head *hhead;
+ struct hlist_node *tmp;
+ struct edma_rfs_filter_node *n;
+ bool res;
+
+ hhead = &adapter->rfs.hlist_head[adapter->rfs.hashtoclean++];
+ hlist_for_each_entry_safe(n, tmp, hhead, node) {
+ res = rps_may_expire_flow(adapter->netdev, n->rq_id,
+ n->flow_id, n->filter_id);
+ if (res) {
+ int ret;
+ ret = edma_delete_rfs_filter(adapter, n);
+ if (ret < 0)
+ dev_dbg(&adapter->netdev->dev,
+ "RFS entry %d not allowed to be flushed by Switch",
+ n->flow_id);
+ else {
+ hlist_del(&n->node);
+ kfree(n);
+ adapter->rfs.filter_available++;
+ }
+ }
+ }
+ }
+
+ adapter->rfs.hashtoclean = adapter->rfs.hashtoclean & (EDMA_RFS_FLOW_ENTRIES - 1);
+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
+ mod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4);
+}
+
+/* edma_rx_flow_steer()
+ * Called by core to to steer the flow to CPU
+ */
+int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
+ u16 rxq, u32 flow_id)
+{
+ struct flow_keys keys;
+ struct edma_rfs_filter_node *filter_node;
+ struct edma_adapter *adapter = netdev_priv(dev);
+ u16 hash_tblid;
+ int res;
+
+ if (skb->protocol == htons(ETH_P_IPV6)) {
+ dev_err(&adapter->pdev->dev, "IPv6 not supported\n");
+ res = -EINVAL;
+ goto no_protocol_err;
+ }
+
+ /* Dissect flow parameters
+ * We only support IPv4 + TCP/UDP
+ */
+ res = skb_flow_dissect_flow_keys(skb, &keys, 0);
+ if (!((keys.basic.ip_proto == IPPROTO_TCP) || (keys.basic.ip_proto == IPPROTO_UDP))) {
+ res = -EPROTONOSUPPORT;
+ goto no_protocol_err;
+ }
+
+ /* Check if table entry exists */
+ hash_tblid = skb_get_hash_raw(skb) & EDMA_RFS_FLOW_ENTRIES_MASK;
+
+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
+ filter_node = edma_rfs_key_search(&adapter->rfs.hlist_head[hash_tblid], &keys);
+
+ if (filter_node) {
+ if (rxq == filter_node->rq_id) {
+ res = -EEXIST;
+ goto out;
+ } else {
+ res = edma_delete_rfs_filter(adapter, filter_node);
+ if (res < 0)
+ dev_warn(&adapter->netdev->dev,
+ "Cannot steer flow %d to different queue",
+ filter_node->flow_id);
+ else {
+ adapter->rfs.filter_available++;
+ res = edma_add_rfs_filter(adapter, &keys, rxq, filter_node);
+ if (res < 0) {
+ dev_warn(&adapter->netdev->dev,
+ "Cannot steer flow %d to different queue",
+ filter_node->flow_id);
+ } else {
+ adapter->rfs.filter_available--;
+ filter_node->rq_id = rxq;
+ filter_node->filter_id = res;
+ }
+ }
+ }
+ } else {
+ if (adapter->rfs.filter_available == 0) {
+ res = -EBUSY;
+ goto out;
+ }
+
+ filter_node = kmalloc(sizeof(*filter_node), GFP_ATOMIC);
+ if (!filter_node) {
+ res = -ENOMEM;
+ goto out;
+ }
+
+ res = edma_add_rfs_filter(adapter, &keys, rxq, filter_node);
+ if (res < 0) {
+ kfree(filter_node);
+ goto out;
+ }
+
+ adapter->rfs.filter_available--;
+ filter_node->rq_id = rxq;
+ filter_node->filter_id = res;
+ filter_node->flow_id = flow_id;
+ filter_node->keys = keys;
+ INIT_HLIST_NODE(&filter_node->node);
+ hlist_add_head(&filter_node->node, &adapter->rfs.hlist_head[hash_tblid]);
+ }
+
+out:
+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
+no_protocol_err:
+ return res;
+}
+
+/* edma_register_rfs_filter()
+ * Add RFS filter callback
+ */
+int edma_register_rfs_filter(struct net_device *netdev,
+ set_rfs_filter_callback_t set_filter)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+
+ spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
+
+ if (adapter->set_rfs_rule) {
+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
+ return -1;
+ }
+
+ adapter->set_rfs_rule = set_filter;
+ spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
+
+ return 0;
+}
+
+/* edma_alloc_tx_rings()
+ * Allocate rx rings
+ */
+int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+ int i, err = 0;
+
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
+ err = edma_alloc_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]);
+ if (err) {
+ dev_err(&pdev->dev, "Tx Queue alloc %u failed\n", i);
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+/* edma_free_tx_rings()
+ * Free tx rings
+ */
+void edma_free_tx_rings(struct edma_common_info *edma_cinfo)
+{
+ int i;
+
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++)
+ edma_free_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]);
+}
+
+/* edma_free_tx_resources()
+ * Free buffers associated with tx rings
+ */
+void edma_free_tx_resources(struct edma_common_info *edma_cinfo)
+{
+ struct edma_tx_desc_ring *etdr;
+ struct edma_sw_desc *sw_desc;
+ struct platform_device *pdev = edma_cinfo->pdev;
+ int i, j;
+
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
+ etdr = edma_cinfo->tpd_ring[i];
+ for (j = 0; j < EDMA_TX_RING_SIZE; j++) {
+ sw_desc = &etdr->sw_desc[j];
+ if (sw_desc->flags & (EDMA_SW_DESC_FLAG_SKB_HEAD |
+ EDMA_SW_DESC_FLAG_SKB_FRAG | EDMA_SW_DESC_FLAG_SKB_FRAGLIST))
+ edma_tx_unmap_and_free(pdev, sw_desc);
+ }
+ }
+}
+
+/* edma_alloc_rx_rings()
+ * Allocate rx rings
+ */
+int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo)
+{
+ struct platform_device *pdev = edma_cinfo->pdev;
+ int i, j, err = 0;
+
+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
+ err = edma_alloc_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]);
+ if (err) {
+ dev_err(&pdev->dev, "Rx Queue alloc%u failed\n", i);
+ return err;
+ }
+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+ }
+
+ return 0;
+}
+
+/* edma_free_rx_rings()
+ * free rx rings
+ */
+void edma_free_rx_rings(struct edma_common_info *edma_cinfo)
+{
+ int i, j;
+
+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
+ edma_free_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]);
+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+ }
+}
+
+/* edma_free_queues()
+ * Free the queues allocaated
+ */
+void edma_free_queues(struct edma_common_info *edma_cinfo)
+{
+ int i , j;
+
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
+ if (edma_cinfo->tpd_ring[i])
+ kfree(edma_cinfo->tpd_ring[i]);
+ edma_cinfo->tpd_ring[i] = NULL;
+ }
+
+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
+ if (edma_cinfo->rfd_ring[j])
+ kfree(edma_cinfo->rfd_ring[j]);
+ edma_cinfo->rfd_ring[j] = NULL;
+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+ }
+
+ edma_cinfo->num_rx_queues = 0;
+ edma_cinfo->num_tx_queues = 0;
+
+ return;
+}
+
+/* edma_free_rx_resources()
+ * Free buffers associated with tx rings
+ */
+void edma_free_rx_resources(struct edma_common_info *edma_cinfo)
+{
+ struct edma_rfd_desc_ring *erdr;
+ struct edma_sw_desc *sw_desc;
+ struct platform_device *pdev = edma_cinfo->pdev;
+ int i, j, k;
+
+ for (i = 0, k = 0; i < edma_cinfo->num_rx_queues; i++) {
+ erdr = edma_cinfo->rfd_ring[k];
+ for (j = 0; j < EDMA_RX_RING_SIZE; j++) {
+ sw_desc = &erdr->sw_desc[j];
+ if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD)) {
+ dma_unmap_single(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_FROM_DEVICE);
+ edma_clean_rfd(erdr, j);
+ } else if ((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG)) {
+ dma_unmap_page(&pdev->dev, sw_desc->dma,
+ sw_desc->length, DMA_FROM_DEVICE);
+ edma_clean_rfd(erdr, j);
+ }
+ }
+ k += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+
+ }
+}
+
+/* edma_alloc_queues_tx()
+ * Allocate memory for all rings
+ */
+int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo)
+{
+ int i;
+
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
+ struct edma_tx_desc_ring *etdr;
+ etdr = kzalloc(sizeof(struct edma_tx_desc_ring), GFP_KERNEL);
+ if (!etdr)
+ goto err;
+ etdr->count = edma_cinfo->tx_ring_count;
+ edma_cinfo->tpd_ring[i] = etdr;
+ }
+
+ return 0;
+err:
+ edma_free_queues(edma_cinfo);
+ return -1;
+}
+
+/* edma_alloc_queues_rx()
+ * Allocate memory for all rings
+ */
+int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo)
+{
+ int i, j;
+
+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
+ struct edma_rfd_desc_ring *rfd_ring;
+ rfd_ring = kzalloc(sizeof(struct edma_rfd_desc_ring),
+ GFP_KERNEL);
+ if (!rfd_ring)
+ goto err;
+ rfd_ring->count = edma_cinfo->rx_ring_count;
+ edma_cinfo->rfd_ring[j] = rfd_ring;
+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+ }
+ return 0;
+err:
+ edma_free_queues(edma_cinfo);
+ return -1;
+}
+
+/* edma_clear_irq_status()
+ * Clear interrupt status
+ */
+void edma_clear_irq_status()
+{
+ edma_write_reg(EDMA_REG_RX_ISR, 0xff);
+ edma_write_reg(EDMA_REG_TX_ISR, 0xffff);
+ edma_write_reg(EDMA_REG_MISC_ISR, 0x1fff);
+ edma_write_reg(EDMA_REG_WOL_ISR, 0x1);
+};
+
+/* edma_configure()
+ * Configure skb, edma interrupts and control register.
+ */
+int edma_configure(struct edma_common_info *edma_cinfo)
+{
+ struct edma_hw *hw = &edma_cinfo->hw;
+ u32 intr_modrt_data;
+ u32 intr_ctrl_data = 0;
+ int i, j, ret_count;
+
+ edma_read_reg(EDMA_REG_INTR_CTRL, &intr_ctrl_data);
+ intr_ctrl_data &= ~(1 << EDMA_INTR_SW_IDX_W_TYP_SHIFT);
+ intr_ctrl_data |= hw->intr_sw_idx_w << EDMA_INTR_SW_IDX_W_TYP_SHIFT;
+ edma_write_reg(EDMA_REG_INTR_CTRL, intr_ctrl_data);
+
+ edma_clear_irq_status();
+
+ /* Clear any WOL status */
+ edma_write_reg(EDMA_REG_WOL_CTRL, 0);
+ intr_modrt_data = (EDMA_TX_IMT << EDMA_IRQ_MODRT_TX_TIMER_SHIFT);
+ intr_modrt_data |= (EDMA_RX_IMT << EDMA_IRQ_MODRT_RX_TIMER_SHIFT);
+ edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
+ edma_configure_tx(edma_cinfo);
+ edma_configure_rx(edma_cinfo);
+
+ /* Allocate the RX buffer */
+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
+ struct edma_rfd_desc_ring *ring = edma_cinfo->rfd_ring[j];
+ ret_count = edma_alloc_rx_buf(edma_cinfo, ring, ring->count, j);
+ if (ret_count) {
+ dev_dbg(&edma_cinfo->pdev->dev, "not all rx buffers allocated\n");
+ }
+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+ }
+
+ /* Configure descriptor Ring */
+ edma_init_desc(edma_cinfo);
+ return 0;
+}
+
+/* edma_irq_enable()
+ * Enable default interrupt generation settings
+ */
+void edma_irq_enable(struct edma_common_info *edma_cinfo)
+{
+ struct edma_hw *hw = &edma_cinfo->hw;
+ int i, j;
+
+ edma_write_reg(EDMA_REG_RX_ISR, 0xff);
+ for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(j), hw->rx_intr_mask);
+ j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
+ }
+ edma_write_reg(EDMA_REG_TX_ISR, 0xffff);
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++)
+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), hw->tx_intr_mask);
+}
+
+/* edma_irq_disable()
+ * Disable Interrupt
+ */
+void edma_irq_disable(struct edma_common_info *edma_cinfo)
+{
+ int i;
+
+ for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++)
+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(i), 0x0);
+
+ for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++)
+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), 0x0);
+ edma_write_reg(EDMA_REG_MISC_IMR, 0);
+ edma_write_reg(EDMA_REG_WOL_IMR, 0);
+}
+
+/* edma_free_irqs()
+ * Free All IRQs
+ */
+void edma_free_irqs(struct edma_adapter *adapter)
+{
+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
+ int i, j;
+ int k = ((edma_cinfo->num_rx_queues == 4) ? 1 : 2);
+
+ for (i = 0; i < CONFIG_NR_CPUS; i++) {
+ for (j = edma_cinfo->edma_percpu_info[i].tx_start; j < (edma_cinfo->edma_percpu_info[i].tx_start + 4); j++)
+ free_irq(edma_cinfo->tx_irq[j], &edma_cinfo->edma_percpu_info[i]);
+
+ for (j = edma_cinfo->edma_percpu_info[i].rx_start; j < (edma_cinfo->edma_percpu_info[i].rx_start + k); j++)
+ free_irq(edma_cinfo->rx_irq[j], &edma_cinfo->edma_percpu_info[i]);
+ }
+}
+
+/* edma_enable_rx_ctrl()
+ * Enable RX queue control
+ */
+void edma_enable_rx_ctrl(struct edma_hw *hw)
+{
+ u32 data;
+
+ edma_read_reg(EDMA_REG_RXQ_CTRL, &data);
+ data |= EDMA_RXQ_CTRL_EN;
+ edma_write_reg(EDMA_REG_RXQ_CTRL, data);
+}
+
+
+/* edma_enable_tx_ctrl()
+ * Enable TX queue control
+ */
+void edma_enable_tx_ctrl(struct edma_hw *hw)
+{
+ u32 data;
+
+ edma_read_reg(EDMA_REG_TXQ_CTRL, &data);
+ data |= EDMA_TXQ_CTRL_TXQ_EN;
+ edma_write_reg(EDMA_REG_TXQ_CTRL, data);
+}
+
+/* edma_stop_rx_tx()
+ * Disable RX/TQ Queue control
+ */
+void edma_stop_rx_tx(struct edma_hw *hw)
+{
+ u32 data;
+
+ edma_read_reg(EDMA_REG_RXQ_CTRL, &data);
+ data &= ~EDMA_RXQ_CTRL_EN;
+ edma_write_reg(EDMA_REG_RXQ_CTRL, data);
+ edma_read_reg(EDMA_REG_TXQ_CTRL, &data);
+ data &= ~EDMA_TXQ_CTRL_TXQ_EN;
+ edma_write_reg(EDMA_REG_TXQ_CTRL, data);
+}
+
+/* edma_reset()
+ * Reset the EDMA
+ */
+int edma_reset(struct edma_common_info *edma_cinfo)
+{
+ struct edma_hw *hw = &edma_cinfo->hw;
+
+ edma_irq_disable(edma_cinfo);
+
+ edma_clear_irq_status();
+
+ edma_stop_rx_tx(hw);
+
+ return 0;
+}
+
+/* edma_fill_netdev()
+ * Fill netdev for each etdr
+ */
+int edma_fill_netdev(struct edma_common_info *edma_cinfo, int queue_id,
+ int dev, int txq_id)
+{
+ struct edma_tx_desc_ring *etdr;
+ int i = 0;
+
+ etdr = edma_cinfo->tpd_ring[queue_id];
+
+ while (etdr->netdev[i])
+ i++;
+
+ if (i >= EDMA_MAX_NETDEV_PER_QUEUE)
+ return -1;
+
+ /* Populate the netdev associated with the tpd ring */
+ etdr->netdev[i] = edma_netdev[dev];
+ etdr->nq[i] = netdev_get_tx_queue(edma_netdev[dev], txq_id);
+
+ return 0;
+}
+
+/* edma_set_mac()
+ * Change the Ethernet Address of the NIC
+ */
+int edma_set_mac_addr(struct net_device *netdev, void *p)
+{
+ struct sockaddr *addr = p;
+
+ if (!is_valid_ether_addr(addr->sa_data))
+ return -EINVAL;
+
+ if (netif_running(netdev))
+ return -EBUSY;
+
+ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+ return 0;
+}
+
+/* edma_set_stp_rstp()
+ * set stp/rstp
+ */
+void edma_set_stp_rstp(bool rstp)
+{
+ edma_stp_rstp = rstp;
+}
+
+/* edma_assign_ath_hdr_type()
+ * assign atheros header eth type
+ */
+void edma_assign_ath_hdr_type(int eth_type)
+{
+ edma_ath_eth_type = eth_type & EDMA_ETH_TYPE_MASK;
+}
+
+/* edma_get_default_vlan_tag()
+ * Used by other modules to get the default vlan tag
+ */
+int edma_get_default_vlan_tag(struct net_device *netdev)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+
+ if (adapter->default_vlan_tag)
+ return adapter->default_vlan_tag;
+
+ return 0;
+}
+
+/* edma_open()
+ * gets called when netdevice is up, start the queue.
+ */
+int edma_open(struct net_device *netdev)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+ struct platform_device *pdev = adapter->edma_cinfo->pdev;
+
+ netif_tx_start_all_queues(netdev);
+ edma_initialise_rfs_flow_table(adapter);
+ set_bit(__EDMA_UP, &adapter->state_flags);
+
+ /* if Link polling is enabled, in our case enabled for WAN, then
+ * do a phy start, else always set link as UP
+ */
+ if (adapter->poll_required) {
+ if (!IS_ERR(adapter->phydev)) {
+ phy_start(adapter->phydev);
+ phy_start_aneg(adapter->phydev);
+ adapter->link_state = __EDMA_LINKDOWN;
+ } else {
+ dev_dbg(&pdev->dev, "Invalid PHY device for a link polled interface\n");
+ }
+ } else {
+ adapter->link_state = __EDMA_LINKUP;
+ netif_carrier_on(netdev);
+ }
+
+ return 0;
+}
+
+
+/* edma_close()
+ * gets called when netdevice is down, stops the queue.
+ */
+int edma_close(struct net_device *netdev)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+
+ edma_free_rfs_flow_table(adapter);
+ netif_carrier_off(netdev);
+ netif_tx_stop_all_queues(netdev);
+
+ if (adapter->poll_required) {
+ if (!IS_ERR(adapter->phydev))
+ phy_stop(adapter->phydev);
+ }
+
+ adapter->link_state = __EDMA_LINKDOWN;
+
+ /* Set GMAC state to UP before link state is checked
+ */
+ clear_bit(__EDMA_UP, &adapter->state_flags);
+
+ return 0;
+}
+
+/* edma_poll
+ * polling function that gets called when the napi gets scheduled.
+ *
+ * Main sequence of task performed in this api
+ * is clear irq status -> clear_tx_irq -> clean_rx_irq->
+ * enable interrupts.
+ */
+int edma_poll(struct napi_struct *napi, int budget)
+{
+ struct edma_per_cpu_queues_info *edma_percpu_info = container_of(napi,
+ struct edma_per_cpu_queues_info, napi);
+ struct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo;
+ u32 reg_data;
+ u32 shadow_rx_status, shadow_tx_status;
+ int queue_id;
+ int i, work_done = 0;
+ u16 rx_pending_fill;
+
+ /* Store the Rx/Tx status by ANDing it with
+ * appropriate CPU RX?TX mask
+ */
+ edma_read_reg(EDMA_REG_RX_ISR, &reg_data);
+ edma_percpu_info->rx_status |= reg_data & edma_percpu_info->rx_mask;
+ shadow_rx_status = edma_percpu_info->rx_status;
+ edma_read_reg(EDMA_REG_TX_ISR, &reg_data);
+ edma_percpu_info->tx_status |= reg_data & edma_percpu_info->tx_mask;
+ shadow_tx_status = edma_percpu_info->tx_status;
+
+ /* Every core will have a start, which will be computed
+ * in probe and stored in edma_percpu_info->tx_start variable.
+ * We will shift the status bit by tx_start to obtain
+ * status bits for the core on which the current processing
+ * is happening. Since, there are 4 tx queues per core,
+ * we will run the loop till we get the correct queue to clear.
+ */
+ while (edma_percpu_info->tx_status) {
+ queue_id = ffs(edma_percpu_info->tx_status) - 1;
+ edma_tx_complete(edma_cinfo, queue_id);
+ edma_percpu_info->tx_status &= ~(1 << queue_id);
+ }
+
+ /* Every core will have a start, which will be computed
+ * in probe and stored in edma_percpu_info->tx_start variable.
+ * We will shift the status bit by tx_start to obtain
+ * status bits for the core on which the current processing
+ * is happening. Since, there are 4 tx queues per core, we
+ * will run the loop till we get the correct queue to clear.
+ */
+ while (edma_percpu_info->rx_status) {
+ queue_id = ffs(edma_percpu_info->rx_status) - 1;
+ rx_pending_fill = edma_rx_complete(edma_cinfo, &work_done,
+ budget, queue_id, napi);
+
+ if (likely(work_done < budget)) {
+ if (rx_pending_fill) {
+ /* reschedule poll() to refill rx buffer deficit */
+ work_done = budget;
+ break;
+ }
+ edma_percpu_info->rx_status &= ~(1 << queue_id);
+ } else {
+ break;
+ }
+ }
+
+ /* Clear the status register, to avoid the interrupts to
+ * reoccur.This clearing of interrupt status register is
+ * done here as writing to status register only takes place
+ * once the producer/consumer index has been updated to
+ * reflect that the packet transmission/reception went fine.
+ */
+ edma_write_reg(EDMA_REG_RX_ISR, shadow_rx_status);
+ edma_write_reg(EDMA_REG_TX_ISR, shadow_tx_status);
+
+ /* If budget not fully consumed, exit the polling mode */
+ if (likely(work_done < budget)) {
+ napi_complete(napi);
+
+ /* re-enable the interrupts */
+ for (i = 0; i < edma_cinfo->num_rxq_per_core; i++)
+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x1);
+ for (i = 0; i < edma_cinfo->num_txq_per_core; i++)
+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x1);
+ }
+
+ return work_done;
+}
+
+/* edma interrupt()
+ * interrupt handler
+ */
+irqreturn_t edma_interrupt(int irq, void *dev)
+{
+ struct edma_per_cpu_queues_info *edma_percpu_info = (struct edma_per_cpu_queues_info *) dev;
+ struct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo;
+ int i;
+
+ /* Unmask the TX/RX interrupt register */
+ for (i = 0; i < edma_cinfo->num_rxq_per_core; i++)
+ edma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x0);
+
+ for (i = 0; i < edma_cinfo->num_txq_per_core; i++)
+ edma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x0);
+
+ napi_schedule(&edma_percpu_info->napi);
+
+ return IRQ_HANDLED;
+}
diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.h b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.h
new file mode 100644
index 0000000000..015e5f5026
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma.h
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _EDMA_H_
+#define _EDMA_H_
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/io.h>
+#include <linux/vmalloc.h>
+#include <linux/pagemap.h>
+#include <linux/smp.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/sysctl.h>
+#include <linux/phy.h>
+#include <linux/of_net.h>
+#include <net/checksum.h>
+#include <net/ip6_checksum.h>
+#include <asm-generic/bug.h>
+#include "ess_edma.h"
+
+#define EDMA_CPU_CORES_SUPPORTED 4
+#define EDMA_MAX_PORTID_SUPPORTED 5
+#define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED
+#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
+#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */
+#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
+
+#define EDMA_MAX_RECEIVE_QUEUE 8
+#define EDMA_MAX_TRANSMIT_QUEUE 16
+
+/* WAN/LAN adapter number */
+#define EDMA_WAN 0
+#define EDMA_LAN 1
+
+/* VLAN tag */
+#define EDMA_LAN_DEFAULT_VLAN 1
+#define EDMA_WAN_DEFAULT_VLAN 2
+
+#define EDMA_DEFAULT_GROUP1_VLAN 1
+#define EDMA_DEFAULT_GROUP2_VLAN 2
+#define EDMA_DEFAULT_GROUP3_VLAN 3
+#define EDMA_DEFAULT_GROUP4_VLAN 4
+#define EDMA_DEFAULT_GROUP5_VLAN 5
+
+/* Queues exposed to linux kernel */
+#define EDMA_NETDEV_TX_QUEUE 4
+#define EDMA_NETDEV_RX_QUEUE 4
+
+/* Number of queues per core */
+#define EDMA_NUM_TXQ_PER_CORE 4
+#define EDMA_NUM_RXQ_PER_CORE 2
+
+#define EDMA_TPD_EOP_SHIFT 31
+
+#define EDMA_PORT_ID_SHIFT 12
+#define EDMA_PORT_ID_MASK 0x7
+
+/* tpd word 3 bit 18-28 */
+#define EDMA_TPD_PORT_BITMAP_SHIFT 18
+
+#define EDMA_TPD_FROM_CPU_SHIFT 25
+
+#define EDMA_FROM_CPU_MASK 0x80
+#define EDMA_SKB_PRIORITY_MASK 0x38
+
+/* TX/RX descriptor ring count */
+/* should be a power of 2 */
+#define EDMA_RX_RING_SIZE 128
+#define EDMA_TX_RING_SIZE 128
+
+/* Flags used in paged/non paged mode */
+#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
+#define EDMA_RX_HEAD_BUFF_SIZE 1540
+
+/* MAX frame size supported by switch */
+#define EDMA_MAX_JUMBO_FRAME_SIZE 9216
+
+/* Configurations */
+#define EDMA_INTR_CLEAR_TYPE 0
+#define EDMA_INTR_SW_IDX_W_TYPE 0
+#define EDMA_FIFO_THRESH_TYPE 0
+#define EDMA_RSS_TYPE 0
+#define EDMA_RX_IMT 0x0020
+#define EDMA_TX_IMT 0x0050
+#define EDMA_TPD_BURST 5
+#define EDMA_TXF_BURST 0x100
+#define EDMA_RFD_BURST 8
+#define EDMA_RFD_THR 16
+#define EDMA_RFD_LTHR 0
+
+/* RX/TX per CPU based mask/shift */
+#define EDMA_TX_PER_CPU_MASK 0xF
+#define EDMA_RX_PER_CPU_MASK 0x3
+#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
+#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
+#define EDMA_TX_CPU_START_SHIFT 0x2
+#define EDMA_RX_CPU_START_SHIFT 0x1
+
+/* FLags used in transmit direction */
+#define EDMA_HW_CHECKSUM 0x00000001
+#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
+#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
+
+#define EDMA_SW_DESC_FLAG_LAST 0x1
+#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
+#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
+#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
+#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
+#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
+
+
+#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
+
+/* Ethtool specific list of EDMA supported features */
+#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
+ | SUPPORTED_10baseT_Full \
+ | SUPPORTED_100baseT_Half \
+ | SUPPORTED_100baseT_Full \
+ | SUPPORTED_1000baseT_Full)
+
+/* Recevie side atheros Header */
+#define EDMA_RX_ATH_HDR_VERSION 0x2
+#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
+#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
+#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
+#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
+
+/* Transmit side atheros Header */
+#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
+#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
+#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
+
+#define EDMA_TXQ_START_CORE0 8
+#define EDMA_TXQ_START_CORE1 12
+#define EDMA_TXQ_START_CORE2 0
+#define EDMA_TXQ_START_CORE3 4
+
+#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
+#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
+#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
+#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
+
+#define EDMA_ETH_HDR_LEN 12
+#define EDMA_ETH_TYPE_MASK 0xFFFF
+
+#define EDMA_RX_BUFFER_WRITE 16
+#define EDMA_RFD_AVAIL_THR 80
+
+#define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR
+
+extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,
+ __be16 sport, __be16 dport,
+ uint8_t proto, u16 loadbalance, bool action);
+struct edma_ethtool_statistics {
+ u32 tx_q0_pkt;
+ u32 tx_q1_pkt;
+ u32 tx_q2_pkt;
+ u32 tx_q3_pkt;
+ u32 tx_q4_pkt;
+ u32 tx_q5_pkt;
+ u32 tx_q6_pkt;
+ u32 tx_q7_pkt;
+ u32 tx_q8_pkt;
+ u32 tx_q9_pkt;
+ u32 tx_q10_pkt;
+ u32 tx_q11_pkt;
+ u32 tx_q12_pkt;
+ u32 tx_q13_pkt;
+ u32 tx_q14_pkt;
+ u32 tx_q15_pkt;
+ u32 tx_q0_byte;
+ u32 tx_q1_byte;
+ u32 tx_q2_byte;
+ u32 tx_q3_byte;
+ u32 tx_q4_byte;
+ u32 tx_q5_byte;
+ u32 tx_q6_byte;
+ u32 tx_q7_byte;
+ u32 tx_q8_byte;
+ u32 tx_q9_byte;
+ u32 tx_q10_byte;
+ u32 tx_q11_byte;
+ u32 tx_q12_byte;
+ u32 tx_q13_byte;
+ u32 tx_q14_byte;
+ u32 tx_q15_byte;
+ u32 rx_q0_pkt;
+ u32 rx_q1_pkt;
+ u32 rx_q2_pkt;
+ u32 rx_q3_pkt;
+ u32 rx_q4_pkt;
+ u32 rx_q5_pkt;
+ u32 rx_q6_pkt;
+ u32 rx_q7_pkt;
+ u32 rx_q0_byte;
+ u32 rx_q1_byte;
+ u32 rx_q2_byte;
+ u32 rx_q3_byte;
+ u32 rx_q4_byte;
+ u32 rx_q5_byte;
+ u32 rx_q6_byte;
+ u32 rx_q7_byte;
+ u32 tx_desc_error;
+ u32 rx_alloc_fail_ctr;
+};
+
+struct edma_mdio_data {
+ struct mii_bus *mii_bus;
+ void __iomem *membase;
+ int phy_irq[PHY_MAX_ADDR];
+};
+
+/* EDMA LINK state */
+enum edma_link_state {
+ __EDMA_LINKUP, /* Indicate link is UP */
+ __EDMA_LINKDOWN /* Indicate link is down */
+};
+
+/* EDMA GMAC state */
+enum edma_gmac_state {
+ __EDMA_UP /* use to indicate GMAC is up */
+};
+
+/* edma transmit descriptor */
+struct edma_tx_desc {
+ __le16 len; /* full packet including CRC */
+ __le16 svlan_tag; /* vlan tag */
+ __le32 word1; /* byte 4-7 */
+ __le32 addr; /* address of buffer */
+ __le32 word3; /* byte 12 */
+};
+
+/* edma receive return descriptor */
+struct edma_rx_return_desc {
+ u16 rrd0;
+ u16 rrd1;
+ u16 rrd2;
+ u16 rrd3;
+ u16 rrd4;
+ u16 rrd5;
+ u16 rrd6;
+ u16 rrd7;
+};
+
+/* RFD descriptor */
+struct edma_rx_free_desc {
+ __le32 buffer_addr; /* buffer address */
+};
+
+/* edma hw specific data */
+struct edma_hw {
+ u32 __iomem *hw_addr; /* inner register address */
+ struct edma_adapter *adapter; /* netdevice adapter */
+ u32 rx_intr_mask; /*rx interrupt mask */
+ u32 tx_intr_mask; /* tx interrupt nask */
+ u32 misc_intr_mask; /* misc interrupt mask */
+ u32 wol_intr_mask; /* wake on lan interrupt mask */
+ bool intr_clear_type; /* interrupt clear */
+ bool intr_sw_idx_w; /* interrupt software index */
+ u32 rx_head_buff_size; /* Rx buffer size */
+ u8 rss_type; /* rss protocol type */
+};
+
+/* edma_sw_desc stores software descriptor
+ * SW descriptor has 1:1 map with HW descriptor
+ */
+struct edma_sw_desc {
+ struct sk_buff *skb;
+ dma_addr_t dma; /* dma address */
+ u16 length; /* Tx/Rx buffer length */
+ u32 flags;
+};
+
+/* per core related information */
+struct edma_per_cpu_queues_info {
+ struct napi_struct napi; /* napi associated with the core */
+ u32 tx_mask; /* tx interrupt mask */
+ u32 rx_mask; /* rx interrupt mask */
+ u32 tx_status; /* tx interrupt status */
+ u32 rx_status; /* rx interrupt status */
+ u32 tx_start; /* tx queue start */
+ u32 rx_start; /* rx queue start */
+ struct edma_common_info *edma_cinfo; /* edma common info */
+};
+
+/* edma specific common info */
+struct edma_common_info {
+ struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */
+ struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */
+ struct platform_device *pdev; /* device structure */
+ struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];
+ struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];
+ struct ctl_table_header *edma_ctl_table_hdr;
+ int num_gmac;
+ struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */
+ int num_rx_queues; /* number of rx queue */
+ u32 num_tx_queues; /* number of tx queue */
+ u32 tx_irq[16]; /* number of tx irq */
+ u32 rx_irq[8]; /* number of rx irq */
+ u32 from_cpu; /* from CPU TPD field */
+ u32 num_rxq_per_core; /* Rx queues per core */
+ u32 num_txq_per_core; /* Tx queues per core */
+ u16 tx_ring_count; /* Tx ring count */
+ u16 rx_ring_count; /* Rx ring*/
+ u16 rx_head_buffer_len; /* rx buffer length */
+ u16 rx_page_buffer_len; /* rx buffer length */
+ u32 page_mode; /* Jumbo frame supported flag */
+ u32 fraglist_mode; /* fraglist supported flag */
+ struct edma_hw hw; /* edma hw specific structure */
+ struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
+ spinlock_t stats_lock; /* protect edma stats area for updation */
+ struct timer_list edma_stats_timer;
+ bool is_single_phy;
+ void __iomem *ess_hw_addr;
+ struct clk *ess_clk;
+};
+
+/* transimit packet descriptor (tpd) ring */
+struct edma_tx_desc_ring {
+ struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */
+ struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];
+ /* Array of netdevs associated with the tpd ring */
+ void *hw_desc; /* descriptor ring virtual address */
+ struct edma_sw_desc *sw_desc; /* buffer associated with ring */
+ int netdev_bmp; /* Bitmap for per-ring netdevs */
+ u32 size; /* descriptor ring length in bytes */
+ u16 count; /* number of descriptors in the ring */
+ dma_addr_t dma; /* descriptor ring physical address */
+ u16 sw_next_to_fill; /* next Tx descriptor to fill */
+ u16 sw_next_to_clean; /* next Tx descriptor to clean */
+};
+
+/* receive free descriptor (rfd) ring */
+struct edma_rfd_desc_ring {
+ void *hw_desc; /* descriptor ring virtual address */
+ struct edma_sw_desc *sw_desc; /* buffer associated with ring */
+ u16 size; /* bytes allocated to sw_desc */
+ u16 count; /* number of descriptors in the ring */
+ dma_addr_t dma; /* descriptor ring physical address */
+ u16 sw_next_to_fill; /* next descriptor to fill */
+ u16 sw_next_to_clean; /* next descriptor to clean */
+ u16 pending_fill; /* fill pending from previous iteration */
+};
+
+/* edma_rfs_flter_node - rfs filter node in hash table */
+struct edma_rfs_filter_node {
+ struct flow_keys keys;
+ u32 flow_id; /* flow_id of filter provided by kernel */
+ u16 filter_id; /* filter id of filter returned by adaptor */
+ u16 rq_id; /* desired rq index */
+ struct hlist_node node; /* edma rfs list node */
+};
+
+/* edma_rfs_flow_tbl - rfs flow table */
+struct edma_rfs_flow_table {
+ u16 max_num_filter; /* Maximum number of filters edma supports */
+ u16 hashtoclean; /* hash table index to clean next */
+ int filter_available; /* Number of free filters available */
+ struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];
+ spinlock_t rfs_ftab_lock;
+ struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */
+};
+
+/* EDMA net device structure */
+struct edma_adapter {
+ struct net_device *netdev; /* netdevice */
+ struct platform_device *pdev; /* platform device */
+ struct edma_common_info *edma_cinfo; /* edma common info */
+ struct phy_device *phydev; /* Phy device */
+ struct edma_rfs_flow_table rfs; /* edma rfs flow table */
+ struct net_device_stats stats; /* netdev statistics */
+ set_rfs_filter_callback_t set_rfs_rule;
+ u32 flags;/* status flags */
+ unsigned long state_flags; /* GMAC up/down flags */
+ u32 forced_speed; /* link force speed */
+ u32 forced_duplex; /* link force duplex */
+ u32 link_state; /* phy link state */
+ u32 phy_mdio_addr; /* PHY device address on MII interface */
+ u32 poll_required; /* check if link polling is required */
+ u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
+ u32 default_vlan_tag; /* vlan tag */
+ u32 dp_bitmap;
+ uint8_t phy_id[MII_BUS_ID_SIZE + 3];
+};
+
+int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);
+int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);
+int edma_open(struct net_device *netdev);
+int edma_close(struct net_device *netdev);
+void edma_free_tx_resources(struct edma_common_info *edma_c_info);
+void edma_free_rx_resources(struct edma_common_info *edma_c_info);
+int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);
+int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);
+void edma_free_tx_rings(struct edma_common_info *edma_cinfo);
+void edma_free_rx_rings(struct edma_common_info *edma_cinfo);
+void edma_free_queues(struct edma_common_info *edma_cinfo);
+void edma_irq_disable(struct edma_common_info *edma_cinfo);
+int edma_reset(struct edma_common_info *edma_cinfo);
+int edma_poll(struct napi_struct *napi, int budget);
+netdev_tx_t edma_xmit(struct sk_buff *skb,
+ struct net_device *netdev);
+int edma_configure(struct edma_common_info *edma_cinfo);
+void edma_irq_enable(struct edma_common_info *edma_cinfo);
+void edma_enable_tx_ctrl(struct edma_hw *hw);
+void edma_enable_rx_ctrl(struct edma_hw *hw);
+void edma_stop_rx_tx(struct edma_hw *hw);
+void edma_free_irqs(struct edma_adapter *adapter);
+irqreturn_t edma_interrupt(int irq, void *dev);
+void edma_write_reg(u16 reg_addr, u32 reg_value);
+void edma_read_reg(u16 reg_addr, volatile u32 *reg_value);
+struct net_device_stats *edma_get_stats(struct net_device *netdev);
+int edma_set_mac_addr(struct net_device *netdev, void *p);
+int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
+ u16 rxq, u32 flow_id);
+int edma_register_rfs_filter(struct net_device *netdev,
+ set_rfs_filter_callback_t set_filter);
+void edma_flow_may_expire(struct timer_list *t);
+void edma_set_ethtool_ops(struct net_device *netdev);
+void edma_set_stp_rstp(bool tag);
+void edma_assign_ath_hdr_type(int tag);
+int edma_get_default_vlan_tag(struct net_device *netdev);
+void edma_adjust_link(struct net_device *netdev);
+int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);
+void edma_read_append_stats(struct edma_common_info *edma_cinfo);
+void edma_change_tx_coalesce(int usecs);
+void edma_change_rx_coalesce(int usecs);
+void edma_get_tx_rx_coalesce(u32 *reg_val);
+void edma_clear_irq_status(void);
+void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
+ struct phy_device *phydev, uint8_t port_id);
+#endif /* _EDMA_H_ */
diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
new file mode 100644
index 0000000000..db5eac2f03
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
@@ -0,0 +1,1363 @@
+/*
+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/cpu_rmap.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/timer.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/reset.h>
+#include "edma.h"
+#include "ess_edma.h"
+
+/* Weight round robin and virtual QID mask */
+#define EDMA_WRR_VID_SCTL_MASK 0xffff
+
+/* Weight round robin and virtual QID shift */
+#define EDMA_WRR_VID_SCTL_SHIFT 16
+
+char edma_axi_driver_name[] = "ess_edma";
+static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
+ NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
+
+static u32 edma_hw_addr;
+
+char edma_tx_irq[16][64];
+char edma_rx_irq[8][64];
+struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
+static u16 tx_start[4] = {EDMA_TXQ_START_CORE0, EDMA_TXQ_START_CORE1,
+ EDMA_TXQ_START_CORE2, EDMA_TXQ_START_CORE3};
+static u32 tx_mask[4] = {EDMA_TXQ_IRQ_MASK_CORE0, EDMA_TXQ_IRQ_MASK_CORE1,
+ EDMA_TXQ_IRQ_MASK_CORE2, EDMA_TXQ_IRQ_MASK_CORE3};
+
+static u32 edma_default_ltag __read_mostly = EDMA_LAN_DEFAULT_VLAN;
+static u32 edma_default_wtag __read_mostly = EDMA_WAN_DEFAULT_VLAN;
+static u32 edma_default_group1_vtag __read_mostly = EDMA_DEFAULT_GROUP1_VLAN;
+static u32 edma_default_group2_vtag __read_mostly = EDMA_DEFAULT_GROUP2_VLAN;
+static u32 edma_default_group3_vtag __read_mostly = EDMA_DEFAULT_GROUP3_VLAN;
+static u32 edma_default_group4_vtag __read_mostly = EDMA_DEFAULT_GROUP4_VLAN;
+static u32 edma_default_group5_vtag __read_mostly = EDMA_DEFAULT_GROUP5_VLAN;
+static u32 edma_rss_idt_val = EDMA_RSS_IDT_VALUE;
+static u32 edma_rss_idt_idx;
+
+static int edma_weight_assigned_to_q __read_mostly;
+static int edma_queue_to_virtual_q __read_mostly;
+static bool edma_enable_rstp __read_mostly;
+static int edma_athr_hdr_eth_type __read_mostly;
+
+static int page_mode;
+module_param(page_mode, int, 0);
+MODULE_PARM_DESC(page_mode, "enable page mode");
+
+static int overwrite_mode;
+module_param(overwrite_mode, int, 0);
+MODULE_PARM_DESC(overwrite_mode, "overwrite default page_mode setting");
+
+static int jumbo_mru = EDMA_RX_HEAD_BUFF_SIZE;
+module_param(jumbo_mru, int, 0);
+MODULE_PARM_DESC(jumbo_mru, "enable fraglist support");
+
+static int num_rxq = 4;
+module_param(num_rxq, int, 0);
+MODULE_PARM_DESC(num_rxq, "change the number of rx queues");
+
+void edma_write_reg(u16 reg_addr, u32 reg_value)
+{
+ writel(reg_value, ((void __iomem *)(edma_hw_addr + reg_addr)));
+}
+
+void edma_read_reg(u16 reg_addr, volatile u32 *reg_value)
+{
+ *reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr));
+}
+
+static void ess_write_reg(struct edma_common_info *edma, u16 reg_addr, u32 reg_value)
+{
+ writel(reg_value, ((void __iomem *)
+ ((unsigned long)edma->ess_hw_addr + reg_addr)));
+}
+
+static void ess_read_reg(struct edma_common_info *edma, u16 reg_addr,
+ volatile u32 *reg_value)
+{
+ *reg_value = readl((void __iomem *)
+ ((unsigned long)edma->ess_hw_addr + reg_addr));
+}
+
+static int ess_reset(struct edma_common_info *edma)
+{
+ struct device_node *switch_node = NULL;
+ struct reset_control *ess_rst;
+ u32 regval;
+
+ switch_node = of_find_node_by_name(NULL, "ess-switch");
+ if (!switch_node) {
+ pr_err("switch-node not found\n");
+ return -EINVAL;
+ }
+
+ ess_rst = of_reset_control_get(switch_node, "ess_rst");
+ of_node_put(switch_node);
+
+ if (IS_ERR(ess_rst)) {
+ pr_err("failed to find ess_rst!\n");
+ return -ENOENT;
+ }
+
+ reset_control_assert(ess_rst);
+ msleep(10);
+ reset_control_deassert(ess_rst);
+ msleep(100);
+ reset_control_put(ess_rst);
+
+ /* Enable only port 5 <--> port 0
+ * bits 0:6 bitmap of ports it can fwd to */
+#define SET_PORT_BMP(r,v) \
+ ess_read_reg(edma, r, &regval); \
+ ess_write_reg(edma, r, ((regval & ~0x3F) | v));
+
+ SET_PORT_BMP(ESS_PORT0_LOOKUP_CTRL,0x20);
+ SET_PORT_BMP(ESS_PORT1_LOOKUP_CTRL,0x00);
+ SET_PORT_BMP(ESS_PORT2_LOOKUP_CTRL,0x00);
+ SET_PORT_BMP(ESS_PORT3_LOOKUP_CTRL,0x00);
+ SET_PORT_BMP(ESS_PORT4_LOOKUP_CTRL,0x00);
+ SET_PORT_BMP(ESS_PORT5_LOOKUP_CTRL,0x01);
+ ess_write_reg(edma, ESS_RGMII_CTRL, 0x400);
+ ess_write_reg(edma, ESS_PORT0_STATUS, ESS_PORT_1G_FDX);
+ ess_write_reg(edma, ESS_PORT5_STATUS, ESS_PORT_1G_FDX);
+ ess_write_reg(edma, ESS_PORT0_HEADER_CTRL, 0);
+#undef SET_PORT_BMP
+
+ /* forward multicast and broadcast frames to CPU */
+ ess_write_reg(edma, ESS_FWD_CTRL1,
+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_UC_FLOOD_S) |
+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_MC_FLOOD_S) |
+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_BC_FLOOD_S));
+
+ return 0;
+}
+
+void ess_set_port_status_speed(struct edma_common_info *edma,
+ struct phy_device *phydev, uint8_t port_id)
+{
+ uint16_t reg_off = ESS_PORT0_STATUS + (4 * port_id);
+ uint32_t reg_val = 0;
+
+ ess_read_reg(edma, reg_off, &reg_val);
+
+ /* reset the speed bits [0:1] */
+ reg_val &= ~ESS_PORT_STATUS_SPEED_INV;
+
+ /* set the new speed */
+ switch(phydev->speed) {
+ case SPEED_1000: reg_val |= ESS_PORT_STATUS_SPEED_1000; break;
+ case SPEED_100: reg_val |= ESS_PORT_STATUS_SPEED_100; break;
+ case SPEED_10: reg_val |= ESS_PORT_STATUS_SPEED_10; break;
+ default: reg_val |= ESS_PORT_STATUS_SPEED_INV; break;
+ }
+
+ /* check full/half duplex */
+ if (phydev->duplex) {
+ reg_val |= ESS_PORT_STATUS_DUPLEX_MODE;
+ } else {
+ reg_val &= ~ESS_PORT_STATUS_DUPLEX_MODE;
+ }
+
+ ess_write_reg(edma, reg_off, reg_val);
+}
+
+/* edma_change_tx_coalesce()
+ * change tx interrupt moderation timer
+ */
+void edma_change_tx_coalesce(int usecs)
+{
+ u32 reg_value;
+
+ /* Here, we right shift the value from the user by 1, this is
+ * done because IMT resolution timer is 2usecs. 1 count
+ * of this register corresponds to 2 usecs.
+ */
+ edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, &reg_value);
+ reg_value = ((reg_value & 0xffff) | ((usecs >> 1) << 16));
+ edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value);
+}
+
+/* edma_change_rx_coalesce()
+ * change rx interrupt moderation timer
+ */
+void edma_change_rx_coalesce(int usecs)
+{
+ u32 reg_value;
+
+ /* Here, we right shift the value from the user by 1, this is
+ * done because IMT resolution timer is 2usecs. 1 count
+ * of this register corresponds to 2 usecs.
+ */
+ edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, &reg_value);
+ reg_value = ((reg_value & 0xffff0000) | (usecs >> 1));
+ edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value);
+}
+
+/* edma_get_tx_rx_coalesce()
+ * Get tx/rx interrupt moderation value
+ */
+void edma_get_tx_rx_coalesce(u32 *reg_val)
+{
+ edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_val);
+}
+
+void edma_read_append_stats(struct edma_common_info *edma_cinfo)
+{
+ uint32_t *p;
+ int i;
+ u32 stat;
+
+ spin_lock_bh(&edma_cinfo->stats_lock);
+ p = (uint32_t *)&(edma_cinfo->edma_ethstats);
+
+ for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) {
+ edma_read_reg(EDMA_REG_TX_STAT_PKT_Q(i), &stat);
+ *p += stat;
+ p++;
+ }
+
+ for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) {
+ edma_read_reg(EDMA_REG_TX_STAT_BYTE_Q(i), &stat);
+ *p += stat;
+ p++;
+ }
+
+ for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) {
+ edma_read_reg(EDMA_REG_RX_STAT_PKT_Q(i), &stat);
+ *p += stat;
+ p++;
+ }
+
+ for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) {
+ edma_read_reg(EDMA_REG_RX_STAT_BYTE_Q(i), &stat);
+ *p += stat;
+ p++;
+ }
+
+ spin_unlock_bh(&edma_cinfo->stats_lock);
+}
+
+static void edma_statistics_timer(struct timer_list *t)
+{
+ struct edma_common_info *edma_cinfo =
+ from_timer(edma_cinfo, t, edma_stats_timer);
+
+ edma_read_append_stats(edma_cinfo);
+
+ mod_timer(&edma_cinfo->edma_stats_timer, jiffies + 1*HZ);
+}
+
+static int edma_enable_stp_rstp(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ int ret;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+ if (write)
+ edma_set_stp_rstp(edma_enable_rstp);
+
+ return ret;
+}
+
+static int edma_ath_hdr_eth_type(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ int ret;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+ if (write)
+ edma_assign_ath_hdr_type(edma_athr_hdr_eth_type);
+
+ return ret;
+}
+
+static int edma_change_default_lan_vlan(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ struct edma_adapter *adapter;
+ int ret;
+
+ if (!edma_netdev[1]) {
+ pr_err("Netdevice for default_lan does not exist\n");
+ return -1;
+ }
+
+ adapter = netdev_priv(edma_netdev[1]);
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+ if (write)
+ adapter->default_vlan_tag = edma_default_ltag;
+
+ return ret;
+}
+
+static int edma_change_default_wan_vlan(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ struct edma_adapter *adapter;
+ int ret;
+
+ if (!edma_netdev[0]) {
+ pr_err("Netdevice for default_wan does not exist\n");
+ return -1;
+ }
+
+ adapter = netdev_priv(edma_netdev[0]);
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+ if (write)
+ adapter->default_vlan_tag = edma_default_wtag;
+
+ return ret;
+}
+
+static int edma_change_group1_vtag(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ struct edma_adapter *adapter;
+ struct edma_common_info *edma_cinfo;
+ int ret;
+
+ if (!edma_netdev[0]) {
+ pr_err("Netdevice for Group 1 does not exist\n");
+ return -1;
+ }
+
+ adapter = netdev_priv(edma_netdev[0]);
+ edma_cinfo = adapter->edma_cinfo;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+ if (write)
+ adapter->default_vlan_tag = edma_default_group1_vtag;
+
+ return ret;
+}
+
+static int edma_change_group2_vtag(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ struct edma_adapter *adapter;
+ struct edma_common_info *edma_cinfo;
+ int ret;
+
+ if (!edma_netdev[1]) {
+ pr_err("Netdevice for Group 2 does not exist\n");
+ return -1;
+ }
+
+ adapter = netdev_priv(edma_netdev[1]);
+ edma_cinfo = adapter->edma_cinfo;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+ if (write)
+ adapter->default_vlan_tag = edma_default_group2_vtag;
+
+ return ret;
+}
+
+static int edma_change_group3_vtag(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ struct edma_adapter *adapter;
+ struct edma_common_info *edma_cinfo;
+ int ret;
+
+ if (!edma_netdev[2]) {
+ pr_err("Netdevice for Group 3 does not exist\n");
+ return -1;
+ }
+
+ adapter = netdev_priv(edma_netdev[2]);
+ edma_cinfo = adapter->edma_cinfo;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+ if (write)
+ adapter->default_vlan_tag = edma_default_group3_vtag;
+
+ return ret;
+}
+
+static int edma_change_group4_vtag(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ struct edma_adapter *adapter;
+ struct edma_common_info *edma_cinfo;
+ int ret;
+
+ if (!edma_netdev[3]) {
+ pr_err("Netdevice for Group 4 does not exist\n");
+ return -1;
+ }
+
+ adapter = netdev_priv(edma_netdev[3]);
+ edma_cinfo = adapter->edma_cinfo;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+ if (write)
+ adapter->default_vlan_tag = edma_default_group4_vtag;
+
+ return ret;
+}
+
+static int edma_change_group5_vtag(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ struct edma_adapter *adapter;
+ struct edma_common_info *edma_cinfo;
+ int ret;
+
+ if (!edma_netdev[4]) {
+ pr_err("Netdevice for Group 5 does not exist\n");
+ return -1;
+ }
+
+ adapter = netdev_priv(edma_netdev[4]);
+ edma_cinfo = adapter->edma_cinfo;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+
+ if (write)
+ adapter->default_vlan_tag = edma_default_group5_vtag;
+
+ return ret;
+}
+
+static int edma_set_rss_idt_value(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ int ret;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+ if (write && !ret)
+ edma_write_reg(EDMA_REG_RSS_IDT(edma_rss_idt_idx),
+ edma_rss_idt_val);
+ return ret;
+}
+
+static int edma_set_rss_idt_idx(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ int ret;
+ u32 old_value = edma_rss_idt_idx;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+ if (!write || ret)
+ return ret;
+
+ if (edma_rss_idt_idx >= EDMA_NUM_IDT) {
+ pr_err("Invalid RSS indirection table index %d\n",
+ edma_rss_idt_idx);
+ edma_rss_idt_idx = old_value;
+ return -EINVAL;
+ }
+ return ret;
+}
+
+static int edma_weight_assigned_to_queues(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ int ret, queue_id, weight;
+ u32 reg_data, data, reg_addr;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+ if (write) {
+ queue_id = edma_weight_assigned_to_q & EDMA_WRR_VID_SCTL_MASK;
+ if (queue_id < 0 || queue_id > 15) {
+ pr_err("queue_id not within desired range\n");
+ return -EINVAL;
+ }
+
+ weight = edma_weight_assigned_to_q >> EDMA_WRR_VID_SCTL_SHIFT;
+ if (weight < 0 || weight > 0xF) {
+ pr_err("queue_id not within desired range\n");
+ return -EINVAL;
+ }
+
+ data = weight << EDMA_WRR_SHIFT(queue_id);
+
+ reg_addr = EDMA_REG_WRR_CTRL_Q0_Q3 + (queue_id & ~0x3);
+ edma_read_reg(reg_addr, &reg_data);
+ reg_data &= ~(1 << EDMA_WRR_SHIFT(queue_id));
+ edma_write_reg(reg_addr, data | reg_data);
+ }
+
+ return ret;
+}
+
+static int edma_queue_to_virtual_queue_map(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ int ret, queue_id, virtual_qid;
+ u32 reg_data, data, reg_addr;
+
+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
+ if (write) {
+ queue_id = edma_queue_to_virtual_q & EDMA_WRR_VID_SCTL_MASK;
+ if (queue_id < 0 || queue_id > 15) {
+ pr_err("queue_id not within desired range\n");
+ return -EINVAL;
+ }
+
+ virtual_qid = edma_queue_to_virtual_q >>
+ EDMA_WRR_VID_SCTL_SHIFT;
+ if (virtual_qid < 0 || virtual_qid > 8) {
+ pr_err("queue_id not within desired range\n");
+ return -EINVAL;
+ }
+
+ data = virtual_qid << EDMA_VQ_ID_SHIFT(queue_id);
+
+ reg_addr = EDMA_REG_VQ_CTRL0 + (queue_id & ~0x3);
+ edma_read_reg(reg_addr, &reg_data);
+ reg_data &= ~(1 << EDMA_VQ_ID_SHIFT(queue_id));
+ edma_write_reg(reg_addr, data | reg_data);
+ }
+
+ return ret;
+}
+
+static struct ctl_table edma_table[] = {
+ {
+ .procname = "default_lan_tag",
+ .data = &edma_default_ltag,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_change_default_lan_vlan
+ },
+ {
+ .procname = "default_wan_tag",
+ .data = &edma_default_wtag,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_change_default_wan_vlan
+ },
+ {
+ .procname = "weight_assigned_to_queues",
+ .data = &edma_weight_assigned_to_q,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_weight_assigned_to_queues
+ },
+ {
+ .procname = "queue_to_virtual_queue_map",
+ .data = &edma_queue_to_virtual_q,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_queue_to_virtual_queue_map
+ },
+ {
+ .procname = "enable_stp_rstp",
+ .data = &edma_enable_rstp,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_enable_stp_rstp
+ },
+ {
+ .procname = "athr_hdr_eth_type",
+ .data = &edma_athr_hdr_eth_type,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_ath_hdr_eth_type
+ },
+ {
+ .procname = "default_group1_vlan_tag",
+ .data = &edma_default_group1_vtag,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_change_group1_vtag
+ },
+ {
+ .procname = "default_group2_vlan_tag",
+ .data = &edma_default_group2_vtag,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_change_group2_vtag
+ },
+ {
+ .procname = "default_group3_vlan_tag",
+ .data = &edma_default_group3_vtag,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_change_group3_vtag
+ },
+ {
+ .procname = "default_group4_vlan_tag",
+ .data = &edma_default_group4_vtag,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_change_group4_vtag
+ },
+ {
+ .procname = "default_group5_vlan_tag",
+ .data = &edma_default_group5_vtag,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_change_group5_vtag
+ },
+ {
+ .procname = "edma_rss_idt_value",
+ .data = &edma_rss_idt_val,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_set_rss_idt_value
+ },
+ {
+ .procname = "edma_rss_idt_idx",
+ .data = &edma_rss_idt_idx,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = edma_set_rss_idt_idx
+ },
+ {}
+};
+
+static int ess_parse(struct edma_common_info *edma)
+{
+ struct device_node *switch_node;
+ int ret = -EINVAL;
+
+ switch_node = of_find_node_by_name(NULL, "ess-switch");
+ if (!switch_node) {
+ pr_err("cannot find ess-switch node\n");
+ goto out;
+ }
+
+ edma->ess_hw_addr = of_io_request_and_map(switch_node,
+ 0, KBUILD_MODNAME);
+ if (!edma->ess_hw_addr) {
+ pr_err("%s ioremap fail.", __func__);
+ goto out;
+ }
+
+ edma->ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
+ ret = clk_prepare_enable(edma->ess_clk);
+out:
+ of_node_put(switch_node);
+ return ret;
+}
+
+/* edma_axi_netdev_ops
+ * Describe the operations supported by registered netdevices
+ *
+ * static const struct net_device_ops edma_axi_netdev_ops = {
+ * .ndo_open = edma_open,
+ * .ndo_stop = edma_close,
+ * .ndo_start_xmit = edma_xmit_frame,
+ * .ndo_set_mac_address = edma_set_mac_addr,
+ * }
+ */
+static const struct net_device_ops edma_axi_netdev_ops = {
+ .ndo_open = edma_open,
+ .ndo_stop = edma_close,
+ .ndo_start_xmit = edma_xmit,
+ .ndo_set_mac_address = edma_set_mac_addr,
+#ifdef CONFIG_RFS_ACCEL
+ .ndo_rx_flow_steer = edma_rx_flow_steer,
+ .ndo_register_rfs_filter = edma_register_rfs_filter,
+ .ndo_get_default_vlan_tag = edma_get_default_vlan_tag,
+#endif
+ .ndo_get_stats = edma_get_stats,
+};
+
+/* edma_axi_probe()
+ * Initialise an adapter identified by a platform_device structure.
+ *
+ * The OS initialization, configuring of the adapter private structure,
+ * and a hardware reset occur in the probe.
+ */
+static int edma_axi_probe(struct platform_device *pdev)
+{
+ struct edma_common_info *edma_cinfo;
+ struct edma_hw *hw;
+ struct edma_adapter *adapter[EDMA_MAX_PORTID_SUPPORTED];
+ struct resource *res;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *pnp;
+ struct device_node *mdio_node = NULL;
+ struct platform_device *mdio_plat = NULL;
+ struct mii_bus *miibus = NULL;
+ struct edma_mdio_data *mdio_data = NULL;
+ int i, j, k, err = 0;
+ int portid_bmp;
+ int idx = 0, idx_mac = 0;
+
+ if (CONFIG_NR_CPUS != EDMA_CPU_CORES_SUPPORTED) {
+ dev_err(&pdev->dev, "Invalid CPU Cores\n");
+ return -EINVAL;
+ }
+
+ if ((num_rxq != 4) && (num_rxq != 8)) {
+ dev_err(&pdev->dev, "Invalid RX queue, edma probe failed\n");
+ return -EINVAL;
+ }
+ edma_cinfo = kzalloc(sizeof(struct edma_common_info), GFP_KERNEL);
+ if (!edma_cinfo) {
+ err = -ENOMEM;
+ goto err_alloc;
+ }
+
+ edma_cinfo->pdev = pdev;
+
+ of_property_read_u32(np, "qcom,num_gmac", &edma_cinfo->num_gmac);
+ if (edma_cinfo->num_gmac > EDMA_MAX_PORTID_SUPPORTED) {
+ pr_err("Invalid DTSI Entry for qcom,num_gmac\n");
+ err = -EINVAL;
+ goto err_cinfo;
+ }
+
+ /* Initialize the netdev array before allocation
+ * to avoid double free
+ */
+ for (i = 0 ; i < edma_cinfo->num_gmac ; i++)
+ edma_netdev[i] = NULL;
+
+ for (i = 0 ; i < edma_cinfo->num_gmac ; i++) {
+ edma_netdev[i] = alloc_etherdev_mqs(sizeof(struct edma_adapter),
+ EDMA_NETDEV_TX_QUEUE, EDMA_NETDEV_RX_QUEUE);
+
+ if (!edma_netdev[i]) {
+ dev_err(&pdev->dev,
+ "net device alloc fails for index=%d\n", i);
+ err = -ENODEV;
+ goto err_ioremap;
+ }
+
+ SET_NETDEV_DEV(edma_netdev[i], &pdev->dev);
+ platform_set_drvdata(pdev, edma_netdev[i]);
+ edma_cinfo->netdev[i] = edma_netdev[i];
+ }
+
+ /* Fill ring details */
+ edma_cinfo->num_tx_queues = EDMA_MAX_TRANSMIT_QUEUE;
+ edma_cinfo->num_txq_per_core = (EDMA_MAX_TRANSMIT_QUEUE / 4);
+ edma_cinfo->tx_ring_count = EDMA_TX_RING_SIZE;
+
+ /* Update num rx queues based on module parameter */
+ edma_cinfo->num_rx_queues = num_rxq;
+ edma_cinfo->num_rxq_per_core = ((num_rxq == 4) ? 1 : 2);
+
+ edma_cinfo->rx_ring_count = EDMA_RX_RING_SIZE;
+
+ hw = &edma_cinfo->hw;
+
+ /* Fill HW defaults */
+ hw->tx_intr_mask = EDMA_TX_IMR_NORMAL_MASK;
+ hw->rx_intr_mask = EDMA_RX_IMR_NORMAL_MASK;
+
+ of_property_read_u32(np, "qcom,page-mode", &edma_cinfo->page_mode);
+ of_property_read_u32(np, "qcom,rx_head_buf_size",
+ &hw->rx_head_buff_size);
+
+ if (overwrite_mode) {
+ dev_info(&pdev->dev, "page mode overwritten");
+ edma_cinfo->page_mode = page_mode;
+ }
+
+ if (jumbo_mru)
+ edma_cinfo->fraglist_mode = 1;
+
+ if (edma_cinfo->page_mode)
+ hw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE_JUMBO;
+ else if (edma_cinfo->fraglist_mode)
+ hw->rx_head_buff_size = jumbo_mru;
+ else if (!hw->rx_head_buff_size)
+ hw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE;
+
+ hw->misc_intr_mask = 0;
+ hw->wol_intr_mask = 0;
+
+ hw->intr_clear_type = EDMA_INTR_CLEAR_TYPE;
+ hw->intr_sw_idx_w = EDMA_INTR_SW_IDX_W_TYPE;
+
+ /* configure RSS type to the different protocol that can be
+ * supported
+ */
+ hw->rss_type = EDMA_RSS_TYPE_IPV4TCP | EDMA_RSS_TYPE_IPV6_TCP |
+ EDMA_RSS_TYPE_IPV4_UDP | EDMA_RSS_TYPE_IPV6UDP |
+ EDMA_RSS_TYPE_IPV4 | EDMA_RSS_TYPE_IPV6;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ edma_cinfo->hw.hw_addr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(edma_cinfo->hw.hw_addr)) {
+ err = PTR_ERR(edma_cinfo->hw.hw_addr);
+ goto err_ioremap;
+ }
+
+ edma_hw_addr = (u32)edma_cinfo->hw.hw_addr;
+
+ /* Parse tx queue interrupt number from device tree */
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++)
+ edma_cinfo->tx_irq[i] = platform_get_irq(pdev, i);
+
+ /* Parse rx queue interrupt number from device tree
+ * Here we are setting j to point to the point where we
+ * left tx interrupt parsing(i.e 16) and run run the loop
+ * from 0 to 7 to parse rx interrupt number.
+ */
+ for (i = 0, j = edma_cinfo->num_tx_queues, k = 0;
+ i < edma_cinfo->num_rx_queues; i++) {
+ edma_cinfo->rx_irq[k] = platform_get_irq(pdev, j);
+ k += ((num_rxq == 4) ? 2 : 1);
+ j += ((num_rxq == 4) ? 2 : 1);
+ }
+
+ edma_cinfo->rx_head_buffer_len = edma_cinfo->hw.rx_head_buff_size;
+ edma_cinfo->rx_page_buffer_len = PAGE_SIZE;
+
+ err = edma_alloc_queues_tx(edma_cinfo);
+ if (err) {
+ dev_err(&pdev->dev, "Allocation of TX queue failed\n");
+ goto err_tx_qinit;
+ }
+
+ err = edma_alloc_queues_rx(edma_cinfo);
+ if (err) {
+ dev_err(&pdev->dev, "Allocation of RX queue failed\n");
+ goto err_rx_qinit;
+ }
+
+ err = edma_alloc_tx_rings(edma_cinfo);
+ if (err) {
+ dev_err(&pdev->dev, "Allocation of TX resources failed\n");
+ goto err_tx_rinit;
+ }
+
+ err = edma_alloc_rx_rings(edma_cinfo);
+ if (err) {
+ dev_err(&pdev->dev, "Allocation of RX resources failed\n");
+ goto err_rx_rinit;
+ }
+
+ /* Initialize netdev and netdev bitmap for transmit descriptor rings */
+ for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
+ struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[i];
+ int j;
+
+ etdr->netdev_bmp = 0;
+ for (j = 0; j < EDMA_MAX_NETDEV_PER_QUEUE; j++) {
+ etdr->netdev[j] = NULL;
+ etdr->nq[j] = NULL;
+ }
+ }
+
+ if (of_property_read_bool(np, "qcom,mdio_supported")) {
+ mdio_node = of_find_compatible_node(NULL, NULL,
+ "qcom,ipq4019-mdio");
+ if (!mdio_node) {
+ dev_err(&pdev->dev, "cannot find mdio node by phandle");
+ err = -EIO;
+ goto err_mdiobus_init_fail;
+ }
+
+ mdio_plat = of_find_device_by_node(mdio_node);
+ if (!mdio_plat) {
+ dev_err(&pdev->dev,
+ "cannot find platform device from mdio node");
+ of_node_put(mdio_node);
+ err = -EIO;
+ goto err_mdiobus_init_fail;
+ }
+
+ mdio_data = dev_get_drvdata(&mdio_plat->dev);
+ if (!mdio_data) {
+ dev_err(&pdev->dev,
+ "cannot get mii bus reference from device data");
+ of_node_put(mdio_node);
+ err = -EIO;
+ goto err_mdiobus_init_fail;
+ }
+
+ miibus = mdio_data->mii_bus;
+ }
+
+ if (of_property_read_bool(np, "qcom,single-phy") &&
+ edma_cinfo->num_gmac == 1) {
+ err = ess_parse(edma_cinfo);
+ if (!err)
+ err = ess_reset(edma_cinfo);
+ if (err)
+ goto err_single_phy_init;
+ else
+ edma_cinfo->is_single_phy = true;
+ }
+
+ for_each_available_child_of_node(np, pnp) {
+ const char *mac_addr;
+
+ /* this check is needed if parent and daughter dts have
+ * different number of gmac nodes
+ */
+ if (idx_mac == edma_cinfo->num_gmac) {
+ of_node_put(np);
+ break;
+ }
+
+ mac_addr = of_get_mac_address(pnp);
+ if (mac_addr)
+ memcpy(edma_netdev[idx_mac]->dev_addr, mac_addr, ETH_ALEN);
+
+ idx_mac++;
+ }
+
+ /* Populate the adapter structure register the netdevice */
+ for (i = 0; i < edma_cinfo->num_gmac; i++) {
+ int k, m;
+
+ adapter[i] = netdev_priv(edma_netdev[i]);
+ adapter[i]->netdev = edma_netdev[i];
+ adapter[i]->pdev = pdev;
+ for (j = 0; j < CONFIG_NR_CPUS; j++) {
+ m = i % 2;
+ adapter[i]->tx_start_offset[j] =
+ ((j << EDMA_TX_CPU_START_SHIFT) + (m << 1));
+ /* Share the queues with available net-devices.
+ * For instance , with 5 net-devices
+ * eth0/eth2/eth4 will share q0,q1,q4,q5,q8,q9,q12,q13
+ * and eth1/eth3 will get the remaining.
+ */
+ for (k = adapter[i]->tx_start_offset[j]; k <
+ (adapter[i]->tx_start_offset[j] + 2); k++) {
+ if (edma_fill_netdev(edma_cinfo, k, i, j)) {
+ pr_err("Netdev overflow Error\n");
+ goto err_register;
+ }
+ }
+ }
+
+ adapter[i]->edma_cinfo = edma_cinfo;
+ edma_netdev[i]->netdev_ops = &edma_axi_netdev_ops;
+ edma_netdev[i]->max_mtu = 9000;
+ edma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM
+ | NETIF_F_HW_VLAN_CTAG_TX
+ | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG |
+ NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GRO;
+ edma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
+ NETIF_F_HW_VLAN_CTAG_RX
+ | NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
+ NETIF_F_GRO;
+ edma_netdev[i]->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG |
+ NETIF_F_TSO | NETIF_F_TSO6 |
+ NETIF_F_GRO;
+ edma_netdev[i]->wanted_features = NETIF_F_HW_CSUM | NETIF_F_SG |
+ NETIF_F_TSO | NETIF_F_TSO6 |
+ NETIF_F_GRO;
+
+#ifdef CONFIG_RFS_ACCEL
+ edma_netdev[i]->features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
+ edma_netdev[i]->hw_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
+ edma_netdev[i]->vlan_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
+ edma_netdev[i]->wanted_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
+#endif
+ edma_set_ethtool_ops(edma_netdev[i]);
+
+ /* This just fill in some default MAC address
+ */
+ if (!is_valid_ether_addr(edma_netdev[i]->dev_addr)) {
+ random_ether_addr(edma_netdev[i]->dev_addr);
+ pr_info("EDMA using MAC@ - using");
+ pr_info("%02x:%02x:%02x:%02x:%02x:%02x\n",
+ *(edma_netdev[i]->dev_addr),
+ *(edma_netdev[i]->dev_addr + 1),
+ *(edma_netdev[i]->dev_addr + 2),
+ *(edma_netdev[i]->dev_addr + 3),
+ *(edma_netdev[i]->dev_addr + 4),
+ *(edma_netdev[i]->dev_addr + 5));
+ }
+
+ err = register_netdev(edma_netdev[i]);
+ if (err)
+ goto err_register;
+
+ /* carrier off reporting is important to
+ * ethtool even BEFORE open
+ */
+ netif_carrier_off(edma_netdev[i]);
+
+ /* Allocate reverse irq cpu mapping structure for
+ * receive queues
+ */
+#ifdef CONFIG_RFS_ACCEL
+ edma_netdev[i]->rx_cpu_rmap =
+ alloc_irq_cpu_rmap(EDMA_NETDEV_RX_QUEUE);
+ if (!edma_netdev[i]->rx_cpu_rmap) {
+ err = -ENOMEM;
+ goto err_rmap_alloc_fail;
+ }
+#endif
+ }
+
+ for (i = 0; i < EDMA_MAX_PORTID_BITMAP_INDEX; i++)
+ edma_cinfo->portid_netdev_lookup_tbl[i] = NULL;
+
+ for_each_available_child_of_node(np, pnp) {
+ const uint32_t *vlan_tag = NULL;
+ int len;
+
+ /* this check is needed if parent and daughter dts have
+ * different number of gmac nodes
+ */
+ if (idx == edma_cinfo->num_gmac)
+ break;
+
+ /* Populate port-id to netdev lookup table */
+ vlan_tag = of_get_property(pnp, "vlan_tag", &len);
+ if (!vlan_tag) {
+ pr_err("Vlan tag parsing Failed.\n");
+ goto err_rmap_alloc_fail;
+ }
+
+ adapter[idx]->default_vlan_tag = of_read_number(vlan_tag, 1);
+ vlan_tag++;
+ portid_bmp = of_read_number(vlan_tag, 1);
+ adapter[idx]->dp_bitmap = portid_bmp;
+
+ portid_bmp = portid_bmp >> 1; /* We ignore CPU Port bit 0 */
+ while (portid_bmp) {
+ int port_bit = ffs(portid_bmp);
+
+ if (port_bit > EDMA_MAX_PORTID_SUPPORTED)
+ goto err_rmap_alloc_fail;
+ edma_cinfo->portid_netdev_lookup_tbl[port_bit] =
+ edma_netdev[idx];
+ portid_bmp &= ~(1 << (port_bit - 1));
+ }
+
+ if (!of_property_read_u32(pnp, "qcom,poll_required",
+ &adapter[idx]->poll_required)) {
+ if (adapter[idx]->poll_required) {
+ of_property_read_u32(pnp, "qcom,phy_mdio_addr",
+ &adapter[idx]->phy_mdio_addr);
+ of_property_read_u32(pnp, "qcom,forced_speed",
+ &adapter[idx]->forced_speed);
+ of_property_read_u32(pnp, "qcom,forced_duplex",
+ &adapter[idx]->forced_duplex);
+
+ /* create a phyid using MDIO bus id
+ * and MDIO bus address
+ */
+ snprintf(adapter[idx]->phy_id,
+ MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
+ miibus->id,
+ adapter[idx]->phy_mdio_addr);
+ }
+ } else {
+ adapter[idx]->poll_required = 0;
+ adapter[idx]->forced_speed = SPEED_1000;
+ adapter[idx]->forced_duplex = DUPLEX_FULL;
+ }
+
+ idx++;
+ }
+
+ edma_cinfo->edma_ctl_table_hdr = register_net_sysctl(&init_net,
+ "net/edma",
+ edma_table);
+ if (!edma_cinfo->edma_ctl_table_hdr) {
+ dev_err(&pdev->dev, "edma sysctl table hdr not registered\n");
+ goto err_unregister_sysctl_tbl;
+ }
+
+ /* Disable all 16 Tx and 8 rx irqs */
+ edma_irq_disable(edma_cinfo);
+
+ err = edma_reset(edma_cinfo);
+ if (err) {
+ err = -EIO;
+ goto err_reset;
+ }
+
+ /* populate per_core_info, do a napi_Add, request 16 TX irqs,
+ * 8 RX irqs, do a napi enable
+ */
+ for (i = 0; i < CONFIG_NR_CPUS; i++) {
+ u8 rx_start;
+
+ edma_cinfo->edma_percpu_info[i].napi.state = 0;
+
+ netif_napi_add(edma_netdev[0],
+ &edma_cinfo->edma_percpu_info[i].napi,
+ edma_poll, 64);
+ napi_enable(&edma_cinfo->edma_percpu_info[i].napi);
+ edma_cinfo->edma_percpu_info[i].tx_mask = tx_mask[i];
+ edma_cinfo->edma_percpu_info[i].rx_mask = EDMA_RX_PER_CPU_MASK
+ << (i << EDMA_RX_PER_CPU_MASK_SHIFT);
+ edma_cinfo->edma_percpu_info[i].tx_start = tx_start[i];
+ edma_cinfo->edma_percpu_info[i].rx_start =
+ i << EDMA_RX_CPU_START_SHIFT;
+ rx_start = i << EDMA_RX_CPU_START_SHIFT;
+ edma_cinfo->edma_percpu_info[i].tx_status = 0;
+ edma_cinfo->edma_percpu_info[i].rx_status = 0;
+ edma_cinfo->edma_percpu_info[i].edma_cinfo = edma_cinfo;
+
+ /* Request irq per core */
+ for (j = edma_cinfo->edma_percpu_info[i].tx_start;
+ j < tx_start[i] + 4; j++) {
+ sprintf(&edma_tx_irq[j][0], "edma_eth_tx%d", j);
+ err = request_irq(edma_cinfo->tx_irq[j],
+ edma_interrupt,
+ 0,
+ &edma_tx_irq[j][0],
+ &edma_cinfo->edma_percpu_info[i]);
+ if (err)
+ goto err_reset;
+ }
+
+ for (j = edma_cinfo->edma_percpu_info[i].rx_start;
+ j < (rx_start +
+ ((edma_cinfo->num_rx_queues == 4) ? 1 : 2));
+ j++) {
+ sprintf(&edma_rx_irq[j][0], "edma_eth_rx%d", j);
+ err = request_irq(edma_cinfo->rx_irq[j],
+ edma_interrupt,
+ 0,
+ &edma_rx_irq[j][0],
+ &edma_cinfo->edma_percpu_info[i]);
+ if (err)
+ goto err_reset;
+ }
+
+#ifdef CONFIG_RFS_ACCEL
+ for (j = edma_cinfo->edma_percpu_info[i].rx_start;
+ j < rx_start + 2; j += 2) {
+ err = irq_cpu_rmap_add(edma_netdev[0]->rx_cpu_rmap,
+ edma_cinfo->rx_irq[j]);
+ if (err)
+ goto err_rmap_add_fail;
+ }
+#endif
+ }
+
+ /* Used to clear interrupt status, allocate rx buffer,
+ * configure edma descriptors registers
+ */
+ err = edma_configure(edma_cinfo);
+ if (err) {
+ err = -EIO;
+ goto err_configure;
+ }
+
+ /* Configure RSS indirection table.
+ * 128 hash will be configured in the following
+ * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively
+ * and so on
+ */
+ for (i = 0; i < EDMA_NUM_IDT; i++)
+ edma_write_reg(EDMA_REG_RSS_IDT(i), EDMA_RSS_IDT_VALUE);
+
+ /* Configure load balance mapping table.
+ * 4 table entry will be configured according to the
+ * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4}
+ * respectively.
+ */
+ edma_write_reg(EDMA_REG_LB_RING, EDMA_LB_REG_VALUE);
+
+ /* Configure Virtual queue for Tx rings
+ * User can also change this value runtime through
+ * a sysctl
+ */
+ edma_write_reg(EDMA_REG_VQ_CTRL0, EDMA_VQ_REG_VALUE);
+ edma_write_reg(EDMA_REG_VQ_CTRL1, EDMA_VQ_REG_VALUE);
+
+ /* Configure Max AXI Burst write size to 128 bytes*/
+ edma_write_reg(EDMA_REG_AXIW_CTRL_MAXWRSIZE,
+ EDMA_AXIW_MAXWRSIZE_VALUE);
+
+ /* Enable All 16 tx and 8 rx irq mask */
+ edma_irq_enable(edma_cinfo);
+ edma_enable_tx_ctrl(&edma_cinfo->hw);
+ edma_enable_rx_ctrl(&edma_cinfo->hw);
+
+ for (i = 0; i < edma_cinfo->num_gmac; i++) {
+ if (adapter[i]->poll_required) {
+ int phy_mode = of_get_phy_mode(np);
+
+ if (phy_mode < 0)
+ phy_mode = PHY_INTERFACE_MODE_SGMII;
+ adapter[i]->phydev =
+ phy_connect(edma_netdev[i],
+ (const char *)adapter[i]->phy_id,
+ &edma_adjust_link,
+ phy_mode);
+ if (IS_ERR(adapter[i]->phydev)) {
+ dev_dbg(&pdev->dev, "PHY attach FAIL");
+ err = -EIO;
+ goto edma_phy_attach_fail;
+ } else {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ adapter[i]->phydev->advertising);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ adapter[i]->phydev->advertising);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ adapter[i]->phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ adapter[i]->phydev->supported);
+ }
+ } else {
+ adapter[i]->phydev = NULL;
+ }
+ }
+
+ spin_lock_init(&edma_cinfo->stats_lock);
+
+ timer_setup(&edma_cinfo->edma_stats_timer, edma_statistics_timer, 0);
+ mod_timer(&edma_cinfo->edma_stats_timer, jiffies + 1*HZ);
+
+ return 0;
+
+edma_phy_attach_fail:
+ miibus = NULL;
+err_configure:
+#ifdef CONFIG_RFS_ACCEL
+ for (i = 0; i < edma_cinfo->num_gmac; i++) {
+ free_irq_cpu_rmap(adapter[i]->netdev->rx_cpu_rmap);
+ adapter[i]->netdev->rx_cpu_rmap = NULL;
+ }
+#endif
+err_rmap_add_fail:
+ edma_free_irqs(adapter[0]);
+ for (i = 0; i < CONFIG_NR_CPUS; i++)
+ napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
+err_reset:
+err_unregister_sysctl_tbl:
+err_rmap_alloc_fail:
+ for (i = 0; i < edma_cinfo->num_gmac; i++)
+ unregister_netdev(edma_netdev[i]);
+err_register:
+err_single_phy_init:
+ iounmap(edma_cinfo->ess_hw_addr);
+ clk_disable_unprepare(edma_cinfo->ess_clk);
+err_mdiobus_init_fail:
+ edma_free_rx_rings(edma_cinfo);
+err_rx_rinit:
+ edma_free_tx_rings(edma_cinfo);
+err_tx_rinit:
+ edma_free_queues(edma_cinfo);
+err_rx_qinit:
+err_tx_qinit:
+ iounmap(edma_cinfo->hw.hw_addr);
+err_ioremap:
+ for (i = 0; i < edma_cinfo->num_gmac; i++) {
+ if (edma_netdev[i])
+ free_netdev(edma_netdev[i]);
+ }
+err_cinfo:
+ kfree(edma_cinfo);
+err_alloc:
+ return err;
+}
+
+/* edma_axi_remove()
+ * Device Removal Routine
+ *
+ * edma_axi_remove is called by the platform subsystem to alert the driver
+ * that it should release a platform device.
+ */
+static int edma_axi_remove(struct platform_device *pdev)
+{
+ struct edma_adapter *adapter = netdev_priv(edma_netdev[0]);
+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
+ struct edma_hw *hw = &edma_cinfo->hw;
+ int i;
+
+ for (i = 0; i < edma_cinfo->num_gmac; i++)
+ unregister_netdev(edma_netdev[i]);
+
+ edma_stop_rx_tx(hw);
+ for (i = 0; i < CONFIG_NR_CPUS; i++)
+ napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
+
+ edma_irq_disable(edma_cinfo);
+ edma_write_reg(EDMA_REG_RX_ISR, 0xff);
+ edma_write_reg(EDMA_REG_TX_ISR, 0xffff);
+#ifdef CONFIG_RFS_ACCEL
+ for (i = 0; i < edma_cinfo->num_gmac; i++) {
+ free_irq_cpu_rmap(edma_netdev[i]->rx_cpu_rmap);
+ edma_netdev[i]->rx_cpu_rmap = NULL;
+ }
+#endif
+
+ for (i = 0; i < edma_cinfo->num_gmac; i++) {
+ struct edma_adapter *adapter = netdev_priv(edma_netdev[i]);
+
+ if (adapter->phydev)
+ phy_disconnect(adapter->phydev);
+ }
+
+ del_timer_sync(&edma_cinfo->edma_stats_timer);
+ edma_free_irqs(adapter);
+ unregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr);
+ iounmap(edma_cinfo->ess_hw_addr);
+ clk_disable_unprepare(edma_cinfo->ess_clk);
+ edma_free_tx_resources(edma_cinfo);
+ edma_free_rx_resources(edma_cinfo);
+ edma_free_tx_rings(edma_cinfo);
+ edma_free_rx_rings(edma_cinfo);
+ edma_free_queues(edma_cinfo);
+ for (i = 0; i < edma_cinfo->num_gmac; i++)
+ free_netdev(edma_netdev[i]);
+
+ kfree(edma_cinfo);
+
+ return 0;
+}
+
+static const struct of_device_id edma_of_mtable[] = {
+ {.compatible = "qcom,ess-edma" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, edma_of_mtable);
+
+static struct platform_driver edma_axi_driver = {
+ .driver = {
+ .name = edma_axi_driver_name,
+ .of_match_table = edma_of_mtable,
+ },
+ .probe = edma_axi_probe,
+ .remove = edma_axi_remove,
+};
+
+module_platform_driver(edma_axi_driver);
+
+MODULE_AUTHOR("Qualcomm Atheros Inc");
+MODULE_DESCRIPTION("QCA ESS EDMA driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c
new file mode 100644
index 0000000000..8f6e3833b6
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/ethtool.h>
+#include <linux/netdevice.h>
+#include <linux/string.h>
+#include "edma.h"
+
+struct edma_ethtool_stats {
+ uint8_t stat_string[ETH_GSTRING_LEN];
+ uint32_t stat_offset;
+};
+
+#define EDMA_STAT(m) offsetof(struct edma_ethtool_statistics, m)
+#define DRVINFO_LEN 32
+
+/* Array of strings describing statistics
+ */
+static const struct edma_ethtool_stats edma_gstrings_stats[] = {
+ {"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)},
+ {"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)},
+ {"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)},
+ {"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)},
+ {"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)},
+ {"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)},
+ {"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)},
+ {"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)},
+ {"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)},
+ {"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)},
+ {"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)},
+ {"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)},
+ {"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)},
+ {"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)},
+ {"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)},
+ {"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)},
+ {"tx_q0_byte", EDMA_STAT(tx_q0_byte)},
+ {"tx_q1_byte", EDMA_STAT(tx_q1_byte)},
+ {"tx_q2_byte", EDMA_STAT(tx_q2_byte)},
+ {"tx_q3_byte", EDMA_STAT(tx_q3_byte)},
+ {"tx_q4_byte", EDMA_STAT(tx_q4_byte)},
+ {"tx_q5_byte", EDMA_STAT(tx_q5_byte)},
+ {"tx_q6_byte", EDMA_STAT(tx_q6_byte)},
+ {"tx_q7_byte", EDMA_STAT(tx_q7_byte)},
+ {"tx_q8_byte", EDMA_STAT(tx_q8_byte)},
+ {"tx_q9_byte", EDMA_STAT(tx_q9_byte)},
+ {"tx_q10_byte", EDMA_STAT(tx_q10_byte)},
+ {"tx_q11_byte", EDMA_STAT(tx_q11_byte)},
+ {"tx_q12_byte", EDMA_STAT(tx_q12_byte)},
+ {"tx_q13_byte", EDMA_STAT(tx_q13_byte)},
+ {"tx_q14_byte", EDMA_STAT(tx_q14_byte)},
+ {"tx_q15_byte", EDMA_STAT(tx_q15_byte)},
+ {"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)},
+ {"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)},
+ {"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)},
+ {"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)},
+ {"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)},
+ {"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)},
+ {"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)},
+ {"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)},
+ {"rx_q0_byte", EDMA_STAT(rx_q0_byte)},
+ {"rx_q1_byte", EDMA_STAT(rx_q1_byte)},
+ {"rx_q2_byte", EDMA_STAT(rx_q2_byte)},
+ {"rx_q3_byte", EDMA_STAT(rx_q3_byte)},
+ {"rx_q4_byte", EDMA_STAT(rx_q4_byte)},
+ {"rx_q5_byte", EDMA_STAT(rx_q5_byte)},
+ {"rx_q6_byte", EDMA_STAT(rx_q6_byte)},
+ {"rx_q7_byte", EDMA_STAT(rx_q7_byte)},
+ {"tx_desc_error", EDMA_STAT(tx_desc_error)},
+ {"rx_alloc_fail_ctr", EDMA_STAT(rx_alloc_fail_ctr)},
+};
+
+#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)
+
+/* edma_get_strset_count()
+ * Get strset count
+ */
+static int edma_get_strset_count(struct net_device *netdev,
+ int sset)
+{
+ switch (sset) {
+ case ETH_SS_STATS:
+ return EDMA_STATS_LEN;
+ default:
+ netdev_dbg(netdev, "%s: Invalid string set", __func__);
+ return -EOPNOTSUPP;
+ }
+}
+
+
+/* edma_get_strings()
+ * get stats string
+ */
+static void edma_get_strings(struct net_device *netdev, uint32_t stringset,
+ uint8_t *data)
+{
+ uint8_t *p = data;
+ uint32_t i;
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < EDMA_STATS_LEN; i++) {
+ memcpy(p, edma_gstrings_stats[i].stat_string,
+ min((size_t)ETH_GSTRING_LEN,
+ strlen(edma_gstrings_stats[i].stat_string)
+ + 1));
+ p += ETH_GSTRING_LEN;
+ }
+ break;
+ }
+}
+
+/* edma_get_ethtool_stats()
+ * Get ethtool statistics
+ */
+static void edma_get_ethtool_stats(struct net_device *netdev,
+ struct ethtool_stats *stats, uint64_t *data)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
+ int i;
+ uint8_t *p = NULL;
+
+ edma_read_append_stats(edma_cinfo);
+
+ for(i = 0; i < EDMA_STATS_LEN; i++) {
+ p = (uint8_t *)&(edma_cinfo->edma_ethstats) +
+ edma_gstrings_stats[i].stat_offset;
+ data[i] = *(uint32_t *)p;
+ }
+}
+
+/* edma_get_drvinfo()
+ * get edma driver info
+ */
+static void edma_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ strlcpy(info->driver, "ess_edma", DRVINFO_LEN);
+ strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
+}
+
+/* edma_nway_reset()
+ * Reset the phy, if available.
+ */
+static int edma_nway_reset(struct net_device *netdev)
+{
+ return -EINVAL;
+}
+
+/* edma_get_wol()
+ * get wake on lan info
+ */
+static void edma_get_wol(struct net_device *netdev,
+ struct ethtool_wolinfo *wol)
+{
+ wol->supported = 0;
+ wol->wolopts = 0;
+}
+
+/* edma_get_msglevel()
+ * get message level.
+ */
+static uint32_t edma_get_msglevel(struct net_device *netdev)
+{
+ return 0;
+}
+
+/* edma_get_settings()
+ * Get edma settings
+ */
+#if 0
+static int edma_get_settings(struct net_device *netdev,
+ struct ethtool_cmd *ecmd)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+
+ if (adapter->poll_required) {
+ struct phy_device *phydev = NULL;
+ uint16_t phyreg;
+
+ if ((adapter->forced_speed != SPEED_UNKNOWN)
+ && !(adapter->poll_required))
+ return -EPERM;
+
+ phydev = adapter->phydev;
+
+ ecmd->advertising = phydev->advertising;
+ ecmd->autoneg = phydev->autoneg;
+
+ if (adapter->link_state == __EDMA_LINKDOWN) {
+ ecmd->speed = SPEED_UNKNOWN;
+ ecmd->duplex = DUPLEX_UNKNOWN;
+ } else {
+ ecmd->speed = phydev->speed;
+ ecmd->duplex = phydev->duplex;
+ }
+
+ ecmd->phy_address = adapter->phy_mdio_addr;
+
+ phyreg = (uint16_t)phy_read(adapter->phydev, MII_LPA);
+ if (phyreg & LPA_10HALF)
+ ecmd->lp_advertising |= ADVERTISED_10baseT_Half;
+
+ if (phyreg & LPA_10FULL)
+ ecmd->lp_advertising |= ADVERTISED_10baseT_Full;
+
+ if (phyreg & LPA_100HALF)
+ ecmd->lp_advertising |= ADVERTISED_100baseT_Half;
+
+ if (phyreg & LPA_100FULL)
+ ecmd->lp_advertising |= ADVERTISED_100baseT_Full;
+
+ phyreg = (uint16_t)phy_read(adapter->phydev, MII_STAT1000);
+ if (phyreg & LPA_1000HALF)
+ ecmd->lp_advertising |= ADVERTISED_1000baseT_Half;
+
+ if (phyreg & LPA_1000FULL)
+ ecmd->lp_advertising |= ADVERTISED_1000baseT_Full;
+ } else {
+ /* If the speed/duplex for this GMAC is forced and we
+ * are not polling for link state changes, return the
+ * values as specified by platform. This will be true
+ * for GMACs connected to switch, and interfaces that
+ * do not use a PHY.
+ */
+ if (!(adapter->poll_required)) {
+ if (adapter->forced_speed != SPEED_UNKNOWN) {
+ /* set speed and duplex */
+ ethtool_cmd_speed_set(ecmd, SPEED_1000);
+ ecmd->duplex = DUPLEX_FULL;
+
+ /* Populate capabilities advertised by self */
+ ecmd->advertising = 0;
+ ecmd->autoneg = 0;
+ ecmd->port = PORT_TP;
+ ecmd->transceiver = XCVR_EXTERNAL;
+ } else {
+ /* non link polled and non
+ * forced speed/duplex interface
+ */
+ return -EIO;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/* edma_set_settings()
+ * Set EDMA settings
+ */
+static int edma_set_settings(struct net_device *netdev,
+ struct ethtool_cmd *ecmd)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+ struct phy_device *phydev = NULL;
+
+ if ((adapter->forced_speed != SPEED_UNKNOWN) &&
+ !adapter->poll_required)
+ return -EPERM;
+
+ phydev = adapter->phydev;
+ phydev->advertising = ecmd->advertising;
+ phydev->autoneg = ecmd->autoneg;
+ phydev->speed = ethtool_cmd_speed(ecmd);
+ phydev->duplex = ecmd->duplex;
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+#endif
+
+/* edma_get_coalesce
+ * get interrupt mitigation
+ */
+static int edma_get_coalesce(struct net_device *netdev,
+ struct ethtool_coalesce *ec)
+{
+ u32 reg_val;
+
+ edma_get_tx_rx_coalesce(&reg_val);
+
+ /* We read the Interrupt Moderation Timer(IMT) register value,
+ * use lower 16 bit for rx and higher 16 bit for Tx. We do a
+ * left shift by 1, because IMT resolution timer is 2usecs.
+ * Hence the value given by the register is multiplied by 2 to
+ * get the actual time in usecs.
+ */
+ ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);
+ ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);
+
+ return 0;
+}
+
+/* edma_set_coalesce
+ * set interrupt mitigation
+ */
+static int edma_set_coalesce(struct net_device *netdev,
+ struct ethtool_coalesce *ec)
+{
+ if (ec->tx_coalesce_usecs)
+ edma_change_tx_coalesce(ec->tx_coalesce_usecs);
+ if (ec->rx_coalesce_usecs)
+ edma_change_rx_coalesce(ec->rx_coalesce_usecs);
+
+ return 0;
+}
+
+/* edma_set_priv_flags()
+ * Set EDMA private flags
+ */
+static int edma_set_priv_flags(struct net_device *netdev, u32 flags)
+{
+ return 0;
+}
+
+/* edma_get_priv_flags()
+ * get edma driver flags
+ */
+static u32 edma_get_priv_flags(struct net_device *netdev)
+{
+ return 0;
+}
+
+/* edma_get_ringparam()
+ * get ring size
+ */
+static void edma_get_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ring)
+{
+ struct edma_adapter *adapter = netdev_priv(netdev);
+ struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
+
+ ring->tx_max_pending = edma_cinfo->tx_ring_count;
+ ring->rx_max_pending = edma_cinfo->rx_ring_count;
+}
+
+/* Ethtool operations
+ */
+static const struct ethtool_ops edma_ethtool_ops = {
+ .get_drvinfo = &edma_get_drvinfo,
+ .get_link = &ethtool_op_get_link,
+ .get_msglevel = &edma_get_msglevel,
+ .nway_reset = &edma_nway_reset,
+ .get_wol = &edma_get_wol,
+// .get_settings = &edma_get_settings,
+// .set_settings = &edma_set_settings,
+ .get_strings = &edma_get_strings,
+ .get_sset_count = &edma_get_strset_count,
+ .get_ethtool_stats = &edma_get_ethtool_stats,
+ .get_coalesce = &edma_get_coalesce,
+ .set_coalesce = &edma_set_coalesce,
+ .get_priv_flags = edma_get_priv_flags,
+ .set_priv_flags = edma_set_priv_flags,
+ .get_ringparam = edma_get_ringparam,
+};
+
+/* edma_set_ethtool_ops
+ * Set ethtool operations
+ */
+void edma_set_ethtool_ops(struct net_device *netdev)
+{
+ netdev->ethtool_ops = &edma_ethtool_ops;
+}
diff --git a/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/ess_edma.h b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/ess_edma.h
new file mode 100644
index 0000000000..021be98a38
--- /dev/null
+++ b/target/linux/ipq40xx/files-5.4/drivers/net/ethernet/qualcomm/essedma/ess_edma.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ESS_EDMA_H_
+#define _ESS_EDMA_H_
+
+#include <linux/types.h>
+
+struct edma_adapter;
+struct edma_hw;
+
+/* register definition */
+#define EDMA_REG_MAS_CTRL 0x0
+#define EDMA_REG_TIMEOUT_CTRL 0x004
+#define EDMA_REG_DBG0 0x008
+#define EDMA_REG_DBG1 0x00C
+#define EDMA_REG_SW_CTRL0 0x100
+#define EDMA_REG_SW_CTRL1 0x104
+
+/* Interrupt Status Register */
+#define EDMA_REG_RX_ISR 0x200
+#define EDMA_REG_TX_ISR 0x208
+#define EDMA_REG_MISC_ISR 0x210
+#define EDMA_REG_WOL_ISR 0x218
+
+#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)
+
+#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100
+#define EDMA_MISC_ISR_AXIR_ERR 0x00000200
+#define EDMA_MISC_ISR_TXF_DEAD 0x00000400
+#define EDMA_MISC_ISR_AXIW_ERR 0x00000800
+#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000
+
+#define EDMA_WOL_ISR 0x00000001
+
+/* Interrupt Mask Register */
+#define EDMA_REG_MISC_IMR 0x214
+#define EDMA_REG_WOL_IMR 0x218
+
+#define EDMA_RX_IMR_NORMAL_MASK 0x1
+#define EDMA_TX_IMR_NORMAL_MASK 0x1
+#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF
+#define EDMA_WOL_IMR_NORMAL_MASK 0x1
+
+/* Edma receive consumer index */
+#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
+/* Edma transmit consumer index */
+#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
+
+/* IRQ Moderator Initial Timer Register */
+#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280
+#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF
+#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0
+#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16
+
+/* Interrupt Control Register */
+#define EDMA_REG_INTR_CTRL 0x284
+#define EDMA_INTR_CLR_TYP_SHIFT 0
+#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1
+#define EDMA_INTR_CLEAR_TYPE_W1 0
+#define EDMA_INTR_CLEAR_TYPE_R 1
+
+/* RX Interrupt Mask Register */
+#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
+
+/* TX Interrupt mask register */
+#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
+
+/* Load Ptr Register
+ * Software sets this bit after the initialization of the head and tail
+ */
+#define EDMA_REG_TX_SRAM_PART 0x400
+#define EDMA_LOAD_PTR_SHIFT 16
+
+/* TXQ Control Register */
+#define EDMA_REG_TXQ_CTRL 0x404
+#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10
+#define EDMA_TXQ_CTRL_TXQ_EN 0x20
+#define EDMA_TXQ_CTRL_ENH_MODE 0x40
+#define EDMA_TXQ_CTRL_LS_8023_EN 0x80
+#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100
+#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200
+#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF
+#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF
+#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0
+#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16
+
+#define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
+#define EDMA_TXF_WATER_MARK_MASK 0x0FFF
+#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0
+#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16
+#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000
+
+/* WRR Control Register */
+#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c
+#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410
+#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414
+#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418
+
+/* Weight round robin(WRR), it takes queue as input, and computes
+ * starting bits where we need to write the weight for a particular
+ * queue
+ */
+#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)
+
+/* Tx Descriptor Control Register */
+#define EDMA_REG_TPD_RING_SIZE 0x41C
+#define EDMA_TPD_RING_SIZE_SHIFT 0
+#define EDMA_TPD_RING_SIZE_MASK 0xFFFF
+
+/* Transmit descriptor base address */
+#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
+
+/* TPD Index Register */
+#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
+
+#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF
+#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000
+#define EDMA_TPD_PROD_IDX_MASK 0xFFFF
+#define EDMA_TPD_CONS_IDX_MASK 0xFFFF
+#define EDMA_TPD_PROD_IDX_SHIFT 0
+#define EDMA_TPD_CONS_IDX_SHIFT 16
+
+/* TX Virtual Queue Mapping Control Register */
+#define EDMA_REG_VQ_CTRL0 0x4A0
+#define EDMA_REG_VQ_CTRL1 0x4A4
+
+/* Virtual QID shift, it takes queue as input, and computes
+ * Virtual QID position in virtual qid control register
+ */
+#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)
+
+/* Virtual Queue Default Value */
+#define EDMA_VQ_REG_VALUE 0x240240
+
+/* Tx side Port Interface Control Register */
+#define EDMA_REG_PORT_CTRL 0x4A8
+#define EDMA_PAD_EN_SHIFT 15
+
+/* Tx side VLAN Configuration Register */
+#define EDMA_REG_VLAN_CFG 0x4AC
+
+#define EDMA_TX_CVLAN 16
+#define EDMA_TX_INS_CVLAN 17
+#define EDMA_TX_CVLAN_TAG_SHIFT 0
+
+#define EDMA_TX_SVLAN 14
+#define EDMA_TX_INS_SVLAN 15
+#define EDMA_TX_SVLAN_TAG_SHIFT 16
+
+/* Tx Queue Packet Statistic Register */
+#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
+
+#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF
+
+/* Tx Queue Byte Statistic Register */
+#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
+
+/* Load Balance Based Ring Offset Register */
+#define EDMA_REG_LB_RING 0x800
+#define EDMA_LB_RING_ENTRY_MASK 0xff
+#define EDMA_LB_RING_ID_MASK 0x7
+#define EDMA_LB_RING_PROFILE_ID_MASK 0x3
+#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8
+#define EDMA_LB_RING_ID_OFFSET 0
+#define EDMA_LB_RING_PROFILE_ID_OFFSET 3
+#define EDMA_LB_REG_VALUE 0x6040200
+
+/* Load Balance Priority Mapping Register */
+#define EDMA_REG_LB_PRI_START 0x804
+#define EDMA_REG_LB_PRI_END 0x810
+#define EDMA_LB_PRI_REG_INC 4
+#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4
+#define EDMA_LB_PRI_ENTRY_MASK 0xf
+
+/* RSS Priority Mapping Register */
+#define EDMA_REG_RSS_PRI 0x820
+#define EDMA_RSS_PRI_ENTRY_MASK 0xf
+#define EDMA_RSS_RING_ID_MASK 0x7
+#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4
+
+/* RSS Indirection Register */
+#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
+#define EDMA_NUM_IDT 16
+#define EDMA_RSS_IDT_VALUE 0x64206420
+
+/* Default RSS Ring Register */
+#define EDMA_REG_DEF_RSS 0x890
+#define EDMA_DEF_RSS_MASK 0x7
+
+/* RSS Hash Function Type Register */
+#define EDMA_REG_RSS_TYPE 0x894
+#define EDMA_RSS_TYPE_NONE 0x01
+#define EDMA_RSS_TYPE_IPV4TCP 0x02
+#define EDMA_RSS_TYPE_IPV6_TCP 0x04
+#define EDMA_RSS_TYPE_IPV4_UDP 0x08
+#define EDMA_RSS_TYPE_IPV6UDP 0x10
+#define EDMA_RSS_TYPE_IPV4 0x20
+#define EDMA_RSS_TYPE_IPV6 0x40
+#define EDMA_RSS_HASH_MODE_MASK 0x7f
+
+#define EDMA_REG_RSS_HASH_VALUE 0x8C0
+
+#define EDMA_REG_RSS_TYPE_RESULT 0x8C4
+
+#define EDMA_HASH_TYPE_START 0
+#define EDMA_HASH_TYPE_END 5
+#define EDMA_HASH_TYPE_SHIFT 12
+
+#define EDMA_RFS_FLOW_ENTRIES 1024
+#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
+#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128
+
+/* RFD Base Address Register */
+#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
+
+/* RFD Index Register */
+#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))
+
+#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF
+#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000
+#define EDMA_RFD_PROD_IDX_MASK 0xFFF
+#define EDMA_RFD_CONS_IDX_MASK 0xFFF
+#define EDMA_RFD_PROD_IDX_SHIFT 0
+#define EDMA_RFD_CONS_IDX_SHIFT 16
+
+/* Rx Descriptor Control Register */
+#define EDMA_REG_RX_DESC0 0xA10
+#define EDMA_RFD_RING_SIZE_MASK 0xFFF
+#define EDMA_RX_BUF_SIZE_MASK 0xFFFF
+#define EDMA_RFD_RING_SIZE_SHIFT 0
+#define EDMA_RX_BUF_SIZE_SHIFT 16
+
+#define EDMA_REG_RX_DESC1 0xA14
+#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F
+#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F
+#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF
+#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0
+#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8
+#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16
+
+/* RXQ Control Register */
+#define EDMA_REG_RXQ_CTRL 0xA18
+#define EDMA_FIFO_THRESH_TYPE_SHIF 0
+#define EDMA_FIFO_THRESH_128_BYTE 0x0
+#define EDMA_FIFO_THRESH_64_BYTE 0x1
+#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002
+#define EDMA_RXQ_CTRL_EN 0x0000FF00
+
+/* AXI Burst Size Config */
+#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
+#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0
+
+/* Rx Statistics Register */
+#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
+#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
+
+/* WoL Pattern Length Register */
+#define EDMA_REG_WOL_PATTERN_LEN0 0xC00
+#define EDMA_WOL_PT_LEN_MASK 0xFF
+#define EDMA_WOL_PT0_LEN_SHIFT 0
+#define EDMA_WOL_PT1_LEN_SHIFT 8
+#define EDMA_WOL_PT2_LEN_SHIFT 16
+#define EDMA_WOL_PT3_LEN_SHIFT 24
+
+#define EDMA_REG_WOL_PATTERN_LEN1 0xC04
+#define EDMA_WOL_PT4_LEN_SHIFT 0
+#define EDMA_WOL_PT5_LEN_SHIFT 8
+#define EDMA_WOL_PT6_LEN_SHIFT 16
+
+/* WoL Control Register */
+#define EDMA_REG_WOL_CTRL 0xC08
+#define EDMA_WOL_WK_EN 0x00000001
+#define EDMA_WOL_MG_EN 0x00000002
+#define EDMA_WOL_PT0_EN 0x00000004
+#define EDMA_WOL_PT1_EN 0x00000008
+#define EDMA_WOL_PT2_EN 0x00000010
+#define EDMA_WOL_PT3_EN 0x00000020
+#define EDMA_WOL_PT4_EN 0x00000040
+#define EDMA_WOL_PT5_EN 0x00000080
+#define EDMA_WOL_PT6_EN 0x00000100
+
+/* MAC Control Register */
+#define EDMA_REG_MAC_CTRL0 0xC20
+#define EDMA_REG_MAC_CTRL1 0xC24
+
+/* WoL Pattern Register */
+#define EDMA_REG_WOL_PATTERN_START 0x5000
+#define EDMA_PATTERN_PART_REG_OFFSET 0x40
+
+
+/* TX descriptor fields */
+#define EDMA_TPD_HDR_SHIFT 0
+#define EDMA_TPD_PPPOE_EN 0x00000100
+#define EDMA_TPD_IP_CSUM_EN 0x00000200
+#define EDMA_TPD_TCP_CSUM_EN 0x0000400
+#define EDMA_TPD_UDP_CSUM_EN 0x00000800
+#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00
+#define EDMA_TPD_LSO_EN 0x00001000
+#define EDMA_TPD_LSO_V2_EN 0x00002000
+#define EDMA_TPD_IPV4_EN 0x00010000
+#define EDMA_TPD_MSS_MASK 0x1FFF
+#define EDMA_TPD_MSS_SHIFT 18
+#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18
+
+/* RRD descriptor fields */
+#define EDMA_RRD_NUM_RFD_MASK 0x000F
+#define EDMA_RRD_SVLAN 0x8000
+#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;
+
+#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF
+#define EDMA_RRD_CSUM_FAIL_MASK 0xC000
+#define EDMA_RRD_CVLAN 0x0001
+#define EDMA_RRD_DESC_VALID 0x8000
+
+#define EDMA_RRD_PRIORITY_SHIFT 4
+#define EDMA_RRD_PRIORITY_MASK 0x7
+#define EDMA_RRD_PORT_TYPE_SHIFT 7
+#define EDMA_RRD_PORT_TYPE_MASK 0x1F
+
+#define ESS_RGMII_CTRL 0x0004
+
+/* Port status registers */
+#define ESS_PORT0_STATUS 0x007C
+#define ESS_PORT1_STATUS 0x0080
+#define ESS_PORT2_STATUS 0x0084
+#define ESS_PORT3_STATUS 0x0088
+#define ESS_PORT4_STATUS 0x008C
+#define ESS_PORT5_STATUS 0x0090
+
+#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80
+#define ESS_PORT_STATUS_DUPLEX_MODE 0x40
+#define ESS_PORT_STATUS_RX_FLOW_EN 0x20
+#define ESS_PORT_STATUS_TX_FLOW_EN 0x10
+#define ESS_PORT_STATUS_RX_MAC_EN 0x08
+#define ESS_PORT_STATUS_TX_MAC_EN 0x04
+#define ESS_PORT_STATUS_SPEED_INV 0x03
+#define ESS_PORT_STATUS_SPEED_1000 0x02
+#define ESS_PORT_STATUS_SPEED_100 0x01
+#define ESS_PORT_STATUS_SPEED_10 0x00
+
+#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
+ ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \
+ ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000)
+
+#define PHY_STATUS_REG 0x11
+#define PHY_STATUS_SPEED 0xC000
+#define PHY_STATUS_SPEED_SHIFT 14
+#define PHY_STATUS_DUPLEX 0x2000
+#define PHY_STATUS_DUPLEX_SHIFT 13
+#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
+#define PHY_STATUS_CARRIER 0x0400
+#define PHY_STATUS_CARRIER_SHIFT 10
+
+/* Port lookup control registers */
+#define ESS_PORT0_LOOKUP_CTRL 0x0660
+#define ESS_PORT1_LOOKUP_CTRL 0x066C
+#define ESS_PORT2_LOOKUP_CTRL 0x0678
+#define ESS_PORT3_LOOKUP_CTRL 0x0684
+#define ESS_PORT4_LOOKUP_CTRL 0x0690
+#define ESS_PORT5_LOOKUP_CTRL 0x069C
+
+#define ESS_PORT0_HEADER_CTRL 0x009C
+
+#define ESS_PORTS_ALL 0x3f
+
+#define ESS_FWD_CTRL1 0x0624
+#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7)
+#define ESS_FWD_CTRL1_UC_FLOOD_S 0
+#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7)
+#define ESS_FWD_CTRL1_MC_FLOOD_S 8
+#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7)
+#define ESS_FWD_CTRL1_BC_FLOOD_S 16
+#define ESS_FWD_CTRL1_IGMP BITS(24, 7)
+#define ESS_FWD_CTRL1_IGMP_S 24
+
+#endif /* _ESS_EDMA_H_ */