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authorKristian Evensen <kristian.evensen@gmail.com>2019-10-20 11:33:13 +0200
committerJohn Crispin <john@phrozen.org>2019-10-21 12:28:03 +0200
commit6f6c00cfc95f603a533ff142cc0e1d34a4ab0588 (patch)
tree39173e7fe076ba1e988965433586bee88ff50914 /target/linux/ipq40xx/files-4.19/arch/arm
parentee41b602a2a2ced06c26e6edc160b2a5e9619f0d (diff)
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ipq40xx: Add support for Unielec U4019
This commit adds support for the 32MB storage/512MB RAM version of the U4019 IPQ4019-based board from Unielec. The board has the following specifications: * Qualcomm IPQ4019 (running at 717MHz) * 512MB DDR3 RAM (optional 256MB/1GB) * 32MB SPI NOR (optional 8/16MB or NAND) * Five gigabit ports (Qualcomm QCA8075) * 1x 2.4 GHz wifi (QCA4019 hw1.0) * 1x 5 Ghz wifi (QCA4019 hw1.0) * 1x mini-PCIe slot (only USB-pins connected) * 1x SIM slot (mini-SIM) * 1x USB2.0 port * 1x button * 1x controllable LED * 1x micro SD-card reader Working: * Ethernet * Wifi * USB-port * mini-PCIe slot + SIM slot * Button * Sysupgrade Not working: * SD card slot (no upstream support) Installation instructions: In order to install OpenWRT on the U4019, you need to go via the initramfs-image. The installation steps are as follows: * Connect to board via serial (header exposed and clearly marked). * Interrupt bootloader by pressing a button. * Copy the initramfs-image to your tftp folder, call the file C0A80079.img. * Give the network interface connected to the U4019 the address 192.168.0.156/24. * Start your tftp-server and run tftpboot on the board. * Run bootm when the file has been transferred, to boot OpenWRT. * Once OpenWRT has booted, copy the sysupgrade-image to the device and run sysupgrade to install OpenWRT on the U4019. Notes: - Since IPQ4019 has been moved to 4.19, I have not added support for kernel 4.14. - There is a bug with hardware encryption on IPQ4019, causing poor performance with TCP and ipsec (see for example FS#2355). In order to improve performance, I have disabled hardware encryption in the DTS. We can enable hw. enc. once/if bug is fixed. - In order for Ethernet to work, the phy has to be reset by setting gpio 47 low/high. Adding support for phy reset via gpio required patching the mdio-driver, and the code added comes from the vendor driver. I do not know if patching the driver is an acceptable approach or not. v1->v2: * Do not use wildcard as identifier in the board.d-scripts (thanks Adrian Schmutzler). Signed-off-by: Kristian Evensen <kristian.evensen@gmail.com>
Diffstat (limited to 'target/linux/ipq40xx/files-4.19/arch/arm')
-rw-r--r--target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019-32m.dts79
-rw-r--r--target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019.dtsi223
2 files changed, 302 insertions, 0 deletions
diff --git a/target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019-32m.dts b/target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019-32m.dts
new file mode 100644
index 0000000000..606ac165ba
--- /dev/null
+++ b/target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019-32m.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "qcom-ipq4019-unielec-u4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Unielec U4019 (32M)";
+ compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <24000000>;
+ broken-flash-reset;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ partition@f0000 {
+ label = "0:APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ partition@170000 {
+ label = "0:ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ partition@180000 {
+ compatible = "denx,fit";
+ label = "firmware";
+ reg = <0x180000 0x1e80000>;
+ };
+ };
+ };
+};
+
diff --git a/target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019.dtsi b/target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019.dtsi
new file mode 100644
index 0000000000..cf67fddd2b
--- /dev/null
+++ b/target/linux/ipq40xx/files-4.19/arch/arm/boot/dts/qcom-ipq4019-unielec-u4019.dtsi
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ compatible = "unielec,u4019","qcom,ipq4019";
+
+ soc {
+ rng@22000 {
+ status = "okay";
+ };
+
+ mdio@90000 {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy-reset-gpio = <&tlmm 47 0>;
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
+ usb2@60f8800 {
+ status = "okay";
+
+ dwc3@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ usb3@8af8800 {
+ status = "okay";
+
+ dwc3@8a00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ aliases {
+ led-boot = &led_status;
+ led-failsafe = &led_status;
+ led-running = &led_status;
+ led-upgrade = &led_status;
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&led_pins>;
+ pinctrl-names = "default";
+
+ led_status: led2 {
+ label = "u4019:green:led2";
+ gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&tlmm {
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial_0_pins: serial0-pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ led_pins: led_pinmux {
+ mux {
+ function = "gpio";
+ pins = "gpio68";
+ bias-disabled;
+ output-low;
+ };
+ };
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
+};