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author | Robert Marko <robert.marko@sartura.hr> | 2021-12-27 15:11:18 +0100 |
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committer | David Bauer <mail@david-bauer.net> | 2022-10-02 23:04:38 +0200 |
commit | b1f21329d4358e74864f17eedd0f887e5ad2a816 (patch) | |
tree | b2927367ab3494128b68637cc874cf307bf6c003 /target/linux/ipq40xx/config-5.15 | |
parent | 28b13bb15766aa6d888718ad83fe3aebcdfd512a (diff) | |
download | upstream-b1f21329d4358e74864f17eedd0f887e5ad2a816.tar.gz upstream-b1f21329d4358e74864f17eedd0f887e5ad2a816.tar.bz2 upstream-b1f21329d4358e74864f17eedd0f887e5ad2a816.zip |
ipq40xx: add DSA switch driver
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
It shares most of the stuff with its external counterpart, however it is
modified for the SoC.
Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
instead of 7.
It also has no built-in PHY-s but rather requires external PSGMII based
companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
out calibration before using them.
PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
unfortunately requires some magic values as the datasheet doesnt document
the bits that are being set or the register at all.
Since its built-in it is MMIO like other peripherals and doesn't have its
own MDIO bus but depends on the SoC provided one.
CPU connection is at Port 0 and it uses some kind of a internal connection
and no traditional RGMII/SGMII.
It also doesn't use in-band tagging like other qca8k switches so a shinfo
based tagger is used.
This is based on the current OpenWrt qca8k version that has been imported
from generic target.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Diffstat (limited to 'target/linux/ipq40xx/config-5.15')
0 files changed, 0 insertions, 0 deletions