aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/imx6/patches-4.3
diff options
context:
space:
mode:
authorLuka Perkov <luka@openwrt.org>2016-01-18 06:43:48 +0000
committerLuka Perkov <luka@openwrt.org>2016-01-18 06:43:48 +0000
commitc4de2dfd2d79021626acdbaefc6cc9c17eac35bf (patch)
tree7c66af2dac9f181d8e9c431ab9f73066de075f24 /target/linux/imx6/patches-4.3
parent85bdde7cf2821655c74fb4381926335a1161f0c1 (diff)
downloadupstream-c4de2dfd2d79021626acdbaefc6cc9c17eac35bf.tar.gz
upstream-c4de2dfd2d79021626acdbaefc6cc9c17eac35bf.tar.bz2
upstream-c4de2dfd2d79021626acdbaefc6cc9c17eac35bf.zip
imx6: drop 4.3 support
Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 48299
Diffstat (limited to 'target/linux/imx6/patches-4.3')
-rw-r--r--target/linux/imx6/patches-4.3/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch26
-rw-r--r--target/linux/imx6/patches-4.3/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch33
-rw-r--r--target/linux/imx6/patches-4.3/037-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch70
-rw-r--r--target/linux/imx6/patches-4.3/040-ARM-dts-imx-ventana-add-pwm-nodes.patch264
-rw-r--r--target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch33
-rw-r--r--target/linux/imx6/patches-4.3/045-imx-thermal-use-cpu-temperature-grade-info-for-thresholds112
-rw-r--r--target/linux/imx6/patches-4.3/100-bootargs.patch11
-rw-r--r--target/linux/imx6/patches-4.3/202-net-igb-add-i210-i211-support-for-phy-read-write.patch129
-rw-r--r--target/linux/imx6/patches-4.3/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch260
-rw-r--r--target/linux/imx6/patches-4.3/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch308
-rw-r--r--target/linux/imx6/patches-4.3/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch27
-rw-r--r--target/linux/imx6/patches-4.3/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch56
-rw-r--r--target/linux/imx6/patches-4.3/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch22
-rw-r--r--target/linux/imx6/patches-4.3/208-sky2-allow-mac-to-come-from-dt.patch28
-rw-r--r--target/linux/imx6/patches-4.3/209-ARM-imx-ventana-add-sky2-alias.patch20
15 files changed, 0 insertions, 1399 deletions
diff --git a/target/linux/imx6/patches-4.3/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch b/target/linux/imx6/patches-4.3/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch
deleted file mode 100644
index db166ed6fa..0000000000
--- a/target/linux/imx6/patches-4.3/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 57b82d9e79d77442bae3d2c13b98ceccb39fe5e2 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 5 Nov 2015 10:49:31 -0800
-Subject: [PATCH 1/3] ARM: dts: imx: ventana: set GW54xx PMIC swbst regulator
- as always-on
-
-The GW54xx PMIC swbst regulator is used for LVDS power, CANbus xceiver
-and HDMI DDC and is enabled by the bootloader. Set the regulator to
-always-on so that Linux doesn't turn it off thinking its not needed.
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-@@ -260,6 +260,8 @@
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
-+ regulator-boot-on;
-+ regulator-always-on;
- };
-
- snvs_reg: vsnvs {
diff --git a/target/linux/imx6/patches-4.3/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch b/target/linux/imx6/patches-4.3/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch
deleted file mode 100644
index 2101fdfcf3..0000000000
--- a/target/linux/imx6/patches-4.3/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 473d0353979db3673a7aa365265ba9b00decd414 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 5 Nov 2015 10:52:53 -0800
-Subject: [PATCH 2/3] ARM: dts: imx: ventana: fix GW53xx/GW54xx lvds channel
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 2 +-
- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-@@ -247,7 +247,7 @@
- &ldb {
- status = "okay";
-
-- lvds-channel@1 {
-+ lvds-channel@0 {
- fsl,data-mapping = "spwg";
- fsl,data-width = <18>;
- status = "okay";
---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-@@ -338,7 +338,7 @@
- &ldb {
- status = "okay";
-
-- lvds-channel@1 {
-+ lvds-channel@0 {
- fsl,data-mapping = "spwg";
- fsl,data-width = <18>;
- status = "okay";
diff --git a/target/linux/imx6/patches-4.3/037-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch b/target/linux/imx6/patches-4.3/037-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch
deleted file mode 100644
index c861e3848c..0000000000
--- a/target/linux/imx6/patches-4.3/037-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From d86b202436b6f3111c4c37b8701daa0764d2ca55 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 5 Nov 2015 11:10:00 -0800
-Subject: [PATCH 3/3] ARM: dts: imx: ventana: Allow HDMI and LVDS to work
- simultaneously
-
-Currently it is not possible to have HDMI and LVDS working simultaneously,
-because both ports try to use PLL5.
-
-Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
-driven from independent sources.
-
-With this change the LDB pixel clock goes to 68.57 MHz, which is still
-within the valid range for the displays supported by the Ventana boards.
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 7 +++++++
- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 7 +++++++
- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 7 +++++++
- 3 files changed, 21 insertions(+)
-
---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-@@ -151,6 +151,13 @@
- status = "okay";
- };
-
-+&clks {
-+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-+};
-+
- &fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-@@ -152,6 +152,13 @@
- status = "okay";
- };
-
-+&clks {
-+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-+};
-+
- &fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-@@ -142,6 +142,13 @@
- status = "okay";
- };
-
-+&clks {
-+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-+};
-+
- &fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
diff --git a/target/linux/imx6/patches-4.3/040-ARM-dts-imx-ventana-add-pwm-nodes.patch b/target/linux/imx6/patches-4.3/040-ARM-dts-imx-ventana-add-pwm-nodes.patch
deleted file mode 100644
index 759f32e6f6..0000000000
--- a/target/linux/imx6/patches-4.3/040-ARM-dts-imx-ventana-add-pwm-nodes.patch
+++ /dev/null
@@ -1,264 +0,0 @@
---- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
-@@ -174,6 +174,24 @@
- status = "okay";
- };
-
-+&pwm2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
-+ status = "disabled";
-+};
-+
-+&pwm3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
-+ status = "disabled";
-+};
-+
-+&pwm4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
-+ status = "disabled";
-+};
-+
- &uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
-@@ -294,6 +312,24 @@
- >;
- };
-
-+ pinctrl_pwm2: pwm2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm3: pwm3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm4: pwm4grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
-+ >;
-+ };
-+
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-@@ -282,6 +282,18 @@
- status = "okay";
- };
-
-+&pwm2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
-+ status = "disabled";
-+};
-+
-+&pwm3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
-+ status = "disabled";
-+};
-+
- &pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
-@@ -436,6 +448,18 @@
- >;
- };
-
-+ pinctrl_pwm2: pwm2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm3: pwm3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
-+ >;
-+ };
-+
- pinctrl_pwm4: pwm4grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-@@ -287,6 +287,18 @@
- };
- };
-
-+&pwm2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
-+ status = "disabled";
-+};
-+
-+&pwm3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
-+ status = "disabled";
-+};
-+
- &pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
-@@ -442,6 +454,18 @@
- >;
- };
-
-+ pinctrl_pwm2: pwm2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm3: pwm3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
-+ >;
-+ };
-+
- pinctrl_pwm4: pwm4grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-@@ -378,6 +378,24 @@
- };
- };
-
-+&pwm1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
-+ status = "disabled";
-+};
-+
-+&pwm2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
-+ status = "disabled";
-+};
-+
-+&pwm3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
-+ status = "disabled";
-+};
-+
- &pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
-@@ -537,6 +555,24 @@
- >;
- };
-
-+ pinctrl_pwm1: pwm1grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm2: pwm2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm3: pwm3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
-+ >;
-+ };
-+
- pinctrl_pwm4: pwm4grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
---- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
-@@ -198,6 +198,18 @@
- status = "okay";
- };
-
-+&pwm2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
-+ status = "disabled";
-+};
-+
-+&pwm3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
-+ status = "disabled";
-+};
-+
- &ssi1 {
- status = "okay";
- };
-@@ -290,6 +302,18 @@
- >;
- };
-
-+ pinctrl_pwm2: pwm2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm3: pwm3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
-+ >;
-+ };
-+
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
---- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
-@@ -164,6 +164,18 @@
- status = "okay";
- };
-
-+&pwm2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
-+ status = "disabled";
-+};
-+
-+&pwm3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
-+ status = "disabled";
-+};
-+
- &uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
-@@ -242,6 +254,18 @@
- >;
- };
-
-+ pinctrl_pwm2: pwm2grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_pwm3: pwm3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
-+ >;
-+ };
-+
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
diff --git a/target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch b/target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch
deleted file mode 100644
index da3571559e..0000000000
--- a/target/linux/imx6/patches-4.3/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-@@ -158,6 +158,14 @@
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
- };
-
-+&ecspi3 {
-+ fsl,spi-num-chipselects = <1>;
-+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_ecspi3>;
-+ status = "okay";
-+};
-+
- &fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
-@@ -357,6 +365,15 @@
- >;
- };
-
-+ pinctrl_ecspi3: escpi3grp {
-+ fsl,pins = <
-+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
-+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
-+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
-+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
-+ >;
-+ };
-+
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
diff --git a/target/linux/imx6/patches-4.3/045-imx-thermal-use-cpu-temperature-grade-info-for-thresholds b/target/linux/imx6/patches-4.3/045-imx-thermal-use-cpu-temperature-grade-info-for-thresholds
deleted file mode 100644
index 6baf7dd801..0000000000
--- a/target/linux/imx6/patches-4.3/045-imx-thermal-use-cpu-temperature-grade-info-for-thresholds
+++ /dev/null
@@ -1,112 +0,0 @@
---- a/drivers/thermal/imx_thermal.c
-+++ b/drivers/thermal/imx_thermal.c
-@@ -55,6 +55,7 @@
- #define TEMPSENSE2_PANIC_VALUE_SHIFT 16
- #define TEMPSENSE2_PANIC_VALUE_MASK 0xfff0000
-
-+#define OCOTP_MEM0 0x0480
- #define OCOTP_ANA1 0x04e0
-
- /* The driver supports 1 passive trip point and 1 critical trip point */
-@@ -64,12 +65,6 @@ enum imx_thermal_trip {
- IMX_TRIP_NUM,
- };
-
--/*
-- * It defines the temperature in millicelsius for passive trip point
-- * that will trigger cooling action when crossed.
-- */
--#define IMX_TEMP_PASSIVE 85000
--
- #define IMX_POLLING_DELAY 2000 /* millisecond */
- #define IMX_PASSIVE_DELAY 1000
-
-@@ -100,12 +95,14 @@ struct imx_thermal_data {
- u32 c1, c2; /* See formula in imx_get_sensor_data() */
- int temp_passive;
- int temp_critical;
-+ unsigned long temp_max;
- int alarm_temp;
- int last_temp;
- bool irq_enabled;
- int irq;
- struct clk *thermal_clk;
- const struct thermal_soc_data *socdata;
-+ const char *temp_grade;
- };
-
- static void imx_set_panic_temp(struct imx_thermal_data *data,
-@@ -285,10 +282,12 @@ static int imx_set_trip_temp(struct ther
- {
- struct imx_thermal_data *data = tz->devdata;
-
-+ /* do not allow changing critical threshold */
- if (trip == IMX_TRIP_CRITICAL)
- return -EPERM;
-
-- if (temp > IMX_TEMP_PASSIVE)
-+ /* do not allow passive to be set higher than critical */
-+ if (temp < 0 || temp > data->temp_critical)
- return -EINVAL;
-
- data->temp_passive = temp;
-@@ -404,17 +403,39 @@ static int imx_get_sensor_data(struct pl
- data->c1 = temp64;
- data->c2 = n1 * data->c1 + 1000 * t1;
-
-- /*
-- * Set the default passive cooling trip point,
-- * can be changed from userspace.
-- */
-- data->temp_passive = IMX_TEMP_PASSIVE;
-+ /* use OTP for thermal grade */
-+ ret = regmap_read(map, OCOTP_MEM0, &val);
-+ if (ret) {
-+ dev_err(&pdev->dev, "failed to read temp grade: %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* The maximum die temp is specified by the Temperature Grade */
-+ switch ((val >> 6) & 0x3) {
-+ case 0: /* Commercial (0 to 95C) */
-+ data->temp_grade = "Commercial";
-+ data->temp_max = 95000;
-+ break;
-+ case 1: /* Extended Commercial (-20 to 105C) */
-+ data->temp_grade = "Extended Commercial";
-+ data->temp_max = 105000;
-+ break;
-+ case 2: /* Industrial (-40 to 105C) */
-+ data->temp_grade = "Industrial";
-+ data->temp_max = 105000;
-+ break;
-+ case 3: /* Automotive (-40 to 125C) */
-+ data->temp_grade = "Automotive";
-+ data->temp_max = 125000;
-+ break;
-+ }
-
- /*
-- * The maximum die temperature set to 20 C higher than
-- * IMX_TEMP_PASSIVE.
-+ * Set the critical trip point at 5C under max
-+ * Set the passive trip point at 10C under max (can change via sysfs)
- */
-- data->temp_critical = 1000 * 20 + data->temp_passive;
-+ data->temp_critical = data->temp_max - (1000 * 5);
-+ data->temp_passive = data->temp_max - (1000 * 10);
-
- return 0;
- }
-@@ -559,6 +580,11 @@ static int imx_thermal_probe(struct plat
- return ret;
- }
-
-+ dev_info(&pdev->dev, "%s CPU temperature grade - max:%ldC"
-+ " critical:%ldC passive:%ldC\n", data->temp_grade,
-+ data->temp_max / 1000, data->temp_critical / 1000,
-+ data->temp_passive / 1000);
-+
- /* Enable measurements at ~ 10 Hz */
- regmap_write(map, TEMPSENSE1 + REG_CLR, TEMPSENSE1_MEASURE_FREQ);
- measure_freq = DIV_ROUND_UP(32768, 10); /* 10 Hz */
diff --git a/target/linux/imx6/patches-4.3/100-bootargs.patch b/target/linux/imx6/patches-4.3/100-bootargs.patch
deleted file mode 100644
index 0954391203..0000000000
--- a/target/linux/imx6/patches-4.3/100-bootargs.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/imx6dl-wandboard.dts
-+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
-@@ -19,4 +19,8 @@
- memory {
- reg = <0x10000000 0x40000000>;
- };
-+
-+ chosen {
-+ bootargs = "console=ttymxc0,115200";
-+ };
- };
diff --git a/target/linux/imx6/patches-4.3/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-4.3/202-net-igb-add-i210-i211-support-for-phy-read-write.patch
deleted file mode 100644
index 6bc23c5206..0000000000
--- a/target/linux/imx6/patches-4.3/202-net-igb-add-i210-i211-support-for-phy-read-write.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-Author: Tim Harvey <tharvey@gateworks.com>
-Date: Thu May 15 00:12:26 2014 -0700
-
- net: igb: add i210/i211 support for phy read/write
-
- The i210/i211 uses the MDICNFG register for the phy address instead of the
- MDIC register.
-
- Signed-off-by: Tim Harvey <tharvey@gateworks.com>
-
---- a/drivers/net/ethernet/intel/igb/e1000_phy.c
-+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
-@@ -129,7 +129,7 @@ out:
- s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
- {
- struct e1000_phy_info *phy = &hw->phy;
-- u32 i, mdic = 0;
-+ u32 i, mdicnfg, mdic = 0;
- s32 ret_val = 0;
-
- if (offset > MAX_PHY_REG_ADDRESS) {
-@@ -142,11 +142,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
- * Control register. The MAC will take care of interfacing with the
- * PHY to retrieve the desired data.
- */
-- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
-- (phy->addr << E1000_MDIC_PHY_SHIFT) |
-- (E1000_MDIC_OP_READ));
-+ switch (hw->mac.type) {
-+ case e1000_i210:
-+ case e1000_i211:
-+ mdicnfg = rd32(E1000_MDICNFG);
-+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
-+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
-+ wr32(E1000_MDICNFG, mdicnfg);
-+ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
-+ (E1000_MDIC_OP_READ));
-+ break;
-+ default:
-+ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
-+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
-+ (E1000_MDIC_OP_READ));
-+ break;
-+ }
-
- wr32(E1000_MDIC, mdic);
-+ wrfl();
-
- /* Poll the ready bit to see if the MDI read completed
- * Increasing the time out as testing showed failures with
-@@ -171,6 +185,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
- *data = (u16) mdic;
-
- out:
-+ switch (hw->mac.type) {
-+ /* restore MDICNFG to have phy's addr */
-+ case e1000_i210:
-+ case e1000_i211:
-+ mdicnfg = rd32(E1000_MDICNFG);
-+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
-+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
-+ wr32(E1000_MDICNFG, mdicnfg);
-+ break;
-+ default:
-+ break;
-+ }
- return ret_val;
- }
-
-@@ -185,7 +211,7 @@ out:
- s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
- {
- struct e1000_phy_info *phy = &hw->phy;
-- u32 i, mdic = 0;
-+ u32 i, mdicnfg, mdic = 0;
- s32 ret_val = 0;
-
- if (offset > MAX_PHY_REG_ADDRESS) {
-@@ -198,12 +224,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
- * Control register. The MAC will take care of interfacing with the
- * PHY to retrieve the desired data.
- */
-- mdic = (((u32)data) |
-- (offset << E1000_MDIC_REG_SHIFT) |
-- (phy->addr << E1000_MDIC_PHY_SHIFT) |
-- (E1000_MDIC_OP_WRITE));
-+ switch (hw->mac.type) {
-+ case e1000_i210:
-+ case e1000_i211:
-+ mdicnfg = rd32(E1000_MDICNFG);
-+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
-+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
-+ wr32(E1000_MDICNFG, mdicnfg);
-+ mdic = (((u32)data) |
-+ (offset << E1000_MDIC_REG_SHIFT) |
-+ (E1000_MDIC_OP_WRITE));
-+ break;
-+ default:
-+ mdic = (((u32)data) |
-+ (offset << E1000_MDIC_REG_SHIFT) |
-+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
-+ (E1000_MDIC_OP_WRITE));
-+ break;
-+ }
-
- wr32(E1000_MDIC, mdic);
-+ wrfl();
-
- /* Poll the ready bit to see if the MDI read completed
- * Increasing the time out as testing showed failures with
-@@ -227,6 +268,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
- }
-
- out:
-+ switch (hw->mac.type) {
-+ /* restore MDICNFG to have phy's addr */
-+ case e1000_i210:
-+ case e1000_i211:
-+ mdicnfg = rd32(E1000_MDICNFG);
-+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
-+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
-+ wr32(E1000_MDICNFG, mdicnfg);
-+ break;
-+ default:
-+ break;
-+ }
- return ret_val;
- }
-
diff --git a/target/linux/imx6/patches-4.3/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch b/target/linux/imx6/patches-4.3/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch
deleted file mode 100644
index 9d19af5cd7..0000000000
--- a/target/linux/imx6/patches-4.3/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch
+++ /dev/null
@@ -1,260 +0,0 @@
-From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 15 May 2014 00:29:18 -0700
-Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr
-
-Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
-The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
-to this function.
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +-
- drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++---------
- drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++-
- 3 files changed, 58 insertions(+), 26 deletions(-)
-
---- a/drivers/net/ethernet/intel/igb/e1000_82575.c
-+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
-@@ -2153,7 +2153,7 @@ static s32 igb_read_phy_reg_82580(struct
- if (ret_val)
- goto out;
-
-- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
-+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
-
- hw->phy.ops.release(hw);
-
-@@ -2178,7 +2178,7 @@ static s32 igb_write_phy_reg_82580(struc
- if (ret_val)
- goto out;
-
-- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
-+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
-
- hw->phy.ops.release(hw);
-
---- a/drivers/net/ethernet/intel/igb/e1000_phy.c
-+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
-@@ -126,9 +126,8 @@ out:
- * Reads the MDI control regsiter in the PHY at offset and stores the
- * information read to data.
- **/
--s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
-+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
- {
-- struct e1000_phy_info *phy = &hw->phy;
- u32 i, mdicnfg, mdic = 0;
- s32 ret_val = 0;
-
-@@ -147,14 +146,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
- case e1000_i211:
- mdicnfg = rd32(E1000_MDICNFG);
- mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
-- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
-+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
- wr32(E1000_MDICNFG, mdicnfg);
- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
- (E1000_MDIC_OP_READ));
- break;
- default:
- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
-- (phy->addr << E1000_MDIC_PHY_SHIFT) |
-+ (addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_READ));
- break;
- }
-@@ -208,9 +207,8 @@ out:
- *
- * Writes data to MDI control register in the PHY at offset.
- **/
--s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
-+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
- {
-- struct e1000_phy_info *phy = &hw->phy;
- u32 i, mdicnfg, mdic = 0;
- s32 ret_val = 0;
-
-@@ -229,7 +227,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
- case e1000_i211:
- mdicnfg = rd32(E1000_MDICNFG);
- mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
-- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
-+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
- wr32(E1000_MDICNFG, mdicnfg);
- mdic = (((u32)data) |
- (offset << E1000_MDIC_REG_SHIFT) |
-@@ -238,7 +236,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
- default:
- mdic = (((u32)data) |
- (offset << E1000_MDIC_REG_SHIFT) |
-- (phy->addr << E1000_MDIC_PHY_SHIFT) |
-+ (addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_WRITE));
- break;
- }
-@@ -458,7 +456,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
- goto out;
-
- if (offset > MAX_PHY_MULTI_PAGE_REG) {
-- ret_val = igb_write_phy_reg_mdic(hw,
-+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
- IGP01E1000_PHY_PAGE_SELECT,
- (u16)offset);
- if (ret_val) {
-@@ -467,8 +465,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
- }
- }
-
-- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-- data);
-+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
-+ MAX_PHY_REG_ADDRESS & offset, data);
-
- hw->phy.ops.release(hw);
-
-@@ -497,7 +495,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
- goto out;
-
- if (offset > MAX_PHY_MULTI_PAGE_REG) {
-- ret_val = igb_write_phy_reg_mdic(hw,
-+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
- IGP01E1000_PHY_PAGE_SELECT,
- (u16)offset);
- if (ret_val) {
-@@ -506,8 +504,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
- }
- }
-
-- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-- data);
-+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
-+ MAX_PHY_REG_ADDRESS & offset, data);
-
- hw->phy.ops.release(hw);
-
-@@ -2547,8 +2545,9 @@ out:
- }
-
- /**
-- * igb_write_phy_reg_gs40g - Write GS40G PHY register
-+ * igb_write_reg_gs40g - Write GS40G PHY register
- * @hw: pointer to the HW structure
-+ * @addr: phy address to write to
- * @offset: lower half is register offset to write to
- * upper half is page to use.
- * @data: data to write at register offset
-@@ -2556,7 +2555,7 @@ out:
- * Acquires semaphore, if necessary, then writes the data to PHY register
- * at the offset. Release any acquired semaphores before exiting.
- **/
--s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
-+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
- {
- s32 ret_val;
- u16 page = offset >> GS40G_PAGE_SHIFT;
-@@ -2566,10 +2565,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
- if (ret_val)
- return ret_val;
-
-- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
-+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
- if (ret_val)
- goto release;
-- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
-+ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
-
- release:
- hw->phy.ops.release(hw);
-@@ -2577,8 +2576,24 @@ release:
- }
-
- /**
-- * igb_read_phy_reg_gs40g - Read GS40G PHY register
-+ * igb_write_phy_reg_gs40g - Write GS40G PHY register
-+ * @hw: pointer to the HW structure
-+ * @offset: lower half is register offset to write to
-+ * upper half is page to use.
-+ * @data: data to write at register offset
-+ *
-+ * Acquires semaphore, if necessary, then writes the data to PHY register
-+ * at the offset. Release any acquired semaphores before exiting.
-+ **/
-+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
-+{
-+ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
-+}
-+
-+/**
-+ * igb_read_reg_gs40g - Read GS40G PHY register
- * @hw: pointer to the HW structure
-+ * @addr: phy address to read from
- * @offset: lower half is register offset to read to
- * upper half is page to use.
- * @data: data to read at register offset
-@@ -2586,7 +2601,7 @@ release:
- * Acquires semaphore, if necessary, then reads the data in the PHY register
- * at the offset. Release any acquired semaphores before exiting.
- **/
--s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
-+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
- {
- s32 ret_val;
- u16 page = offset >> GS40G_PAGE_SHIFT;
-@@ -2596,10 +2611,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
- if (ret_val)
- return ret_val;
-
-- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
-+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
- if (ret_val)
- goto release;
-- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
-+ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
-
- release:
- hw->phy.ops.release(hw);
-@@ -2607,6 +2622,21 @@ release:
- }
-
- /**
-+ * igb_read_phy_reg_gs40g - Read GS40G PHY register
-+ * @hw: pointer to the HW structure
-+ * @offset: lower half is register offset to read to
-+ * upper half is page to use.
-+ * @data: data to read at register offset
-+ *
-+ * Acquires semaphore, if necessary, then reads the data in the PHY register
-+ * at the offset. Release any acquired semaphores before exiting.
-+ **/
-+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
-+{
-+ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
-+}
-+
-+/**
- * igb_set_master_slave_mode - Setup PHY for Master/slave mode
- * @hw: pointer to the HW structure
- *
---- a/drivers/net/ethernet/intel/igb/e1000_phy.h
-+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
-@@ -62,8 +62,8 @@ void igb_power_up_phy_copper(struct e100
- void igb_power_down_phy_copper(struct e1000_hw *hw);
- s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
- s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);
--s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
--s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
-+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
-+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
- s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
- s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
- s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
-@@ -73,6 +73,8 @@ s32 igb_phy_force_speed_duplex_82580(st
- s32 igb_get_cable_length_82580(struct e1000_hw *hw);
- s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
- s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
-+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
-+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
- s32 igb_check_polarity_m88(struct e1000_hw *hw);
-
- /* IGP01E1000 Specific Registers */
diff --git a/target/linux/imx6/patches-4.3/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch b/target/linux/imx6/patches-4.3/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch
deleted file mode 100644
index b73895b7d4..0000000000
--- a/target/linux/imx6/patches-4.3/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch
+++ /dev/null
@@ -1,308 +0,0 @@
-From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey@gateworks.com>
-Date: Thu, 15 May 2014 12:36:23 -0700
-Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy
-
-If an i210 is configured for 1000BASE-BX link_mode and has an external phy
-specified, then register an mii bus using the external phy address as
-a mask.
-
-An i210 hooked to an external standard phy will be configured with a link_mo
-of SGMII in which case phy ops will be configured and used internall in the
-igb driver for link status. However, in certain cases one might be using a
-backplane SerDes connection to something that talks on the mdio bus but is
-not a standard phy, such as a switch. In this case by registering an mdio
-bus a phy driver can manage the device.
-
-Signed-off-by: Tim Harvey <tharvey@gateworks.com>
----
- drivers/net/ethernet/intel/igb/e1000_82575.c | 15 +++
- drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++
- drivers/net/ethernet/intel/igb/igb_main.c | 168 ++++++++++++++++++++++++++-
- 3 files changed, 185 insertions(+), 5 deletions(-)
-
---- a/drivers/net/ethernet/intel/igb/e1000_82575.c
-+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
-@@ -612,13 +612,25 @@ static s32 igb_get_invariants_82575(stru
- switch (link_mode) {
- case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
- hw->phy.media_type = e1000_media_type_internal_serdes;
-+ if (igb_sgmii_uses_mdio_82575(hw)) {
-+ u32 mdicnfg = rd32(E1000_MDICNFG);
-+ mdicnfg &= E1000_MDICNFG_PHY_MASK;
-+ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT;
-+ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n",
-+ hw->phy.addr);
-+ } else {
-+ hw_dbg("1000BASE_KX");
-+ }
- break;
- case E1000_CTRL_EXT_LINK_MODE_SGMII:
- /* Get phy control interface type set (MDIO vs. I2C)*/
- if (igb_sgmii_uses_mdio_82575(hw)) {
- hw->phy.media_type = e1000_media_type_copper;
- dev_spec->sgmii_active = true;
-+ hw_dbg("SGMII with external MDIO PHY");
- break;
-+ } else {
-+ hw_dbg("SGMII with external I2C PHY");
- }
- /* fall through for I2C based SGMII */
- case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
-@@ -635,8 +647,11 @@ static s32 igb_get_invariants_82575(stru
- hw->phy.media_type = e1000_media_type_copper;
- dev_spec->sgmii_active = true;
- }
-+ hw_dbg("SERDES with external SFP");
-
- break;
-+ } else {
-+ hw_dbg("SERDES");
- }
-
- /* do not change link mode for 100BaseFX */
---- a/drivers/net/ethernet/intel/igb/e1000_hw.h
-+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h
-@@ -27,6 +27,7 @@
- #include <linux/delay.h>
- #include <linux/io.h>
- #include <linux/netdevice.h>
-+#include <linux/phy.h>
-
- #include "e1000_regs.h"
- #include "e1000_defines.h"
-@@ -543,6 +544,12 @@ struct e1000_hw {
- struct e1000_mbx_info mbx;
- struct e1000_host_mng_dhcp_cookie mng_cookie;
-
-+#ifdef CONFIG_PHYLIB
-+ /* Phylib and MDIO interface */
-+ struct mii_bus *mii_bus;
-+ struct phy_device *phy_dev;
-+ phy_interface_t phy_interface;
-+#endif
- union {
- struct e1000_dev_spec_82575 _82575;
- } dev_spec;
---- a/drivers/net/ethernet/intel/igb/igb_main.c
-+++ b/drivers/net/ethernet/intel/igb/igb_main.c
-@@ -41,6 +41,7 @@
- #include <linux/if_vlan.h>
- #include <linux/pci.h>
- #include <linux/pci-aspm.h>
-+#include <linux/phy.h>
- #include <linux/delay.h>
- #include <linux/interrupt.h>
- #include <linux/ip.h>
-@@ -2223,6 +2224,126 @@ static s32 igb_init_i2c(struct igb_adapt
- return status;
- }
-
-+
-+#ifdef CONFIG_PHYLIB
-+/*
-+ * MMIO/PHYdev support
-+ */
-+
-+static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-+{
-+ struct e1000_hw *hw = bus->priv;
-+ u16 out;
-+ int err;
-+
-+ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out);
-+ if (err)
-+ return err;
-+ return out;
-+}
-+
-+static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
-+ u16 val)
-+{
-+ struct e1000_hw *hw = bus->priv;
-+
-+ return igb_write_reg_gs40g(hw, mii_id, regnum, val);
-+}
-+
-+static int igb_enet_mdio_reset(struct mii_bus *bus)
-+{
-+ udelay(300);
-+ return 0;
-+}
-+
-+static void igb_enet_mii_link(struct net_device *netdev)
-+{
-+}
-+
-+/* Probe the mdio bus for phys and connect them */
-+static int igb_enet_mii_probe(struct net_device *netdev)
-+{
-+ struct igb_adapter *adapter = netdev_priv(netdev);
-+ struct e1000_hw *hw = &adapter->hw;
-+ struct phy_device *phy_dev = NULL;
-+ int phy_id;
-+
-+ /* check for attached phy */
-+ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
-+ if (hw->mii_bus->phy_map[phy_id]) {
-+ phy_dev = hw->mii_bus->phy_map[phy_id];
-+ break;
-+ }
-+ }
-+ if (!phy_dev) {
-+ netdev_err(netdev, "no PHY found\n");
-+ return -ENODEV;
-+ }
-+
-+ hw->phy_interface = PHY_INTERFACE_MODE_RGMII;
-+ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev),
-+ igb_enet_mii_link, hw->phy_interface);
-+ if (IS_ERR(phy_dev)) {
-+ netdev_err(netdev, "could not attach to PHY\n");
-+ return PTR_ERR(phy_dev);
-+ }
-+
-+ hw->phy_dev = phy_dev;
-+ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n",
-+ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev));
-+
-+ return 0;
-+}
-+
-+/* Create and register mdio bus */
-+static int igb_enet_mii_init(struct pci_dev *pdev)
-+{
-+ struct mii_bus *mii_bus;
-+ struct net_device *netdev = pci_get_drvdata(pdev);
-+ struct igb_adapter *adapter = netdev_priv(netdev);
-+ struct e1000_hw *hw = &adapter->hw;
-+ int err;
-+
-+ mii_bus = mdiobus_alloc();
-+ if (mii_bus == NULL) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ mii_bus->name = "igb_enet_mii_bus";
-+ mii_bus->read = igb_enet_mdio_read;
-+ mii_bus->write = igb_enet_mdio_write;
-+ mii_bus->reset = igb_enet_mdio_reset;
-+ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-+ pci_name(pdev), hw->device_id + 1);
-+ mii_bus->priv = hw;
-+ mii_bus->parent = &pdev->dev;
-+ mii_bus->phy_mask = ~(1 << hw->phy.addr);
-+
-+ err = mdiobus_register(mii_bus);
-+ if (err) {
-+ printk(KERN_ERR "failed to register mii_bus: %d\n", err);
-+ goto err_out_free_mdiobus;
-+ }
-+ hw->mii_bus = mii_bus;
-+
-+ return 0;
-+
-+err_out_free_mdiobus:
-+ mdiobus_free(mii_bus);
-+err_out:
-+ return err;
-+}
-+
-+static void igb_enet_mii_remove(struct e1000_hw *hw)
-+{
-+ if (hw->mii_bus) {
-+ mdiobus_unregister(hw->mii_bus);
-+ mdiobus_free(hw->mii_bus);
-+ }
-+}
-+#endif /* CONFIG_PHYLIB */
-+
- /**
- * igb_probe - Device Initialization Routine
- * @pdev: PCI device information struct
-@@ -2645,6 +2766,13 @@ static int igb_probe(struct pci_dev *pde
- }
- }
- pm_runtime_put_noidle(&pdev->dev);
-+
-+#ifdef CONFIG_PHYLIB
-+ /* create and register the mdio bus if using ext phy */
-+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
-+ igb_enet_mii_init(pdev);
-+#endif
-+
- return 0;
-
- err_register:
-@@ -2792,6 +2920,10 @@ static void igb_remove(struct pci_dev *p
- struct e1000_hw *hw = &adapter->hw;
-
- pm_runtime_get_noresume(&pdev->dev);
-+#ifdef CONFIG_PHYLIB
-+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
-+ igb_enet_mii_remove(hw);
-+#endif
- #ifdef CONFIG_IGB_HWMON
- igb_sysfs_exit(adapter);
- #endif
-@@ -3105,6 +3237,12 @@ static int __igb_open(struct net_device
- if (!resuming)
- pm_runtime_put(&pdev->dev);
-
-+#ifdef CONFIG_PHYLIB
-+ /* Probe and connect to PHY if using ext phy */
-+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
-+ igb_enet_mii_probe(netdev);
-+#endif
-+
- /* start the watchdog. */
- hw->mac.get_link_status = 1;
- schedule_work(&adapter->watchdog_task);
-@@ -7090,21 +7228,41 @@ void igb_alloc_rx_buffers(struct igb_rin
- static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
- {
- struct igb_adapter *adapter = netdev_priv(netdev);
-+ struct e1000_hw *hw = &adapter->hw;
- struct mii_ioctl_data *data = if_mii(ifr);
-
-- if (adapter->hw.phy.media_type != e1000_media_type_copper)
-+ if (adapter->hw.phy.media_type != e1000_media_type_copper &&
-+ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO))
- return -EOPNOTSUPP;
-
- switch (cmd) {
- case SIOCGMIIPHY:
-- data->phy_id = adapter->hw.phy.addr;
-+ data->phy_id = hw->phy.addr;
- break;
- case SIOCGMIIREG:
-- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
-- &data->val_out))
-- return -EIO;
-+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
-+ if (igb_read_reg_gs40g(&adapter->hw, data->phy_id,
-+ data->reg_num & 0x1F,
-+ &data->val_out))
-+ return -EIO;
-+ } else {
-+ if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
-+ &data->val_out))
-+ return -EIO;
-+ }
- break;
- case SIOCSMIIREG:
-+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
-+ if (igb_write_reg_gs40g(hw, data->phy_id,
-+ data->reg_num & 0x1F,
-+ data->val_in))
-+ return -EIO;
-+ } else {
-+ if (igb_write_phy_reg(hw, data->reg_num & 0x1F,
-+ data->val_in))
-+ return -EIO;
-+ }
-+ break;
- default:
- return -EOPNOTSUPP;
- }
diff --git a/target/linux/imx6/patches-4.3/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch b/target/linux/imx6/patches-4.3/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch
deleted file mode 100644
index c91b519272..0000000000
--- a/target/linux/imx6/patches-4.3/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -309,6 +309,14 @@ endif # RTL8366_SMI
-
- source "drivers/net/phy/b53/Kconfig"
-
-+config GATEWORKS_GW16083
-+ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine"
-+ ---help---
-+ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a
-+ Gateworks Ventana baseboard and provides a 7-port GbE managed
-+ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP
-+ ports"
-+
- endif # PHYLIB
-
- config MICREL_KS8995MA
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -44,6 +44,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
- obj-$(CONFIG_DP83867_PHY) += dp83867.o
- obj-$(CONFIG_STE10XP) += ste10Xp.o
- obj-$(CONFIG_MICREL_PHY) += micrel.o
-+obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o
- obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
- obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
- obj-$(CONFIG_AT803X_PHY) += at803x.o
diff --git a/target/linux/imx6/patches-4.3/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch b/target/linux/imx6/patches-4.3/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch
deleted file mode 100644
index a9214d598f..0000000000
--- a/target/linux/imx6/patches-4.3/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch
+++ /dev/null
@@ -1,56 +0,0 @@
---- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
-@@ -158,6 +158,11 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-+
-+ gw16083: gw16083@52 {
-+ compatible = "gateworks,gw16083";
-+ reg = <0x52>;
-+ };
- };
-
- &i2c3 {
---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-@@ -233,6 +233,11 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-+
-+ gw16083: gw16083@52 {
-+ compatible = "gateworks,gw16083";
-+ reg = <0x52>;
-+ };
- };
-
- &i2c3 {
---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-@@ -226,6 +226,11 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-+
-+ gw16083: gw16083@52 {
-+ compatible = "gateworks,gw16083";
-+ reg = <0x52>;
-+ };
- };
-
- &i2c3 {
---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-@@ -317,6 +317,11 @@
- };
- };
- };
-+
-+ gw16083: gw16083@52 {
-+ compatible = "gateworks,gw16083";
-+ reg = <0x52>;
-+ };
- };
-
- &i2c3 {
diff --git a/target/linux/imx6/patches-4.3/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch b/target/linux/imx6/patches-4.3/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch
deleted file mode 100644
index fa3bf138f6..0000000000
--- a/target/linux/imx6/patches-4.3/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch
+++ /dev/null
@@ -1,22 +0,0 @@
---- a/drivers/i2c/busses/i2c-imx.c
-+++ b/drivers/i2c/busses/i2c-imx.c
-@@ -461,6 +461,8 @@ static int i2c_imx_acked(struct imx_i2c_
- {
- if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
- dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
-+ if (i2c_imx->adapter.retries)
-+ return -EAGAIN;
- return -EIO; /* No ACK */
- }
-
-@@ -1010,6 +1012,10 @@ static int i2c_imx_probe(struct platform
- i2c_imx->adapter.nr = pdev->id;
- i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
- i2c_imx->base = base;
-+ if (of_machine_is_compatible("gw,ventana") && phy_addr == 0x021a0000) {
-+ dev_info(&pdev->dev, "Adding retries for Ventana GSC\n");
-+ i2c_imx->adapter.retries = 3;
-+ }
-
- /* Get I2C clock */
- i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
diff --git a/target/linux/imx6/patches-4.3/208-sky2-allow-mac-to-come-from-dt.patch b/target/linux/imx6/patches-4.3/208-sky2-allow-mac-to-come-from-dt.patch
deleted file mode 100644
index 9a94212235..0000000000
--- a/target/linux/imx6/patches-4.3/208-sky2-allow-mac-to-come-from-dt.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/drivers/net/ethernet/marvell/sky2.c
-+++ b/drivers/net/ethernet/marvell/sky2.c
-@@ -4812,7 +4812,24 @@ static struct net_device *sky2_init_netd
- * 1) from device tree data
- * 2) from internal registers set by bootloader
- */
-- iap = of_get_mac_address(hw->pdev->dev.of_node);
-+
-+ iap = NULL;
-+ if (IS_ENABLED(CONFIG_OF)) {
-+ struct device_node *np;
-+ np = of_find_node_by_path("/aliases");
-+ if (np) {
-+ const char *path = of_get_property(np, "sky2", NULL);
-+ if (path)
-+ np = of_find_node_by_path(path);
-+ if (np)
-+ path = of_get_mac_address(np);
-+ if (path)
-+ iap = (unsigned char *) path;
-+ }
-+ }
-+
-+ if (!iap)
-+ iap = of_get_mac_address(hw->pdev->dev.of_node);
- if (iap)
- memcpy(dev->dev_addr, iap, ETH_ALEN);
- else
diff --git a/target/linux/imx6/patches-4.3/209-ARM-imx-ventana-add-sky2-alias.patch b/target/linux/imx6/patches-4.3/209-ARM-imx-ventana-add-sky2-alias.patch
deleted file mode 100644
index 490e015eb0..0000000000
--- a/target/linux/imx6/patches-4.3/209-ARM-imx-ventana-add-sky2-alias.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
-@@ -15,6 +15,7 @@
- /* these are used by bootloader for disabling nodes */
- aliases {
- ethernet1 = &eth1;
-+ sky2 = &eth1;
- led0 = &led0;
- led1 = &led1;
- led2 = &led2;
---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
-@@ -15,6 +15,7 @@
- /* these are used by bootloader for disabling nodes */
- aliases {
- ethernet1 = &eth1;
-+ sky2 = &eth1;
- led0 = &led0;
- led1 = &led1;
- led2 = &led2;