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| author | Luka Perkov <luka@openwrt.org> | 2014-02-12 00:46:02 +0000 |
|---|---|---|
| committer | Luka Perkov <luka@openwrt.org> | 2014-02-12 00:46:02 +0000 |
| commit | ef5c3bbb5f966864be63cbe5007578c6739c9546 (patch) | |
| tree | a47f6c9f42f95bcecb70fa2c3c3ea6a64fa4e196 /target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | |
| parent | 3203599a7d8be39bb01e1dc425bfee14cc74aa00 (diff) | |
| download | upstream-ef5c3bbb5f966864be63cbe5007578c6739c9546.tar.gz upstream-ef5c3bbb5f966864be63cbe5007578c6739c9546.tar.bz2 upstream-ef5c3bbb5f966864be63cbe5007578c6739c9546.zip | |
imx6: drop 3.12 support
Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 39574
Diffstat (limited to 'target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch deleted file mode 100644 index 3dce8d9871..0000000000 --- a/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 8d6a35fb13406f87d926fffeee0d70360ce3077d Mon Sep 17 00:00:00 2001 -From: Sean Cross <xobs@kosagi.com> -Date: Thu, 26 Sep 2013 11:24:46 +0800 -Subject: [PATCH] ARM: imx6q: Add PCIe bits to GPR syscon definition - -PCIe requires additional bits be defined for GPR8 and GPR12. - -Signed-off-by: Sean Cross <xobs@kosagi.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -@@ -241,6 +241,12 @@ - - #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) - -+#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) -+#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) -+ - #define IMX6Q_GPR9_TZASC2_BYP BIT(1) - #define IMX6Q_GPR9_TZASC1_BYP BIT(0) - -@@ -273,7 +279,9 @@ - #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) - #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) - #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) -+#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) - #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) -+#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) - - #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) - #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) |