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author | Luka Perkov <luka@openwrt.org> | 2013-10-29 02:19:09 +0000 |
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committer | Luka Perkov <luka@openwrt.org> | 2013-10-29 02:19:09 +0000 |
commit | e291d89f5c9c3d0de27c73d5f775964fc701aca6 (patch) | |
tree | 48c43554bbefd5a7697ab36dfb843b309209eea6 /target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch | |
parent | a9f1f034386bbd54d70524718e5017b35cc55f8b (diff) | |
download | upstream-e291d89f5c9c3d0de27c73d5f775964fc701aca6.tar.gz upstream-e291d89f5c9c3d0de27c73d5f775964fc701aca6.tar.bz2 upstream-e291d89f5c9c3d0de27c73d5f775964fc701aca6.zip |
imx6: add initial 3.12 support
Signed-off-by: Luka Perkov <luka@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38574 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch')
-rw-r--r-- | target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch b/target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch new file mode 100644 index 0000000000..85212ca010 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch @@ -0,0 +1,60 @@ +From 64990a431469a58b2949aca5be9d69e220d53892 Mon Sep 17 00:00:00 2001 +From: Nicolin Chen <b42378@freescale.com> +Date: Fri, 23 Aug 2013 19:20:34 +0800 +Subject: [PATCH] ARM: imx6q: Add pll4_audio_div to clock tree + +There's a pll4_audio_div clock, an extra divider for pll4, missing +in current clock tree, thus add it. + +Signed-off-by: Nicolin Chen <b42378@freescale.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/clk-imx6q.c | 9 +++++---- + 2 files changed, 6 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -182,7 +182,7 @@ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; + static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; + static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; + static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; +-static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; ++static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; + static const char *gpu_axi_sels[] = { "axi", "ahb", }; + static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; + static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; +@@ -196,7 +196,7 @@ static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di + static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; + static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; + static const char *pcie_axi_sels[] = { "axi", "ahb", }; +-static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", }; ++static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; + static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; + static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; + static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; +@@ -205,7 +205,7 @@ static const char *vdo_axi_sels[] = { "axi", "ahb", }; + static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; + static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", + "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", +- "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; ++ "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; + static const char *cko2_sels[] = { + "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", + "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", +@@ -251,7 +251,7 @@ enum mx6q_clks { + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, +- spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max ++ spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max + }; + + static struct clk *clk[clk_max]; +@@ -359,6 +359,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); + + clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); ++ clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); + clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); + clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); + |