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| author | Luka Perkov <luka@openwrt.org> | 2013-09-25 18:07:24 +0000 |
|---|---|---|
| committer | Luka Perkov <luka@openwrt.org> | 2013-09-25 18:07:24 +0000 |
| commit | d4680767c63c406b3e53c7056e521489b6b91fe9 (patch) | |
| tree | 555f8549af00dc3ce479553c47ed7e67151c0fee /target/linux/imx6/patches-3.10/112-gw51xx.patch | |
| parent | 88ac0fc90aa022bd580b86aa4fda8670b8cd01be (diff) | |
| download | upstream-d4680767c63c406b3e53c7056e521489b6b91fe9.tar.gz upstream-d4680767c63c406b3e53c7056e521489b6b91fe9.tar.bz2 upstream-d4680767c63c406b3e53c7056e521489b6b91fe9.zip | |
imx6: add support for gw51xx
The Gateworks GW51xx family of products is based on the Freescale
i.MX6DL SoC and offers a small form-factor with peripherals such as:
- i.MX6DL 512MB DDR3
- 256MB NAND FLASH
- 1x PCIe
- 1x USB EHCI (to PCIe socket)
- 1x USB OTG
- HDMI out
- Analog Video in
- Gateworks System Controller
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38189 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/imx6/patches-3.10/112-gw51xx.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.10/112-gw51xx.patch | 161 |
1 files changed, 161 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.10/112-gw51xx.patch b/target/linux/imx6/patches-3.10/112-gw51xx.patch new file mode 100644 index 0000000000..1749c28491 --- /dev/null +++ b/target/linux/imx6/patches-3.10/112-gw51xx.patch @@ -0,0 +1,161 @@ +--- a/arch/arm/boot/dts/imx6dl.dtsi ++++ b/arch/arm/boot/dts/imx6dl.dtsi +@@ -80,6 +80,95 @@ + }; + }; + ++ gpmi-nand { ++ pinctrl_gpmi_nand_1: gpmi-nand-1 { ++ fsl,pins = < ++ MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 ++ MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 ++ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 ++ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 ++ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 ++ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 ++ MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 ++ MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 ++ MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 ++ MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 ++ MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 ++ MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 ++ MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 ++ MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 ++ MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 ++ MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 ++ MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 ++ MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 ++ MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 ++ >; ++ }; ++ ++ /* No strobe */ ++ pinctrl_gpmi_nand_2: gpmi-nand-2 { ++ fsl,pins = < ++ MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 ++ MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 ++ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 ++ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 ++ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 ++ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 ++ MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 ++ MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 ++ MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 ++ MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 ++ MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 ++ MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 ++ MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 ++ MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 ++ MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 ++ MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 ++ MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 ++ MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 ++ >; ++ }; ++ }; ++ ++ i2c1 { ++ pinctrl_i2c1_1: i2c1grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 ++ MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 ++ >; ++ }; ++ }; ++ ++ i2c2 { ++ pinctrl_i2c2_1: i2c2grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 ++ MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ pinctrl_i2c2_2: i2c2grp-2 { ++ fsl,pins = < ++ MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 ++ MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ }; ++ ++ i2c3 { ++ pinctrl_i2c3_1: i2c3grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 ++ MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 ++ >; ++ }; ++ pinctrl_i2c3_2: i2c3grp-2 { ++ fsl,pins = < ++ MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 ++ MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ++ >; ++ }; ++ }; ++ + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < +@@ -87,6 +176,36 @@ + MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; ++ pinctrl_uart1_2: uart1grp-2 { ++ fsl,pins = < ++ MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 ++ MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 ++ >; ++ }; ++ }; ++ ++ uart2 { ++ pinctrl_uart2_1: uart2grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 ++ MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 ++ >; ++ }; ++ pinctrl_uart2_2: uart2grp-2 { ++ fsl,pins = < ++ MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 ++ MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 ++ >; ++ }; ++ }; ++ ++ uart3 { ++ pinctrl_uart3_1: uart3grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 ++ MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 ++ >; ++ }; + }; + + uart4 { +@@ -97,6 +216,15 @@ + >; + }; + }; ++ ++ uart5 { ++ pinctrl_uart5_1: uart5grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 ++ MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ++ >; ++ }; ++ }; + + usbotg { + pinctrl_usbotg_2: usbotggrp-2 { +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ + imx6q-arm2.dtb \ + imx6q-gw5400-a.dtb \ + imx6q-gw54xx.dtb \ ++ imx6dl-gw51xx.dtb \ + imx6q-sabreauto.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb \ |